KR20010003998A - Method of forming gate for semiconductor device - Google Patents
Method of forming gate for semiconductor device Download PDFInfo
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- KR20010003998A KR20010003998A KR1019990024583A KR19990024583A KR20010003998A KR 20010003998 A KR20010003998 A KR 20010003998A KR 1019990024583 A KR1019990024583 A KR 1019990024583A KR 19990024583 A KR19990024583 A KR 19990024583A KR 20010003998 A KR20010003998 A KR 20010003998A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트 형성을 위한 식각후 진행되는 산화공정시, 폴리실리콘을 효과적으로 산화시키면서 금속의 산화를 억제할 수 있는 반도체 소자의 게이트 형성방법을 제공한다.The present invention provides a method of forming a gate of a semiconductor device capable of suppressing oxidation of a metal while effectively oxidizing polysilicon during an oxidation process performed after etching for forming a gate.
본 발명에 따른 반도체 소자의 게이트 형성방법은 다음과 같다. 먼저, 반도체 기판 상에 게이트 산화막을 형성하고, 게이트 산화막 상에 게이트 물질로서 폴리실리콘막, 확산방지용 배리어 금속막 및 금속막을 순차적으로 형성한다. 그런 다음, 금속막, 배리어 금속막 및 폴리실리콘막을 식각하여 게이트를 형성하고, 게이트가 형성된 기판을 습식산화로 산화시켜, 상기 폴리실리콘막의 양 측 표면에 산화막을 형성함과 동시에 게이트 산화막 표면의 손상을 회복시킨다. 본 실시예에서, 습식산화는 H2SO4를 기본으로 하는 화학용액을 이용하여 70 내지 100℃, 바람직하게 80 내지 90℃의 저온에서 진행한다.A gate forming method of a semiconductor device according to the present invention is as follows. First, a gate oxide film is formed on a semiconductor substrate, and a polysilicon film, a diffusion barrier metal film, and a metal film are sequentially formed as a gate material on the gate oxide film. Then, a gate is formed by etching the metal film, the barrier metal film, and the polysilicon film, and the substrate on which the gate is formed is oxidized by wet oxidation to form oxide films on both surfaces of the polysilicon film, and at the same time damage the gate oxide film surface. To recover. In this embodiment, the wet oxidation is carried out at a low temperature of 70 to 100 ℃, preferably 80 to 90 ℃ using a chemical solution based on H 2 SO 4 .
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리실리콘막/배리어 금속막/텅스텐막의 적층구조로 이루어진 반도체 소자의 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device having a laminated structure of a polysilicon film / barrier metal film / tungsten film.
일반적으로, 반도체 소자의 게이트 물질로서 폴리실리콘막이 사용되는데, 이러한 폴리실리콘막의 패터닝 후에, 식각 데미지, 특히 게이트 산화막의 손상을 방지하기 위하여, O2개스 분위기에서 건식산화(dry oxidation)로 LDD(lightly doped drain) 산화를 진행하였다.In general, a polysilicon film is used as a gate material of a semiconductor device, and after patterning of the polysilicon film, in order to prevent etching damage, particularly damage to the gate oxide film, LDD (lightly) by dry oxidation in an O 2 gas atmosphere doped drain) oxidation was carried out.
한편, 반도체 소자의 집적도가 증가되면서, 게이트의 저항 (resistivity)이 중요한 요소로서 작용하기 때문에, 0.15㎛ 이하의 디자인 룰을 갖는 반도체 소자의 경우에는 게이트의 저항특성을 향상시키기 위하여, 게이트를 폴리실리콘막과 텅스텐막과 같은 저저항 금속막의 적층구조로 형성하였다. 이때, 텅스텐막과 폴리실리콘막 사이에 확산방지를 위한 배리어 금속막으로서 티타늄질화막(TiN) 또는 텅스텐 질화막(WN) 개재하여 형성한다.On the other hand, since the resistance of the gate acts as an important factor as the degree of integration of the semiconductor device increases, in the case of a semiconductor device having a design rule of 0.15 μm or less, the gate is made of polysilicon to improve the resistance characteristics of the gate. The film was formed in a laminate structure of a low resistance metal film such as a tungsten film. At this time, a barrier metal film for preventing diffusion between the tungsten film and the polysilicon film is formed through a titanium nitride film (TiN) or a tungsten nitride film (WN).
그러나, 상기한 바와 같은 텅스텐-폴리실리콘 구조의 게이트 형성시, 게이트의 패터닝 후 식각 데미지를 회복하기 위하여 LDD 산화를 진행하게 되면, 텅스텐, TiN, WN과 같은 금속들이 심하게 산화되어, 게이트의 변형이 야기되는 문제가 발생한다.However, in the formation of the gate of the tungsten-polysilicon structure as described above, if LDD oxidation is performed to recover the etch damage after patterning of the gate, metals such as tungsten, TiN, and WN are severely oxidized, so that deformation of the gate is prevented. The problem that arises arises.
이러한 문제를 해결하기 위하여, 최근에는 게이트 패턴 형성을 위한 식각후 O2와 H2의 혼합개스 분위기에서 폴리실리콘막을 선택적으로 건식산화시키는 선택산화공정이 제시되고 있으나, 재현성을 확보하기가 어려울 뿐만 아니라 실제의 공정에 적용하는데 어려움이 있다.In order to solve this problem, recently, a selective oxidation process for selectively dry oxidizing a polysilicon film in a mixed gas atmosphere of O 2 and H 2 after etching to form a gate pattern has been proposed, but it is difficult to secure reproducibility. Difficult to apply to the actual process.
또한, 상기한 바와 같은 O2개스 또는 O2와 H2의 혼합개스를 이용한 건식산화는 일반적으로 800 내지 1,000℃의 비교적 고온에서 진행되기 때문에, 고온 공정에 따른 불순물들의 이동에 의해 소자의 특성이 저하되는 문제가 있다.In addition, dry oxidation using the O 2 gas or the mixed gas of O 2 and H 2 as described above generally proceeds at a relatively high temperature of 800 to 1,000 ℃, the characteristics of the device by the movement of impurities in the high temperature process There is a problem of deterioration.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 게이트의 형성을 위한 식각후 진행되는 산화공정시, 폴리실리콘을 효과적으로 산화시키면서 금속의 산화를 억제할 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned conventional problems, a method of forming a gate of a semiconductor device that can suppress the oxidation of the metal while effectively oxidizing the polysilicon during the oxidation process proceeds after etching for the formation of the gate. The purpose is to provide.
또한, 본 발명은 상기한 산화공정을 비교적 저온에서 진행함으로써 불순물 이동으로 인한 소자 특성 저하를 방지할 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다.In addition, an object of the present invention is to provide a method for forming a gate of a semiconductor device that can prevent the deterioration of device characteristics due to impurity movement by proceeding the above oxidation process at a relatively low temperature.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 : 반도체 기판 11 : 게이트 산화막10 semiconductor substrate 11 gate oxide film
12 : 폴리실리콘막 13 : 배리어 금속막12 polysilicon film 13 barrier metal film
14 : 텅스텐막 100 : 게이트14: tungsten film 100: gate
15 : 포토레지스트막 패턴15: photoresist film pattern
16 : 산화막16: oxide film
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자의 게이트 형성방법은 다음과 같다. 먼저, 반도체 기판 상에 게이트 산화막을 형성하고, 게이트 산화막 상에 게이트 물질로서 폴리실리콘막, 확산방지용 배리어 금속막 및 금속막을 순차적으로 형성한다. 그런 다음, 금속막, 배리어 금속막 및 폴리실리콘막을 식각하여 게이트를 형성하고, 게이트가 형성된 기판을 습식산화로 산화시켜, 상기 폴리실리콘막의 양 측 표면에 산화막을 형성함과 동시에 게이트 산화막 표면의 손상을 회복시킨다.In order to achieve the above object of the present invention, the gate forming method of a semiconductor device according to the present invention is as follows. First, a gate oxide film is formed on a semiconductor substrate, and a polysilicon film, a diffusion barrier metal film, and a metal film are sequentially formed as a gate material on the gate oxide film. Then, a gate is formed by etching the metal film, the barrier metal film, and the polysilicon film, and the substrate on which the gate is formed is oxidized by wet oxidation to form oxide films on both surfaces of the polysilicon film, and at the same time damage the gate oxide film surface. To recover.
본 실시예에서, 습식산화는 H2SO4를 기본으로 하는 화학용액을 이용하여 70 내지 100℃, 바람직하게 80 내지 90℃의 저온에서 진행한다.In this embodiment, the wet oxidation is carried out at a low temperature of 70 to 100 ℃, preferably 80 to 90 ℃ using a chemical solution based on H 2 SO 4 .
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(10) 상에 게이트 산화막(11)을 형성하고, 게이트 산화막(11) 상부에 게이트 물질로서, 도핑된 폴리실리콘막(12), 확산방지용 배리어 금속막(13) 및 저저항 금속막으로서 텅스텐막(14)을 순차적으로 형성한다. 여기서, 배리어 금속막(13)은 티타늄 질화막 또는 텅스텐 질화막으로 형성한다. 또한, 텅스텐막(14) 대신에 금속 실리사이드막을 형성할 수 있다. 여기서, 금속 실리사이드막의 금속은 코발트, 텅스텐, 및 티타늄으로 이루어진 그룹으로부터 선택되는 하나의 금속이다. 그런 다음, 텅스텐막(14) 상에 포토리소그라피로 게이트용 포토레지스트막 패턴(15)을 형성한다.Referring to FIG. 1A, a gate oxide film 11 is formed on a semiconductor substrate 10, a doped polysilicon film 12 and a diffusion barrier metal layer 13 as a gate material on the gate oxide film 11. And the tungsten film 14 is sequentially formed as a low resistance metal film. Here, the barrier metal film 13 is formed of a titanium nitride film or a tungsten nitride film. In addition, a metal silicide film can be formed in place of the tungsten film 14. Here, the metal of the metal silicide film is one metal selected from the group consisting of cobalt, tungsten, and titanium. Then, the photoresist film pattern 15 for gate is formed on the tungsten film 14 by photolithography.
그리고 나서, 포토레지스트막 패턴(15)을 식각 마스크로하여 텅스텐막(14), 배리어 금속막(13) 및 폴리실리콘막(12)을 식각하여, 도 1b에 도시된 바와 같이, 폴리실리콘막(12A), 배리어 금속막(13A) 및 텅스텐막(14)의 적층구조로 이루어진 게이트(100)를 형성한다. 그런 다음, 공지된 방법으로 포토레지스트막 패턴(15)을 제거한다.Then, the tungsten film 14, the barrier metal film 13, and the polysilicon film 12 are etched using the photoresist film pattern 15 as an etching mask, and as shown in FIG. 1B, the polysilicon film ( 12A), the barrier metal film 13A and the tungsten film 14 are formed with a stacked structure 100. Then, the photoresist film pattern 15 is removed by a known method.
도 1c를 참조하면, 식각 데미지를 회복하기 위하여, 도 1b의 구조를 H2SO4를 기본으로 하는 화학용액을 이용한 습식산화로 70 내지 100℃, 바람직하게 80 내지 90℃의 비교적 저온에서 LDD 산화를 진행하여, 식각된 폴리실리콘막(12A)의 양 측 표면에 산화막(16)을 형성함과 동시에, 게이트 산화막(11)의 손상을 회복시킨다. 즉, H2SO4를 기본으로 하는 화학용액은 비교적 저온에서 폴리실리콘막의 표면을 산화시키는 특성을 갖는다. 따라서, 본 발명에서는 종래의 O2개스를 이용한 건식산화 대신에, H2SO4를 기본으로 하는 화학용액을 이용하여 습식산화를 진행함으로써, 배리어 금속막(13A) 및 텅스텐막(13A)과 같은 금속의 산화를 억제하면서, 폴리실리콘막(12A)의 표면을 산화시킴과 더불어 게이트 산화막(11)의 손상을 회복할 수 있게 된다.Referring to FIG. 1C, in order to recover the etch damage, the structure of FIG. 1B is wet oxidation using a chemical solution based on H 2 SO 4 , and LDD oxidation at a relatively low temperature of 70 to 100 ° C., preferably 80 to 90 ° C. By proceeding, the oxide films 16 are formed on both surfaces of the etched polysilicon film 12A, and the damage of the gate oxide film 11 is restored. That is, the chemical solution based on H 2 SO 4 has a characteristic of oxidizing the surface of the polysilicon film at a relatively low temperature. Therefore, in the present invention, instead of the conventional dry oxidation using O 2 gas, wet oxidation is performed using a chemical solution based on H 2 SO 4 , such as the barrier metal film 13A and the tungsten film 13A. While suppressing the oxidation of the metal, the surface of the polysilicon film 12A can be oxidized and damage to the gate oxide film 11 can be recovered.
상기한 본 발명에 의하면, 폴리실리콘막/배리어 금속막/텅스텐막의 적층구조로 이루어진 게이트 형성을 위한 식각 후, 식각 데미지를 회복하기 위한 산화공정을 H2SO4를 기본으로 하는 습식산화로 비교적 저온에서 진행함으로써, 금속의 산화를 억제하면서, 폴리실리콘막의 표면을 용이하게 산화시킴과 더불어 게이트 산화막의 손상을 회복시킬 수 있게 된다.According to the present invention described above, after etching to form a gate formed of a laminated structure of a polysilicon film / barrier metal film / tungsten film, an oxidation process for recovering etching damage is performed at a relatively low temperature by wet oxidation based on H 2 SO 4 . By proceeding at, it is possible to easily oxidize the surface of the polysilicon film while restraining the oxidation of the metal, and to recover damage to the gate oxide film.
또한, 비교적 저온에서 습식산화를 진행하기 때문에, 산화공정시 불순물 이동이 방지되어 소자 특성이 향상되는 효과를 얻을 수 있다.In addition, since wet oxidation is performed at a relatively low temperature, impurity migration can be prevented during the oxidation process, thereby improving the device characteristics.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399930B1 (en) * | 2001-12-31 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming gate for semiconductor device |
| KR100806136B1 (en) * | 2002-06-05 | 2008-02-22 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device with metal gate electrode |
| KR100806135B1 (en) * | 2002-05-30 | 2008-02-22 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device having a metal gate electrode |
| KR100943449B1 (en) * | 2009-08-18 | 2010-02-22 | 동국대학교 산학협력단 | Method of gate dielectric formation using low temperature curing and method for manufacturing organic thin film transistor using the same |
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1999
- 1999-06-28 KR KR10-1999-0024583A patent/KR100372818B1/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399930B1 (en) * | 2001-12-31 | 2003-09-29 | 주식회사 하이닉스반도체 | Method of forming gate for semiconductor device |
| KR100806135B1 (en) * | 2002-05-30 | 2008-02-22 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device having a metal gate electrode |
| KR100806136B1 (en) * | 2002-06-05 | 2008-02-22 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device with metal gate electrode |
| KR100943449B1 (en) * | 2009-08-18 | 2010-02-22 | 동국대학교 산학협력단 | Method of gate dielectric formation using low temperature curing and method for manufacturing organic thin film transistor using the same |
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