KR20000033842A - Thin film transistor substrate for liquid crystal display device with improved pad reliability and manufacturing method thereof - Google Patents

Abstract

In manufacturing a thin film transistor substrate for a liquid crystal display device, a data pad line is formed at the time of forming a gate line, and a data line is formed of a triple layer in which a lower chromium layer and an aluminum layer are covered with an upper chromium layer on the gate insulating film. Next, a protective layer is stacked and a contact hole for exposing the gate pad portion, the data pad portion, the data line and the gate line end portions of the data pad line is formed on the protective layer, and the ITO is stacked and patterned thereon to support the auxiliary gate pad and the auxiliary data. An auxiliary data line connected to the pad and the data line and the data pad line at the same time is formed. In this case, since the data pad line is positioned under the gate insulating film, the portion exposed to air even after the liquid crystal injection and sealing is conventionally covered with the gate insulating film, and the ITO and aluminum can be avoided while avoiding contact between the ITO and aluminum. Redundancy can be formed and ITO can be covered with gate pads and data pads to ensure reliability.

Description

Thin film transistor substrate for liquid crystal display device with improved pad reliability and manufacturing method thereof

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof.

A liquid crystal display is an apparatus that displays an image in a manner of controlling the transmittance of light by injecting a liquid crystal material between two substrates and changing a voltage applied between two electrodes formed on the substrate.

In such a liquid crystal display, a gate wiring, a data wiring, a thin film transistor pixel electrode may be formed on one substrate, a common electrode may be formed on the remaining substrate, or a common electrode may be formed on the same substrate as the pixel electrode.

The liquid crystal display is driven by applying a scan signal through a gate line and an image signal through a data line to apply a constant potential to a pixel electrode through a thin film transistor of a specific pixel. At this time, the scan signal and the image signal are applied from the drive integrated circuit connected through the gate pad formed at the beginning of the gate line and the data pad formed at the beginning of the data line.

By the way, in the conventional thin film transistor substrate for liquid crystal display devices, a data pad is formed with aluminum, aluminum-neodymium alloy, etc., and this is exposed directly outside, and there exists a problem in pad reliability. However, although the pad portion may be protected by an anisotropic conductive film (ACF) used to bond the integrated circuit and the pad, the pad portion may not be covered by the ACF and the portion of the data line outside the liquid crystal sealing line may not be protected.

In addition, the thin film transistor is formed by sequentially stacking an insulating film, an amorphous silicon layer, and a highly doped amorphous silicon layer on the gate electrode, and simultaneously patterning the amorphous silicon layer and the doped amorphous silicon layer to form an island thereon, together with a data line thereon. After the source electrode and the drain electrode are formed, an N + doped amorphous silicon layer which is not covered by the data line and the source electrode and the drain electrode is formed by etching. The data in the process of etching the N + doped amorphous silicon layer Aluminum, a line material, has a problem of being damaged by exposure to chlorine (Cl) gas.

The technical problem to be achieved by the present invention is to ensure the reliability of the data pad.

Another object of the present invention is to prevent the data line from being damaged during the thin film transistor formation process.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

2, 3, and 4 are cross-sectional views taken along lines II-II ', III-III', and IV-IV 'of FIG. 1, respectively.

5A, 6A, and 7A are layout views of a thin film transistor substrate according to a procedure of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

5B, 5C, and 5D are cross-sectional views taken along lines Vb-Vb ', Vc-Vc', and Vd-Vd 'of FIG. 5A, respectively.

6B, 6C, and 6D are cross-sectional views taken along lines VIb-VIb ', VIc-VIc', and VId-VId 'of FIG. 6A, respectively.

7B, 7C, and 7D are cross-sectional views taken along the lines 'b-'b', 'c-'c', and 'd-'d' of FIG. 7A, respectively.

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

9, 10, and 11 are cross-sectional views taken along the lines VII-VII ', VII-XI', and XI-XI 'of FIG. 8, respectively.

12A, 13A, and 14A are layout views of a thin film transistor substrate according to a procedure of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

12B, 12C, and 12D are cross-sectional views taken along lines XIIb-XIIb ', XIIc-XIIc', and XIId-XIId 'of FIG. 12A, respectively.

13B, 13C, and 13D are cross-sectional views taken along lines XIIIb-XIIIb ', XIIIc-XIIIc', and XIIId-XIIId 'of FIG. 13A, respectively.

14B, 14C, and 14D are cross-sectional views taken along lines XIVb-XIVb ', XIVc-XIVc', and XIVd-XIVd ', respectively, of FIG. 14A.

In order to solve the above technical problem, in the present invention, data lines formed outside the sealing line are separated together to be connected to the data pad and formed together at the time of forming the gate line, and the data line is formed of a triple layer of chromium, aluminum, and chromium. The chromium layer surrounds the aluminum layer and forms an auxiliary pattern on the protective layer.

Specifically, the first and second contact holes covering the gate line formed on the substrate, the data pad line formed on the substrate and separated from the gate line, the gate line and the data pad line, and exposing a part of the data pad line are provided. Branch is connected to a gate insulating film, a data line formed on the gate insulating film, a gate electrode connected to the gate line, a channel layer formed on the gate insulating film on the gate electrode, a source layer and a channel layer connected to the channel layer, and the data line. A thin film transistor including a drain electrode, a pixel electrode connected to the drain electrode, a data line, a pixel electrode, and a third and fourth contact hole and a data line covering the first and second contact holes, respectively. A protective film having a fifth contact hole to be exposed; A fourth pad connected to the data line through the contact hole has been provided a thin film transistor substrate including an auxiliary data line that is connected to the data line through the fifth contact hole.

At this time, the data line is a lower chromium layer, an aluminum or aluminum-neodymium alloy layer, the upper chromium layer is continuously stacked, the upper chromium layer can completely cover the first metal layer and the lower chromium layer, the protective film The auxiliary gate pad covering the gate pad portion exposed through the contact hole and the auxiliary data pad covering the data pad line may be further formed. The gate line and the data pad line may be formed by sequentially stacking a chromium layer and an aluminum-neodymium alloy layer. The auxiliary gate pad, the auxiliary data pad, and the auxiliary data line may be formed of indium tin oxide (ITO), and the chromium layer and It may be formed in contact with the chromium layer of the data pad line.

The data line may be formed only inside the sealing line, and the second and fourth contact holes may be integrally formed with the fifth contact hole closest to the data pad line.

In addition, a data line shorting bar connecting the data lines into one, an auxiliary gate pad formed on the passivation layer and connected to the gate line, an auxiliary data pad connected to the data line, and first and second gate lines alternately connected to the gate line. The apparatus may further include a first to third auxiliary data line shorting bar connected to the shorting bar and the data pad line in alternating manner, and may include an auxiliary data line, an auxiliary gate pad, an auxiliary data pad, a gate line shorting bar, and an auxiliary data line shorting bar. May be formed of aluminum, and the data line and the data line shorting bar may be formed of chromium.

A thin film transistor substrate having such a structure includes forming a gate line and a data pad line together on an insulating substrate, sequentially laminating a gate insulating film, an amorphous silicon layer, and a doped amorphous silicon layer, and combining the amorphous silicon layer and the doped amorphous silicon layer together. Patterning to form a semiconductor pattern, forming a data line, a source electrode, a drain electrode and a pixel electrode, laminating a protective film, and forming a contact hole exposing a portion of the data line and the data pad line on the protective film and the gate insulating film. And forming an auxiliary data line connected to the data line and the data pad line through the contact hole on the passivation layer.

In this case, the forming of the data line, the source electrode, the drain electrode, and the pixel electrode may be performed by sequentially stacking and patterning the first metal layer and the second metal layer to form a double layer of the data line, and stacking and patterning the first metal layer again. Forming a source electrode, a drain electrode, and a pixel electrode together with an upper layer covering the double layer of the data line; forming a first metal layer in chromium; and forming a second metal layer in aluminum or an aluminum-neodynium alloy. Forming the gate line and the data pad line together may be a step of depositing and patterning the chromium layer, the aluminum, or the aluminum-neodynium alloy layer in sequence. Further, in the forming of the contact hole, the contact hole exposing the gate pad portion of the gate line and the data pad portion of the data pad line may be further formed, and the auxiliary gate pad and the auxiliary data pad may be further formed in the step of forming the auxiliary data line. And forming a contact hole, and then etching the aluminum or aluminum-neodynium alloy layer exposed through the contact hole, wherein the auxiliary data line, the auxiliary gate pad, and the auxiliary data pad are formed of ITO. In the forming of the data line, the source electrode, the drain electrode, and the pixel electrode, a data line shorting bar connecting the data lines together may be further formed, and one end of the gate line may be exposed in the forming of the contact hole. And a contact hole exposing a far end from the gate line of the data pad line. In the forming of the auxiliary data line, the auxiliary gate pad, and the auxiliary data pad, the gate line shorting bar connected to the gate line and the far end of the data pad line are exposed through the contact hole exposing one end of the gate line. A data line auxiliary shorting bar connected to the data pad line may be further formed through the contact hole. The gate line shorting bar may be two lines of metal lines alternately connected to the gate line, and the data line auxiliary shorting bar may be three lines of metal lines alternately connected to the data line, the data line may be formed of chromium, and the auxiliary data line, The auxiliary gate pad, the auxiliary data pad, the gate line shorting bar, and the data line auxiliary shorting bar may be formed of aluminum.

Next, a structure and a manufacturing method of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, and FIGS. 2, 3, and 4 are lines II-II ', III-III', and IV- of FIG. 1, respectively. It is sectional drawing about IV 'line.

First, the structure will be described.

The gate line 200 is formed in the horizontal direction on the transparent insulating substrate 10, and two common electrode lines 300 are formed in parallel with the gate line 200, and the data pad line 220 in the vertical direction. Is formed. In this case, the gate line 200, the common electrode line 300, and the data pad line 220 may be formed of the lower chromium (Cr) layer 201 and the upper aluminum-neodynium (Al-Nd) alloy layer 202. It is formed of a double layer. In addition, a gate pad 210 is formed at one end of the gate line 200, and the data pad line 220 is inside the sealing line 101, which is a line to which an encapsulant to block the outside by injecting and sealing a liquid crystal material is applied. Beginning at and extending outwards, the two common electrode lines 300 are connected by branch lines 310.

The gate insulating film 40 is stacked on the gate line 200, the common electrode line 300, the data pad line 220, and the like, and the amorphous silicon is disposed on the gate insulating film 40 on the gate electrode that is a part of the gate line 200. The pattern 50 is formed, and the amorphous silicon patterns 610 and 620 doped on both sides of the gate line 200 are separated on the amorphous silicon pattern 50.

In addition, a data line 700 is formed in the vertical direction on the gate insulating film 40. The data line 700 includes a lower first chromium layer 701, an upper aluminum layer 702, and an upper second. It is formed of a triple layer of the chromium layer 703. In this case, the first chromium layer 701 and the aluminum layer 702 are formed in the same width, and the third chromium layer 703 is formed in a wider width so that the lower first chromium layer 701 and the aluminum layer ( 702 is completely covered. In addition, the second chromium layer 703 is connected to the source electrode 710 formed on the first doped amorphous silicon pattern 610.

A drain electrode 720 made of the same material as the source electrode 710 is formed on the second doped amorphous silicon pattern 620, and the drain electrode 720 extends to be connected to the pixel electrode 730. The pixel electrode 730 has several branch lines 740, which are alternately arranged with the common electrode branch line 310.

A passivation layer 80 is stacked on the data line 700, the pixel electrode 730, and the like, and the passivation layer 80 includes a first contact hole 810 and a data pad line 220 exposing the gate pad 210. A second contact hole 820 exposing the data pad portion of the data pad, a plurality of third contact holes 830 exposing the data line 700, and ends of the data line 700 and the data pad line 220 simultaneously. The fourth contact hole 840 is formed.

An auxiliary data line 900, an auxiliary gate pad 910, and an auxiliary data pad 920 made of indium tin oxide (ITO) are formed on the passivation layer 80. In this case, the auxiliary data line 900 is connected to the data line 700 through the third contact hole 830 and the second chrome layer 703 of the data line 700 through the fourth contact hole 840. And the chromium layer 201 of the data pad line 220, and the auxiliary gate pad 910 is connected to the chromium layer 201 of the gate pad 210 through the first contact hole 810. The auxiliary data pad 920 is connected to the chromium layer 201 of the data pad line 220 through the second contact hole 820.

In this way, the auxiliary patterns 900, 910 and 920 may be formed of corrosion resistant ITO to improve the reliability of the pads 810, 820 and the data line 700, and the auxiliary patterns 900, 910, Since the metal layer in direct contact with the 920 becomes the chromium layers 201 and 703, the contact portion may be prevented from being damaged due to the chemical reaction caused by the contact between the ITO and aluminum.

A method of manufacturing a thin film transistor substrate having such a structure will be described.

5A, 6A, and 7A are layout views of a thin film transistor substrate according to a procedure of manufacturing a thin film transistor substrate according to a first embodiment of the present invention, and FIGS. 5B, 5C, and 5D are respectively shown in FIG. Sections VB-Vb ', Vc-Vc', and Vd-Vd 'are cross-sectional views, and FIGS. 6B, 6C, and 6D are lines VIb-VIb', VIc-VIc ', and VId-VId, respectively, of FIG. 6A. 7B, 7C, and 7D are cross-sectional views taken along the lines 'b-'b', 'c-'c', and 'd-'d' of FIG. 7A, respectively.

First, as shown in FIGS. 5A to 5D, a chromium layer 201 is deposited on a transparent insulating substrate 10 such as glass to a thickness of about 500 kPa, and then the aluminum-neodynium alloy layer 202 is about 2,500 kPa. After the deposition, the two metal layers 201 and 202 are simultaneously patterned to form a gate line 200 including the gate pad 210, a common electrode line 300 and a common electrode branch line 310, and a data pad. Line 220 is formed, and a silicon nitride layer, an amorphous silicon layer, and a doped amorphous silicon layer are sequentially deposited thereon, and the doped amorphous silicon layer and the amorphous silicon layer are simultaneously patterned to form an island-shaped amorphous layer on the gate insulating film 40. A doped amorphous silicon pattern 60 that is not separated from the silicon pattern 50 is formed.

Next, as shown in FIGS. 6A to 6D, the first chromium layer 701 having a thickness of about 500 GPa and the aluminum-neodynium alloy layer 702 of about 4,000 GPa are continuously deposited and patterned on the gate insulating film 40. As a result, the data line 700 is separated from the data pad line 220.

Next, as shown in FIGS. 7A to 7D, the second chromium layer 703 is deposited and patterned to a thickness of about 500 GPa so that the second chromium layer 703 is formed of the first chromium layer 701 and the aluminum-neodynium alloy. The data line 700 is formed to completely cover the layer 702, and at the same time, the source electrode 710, the drain electrode 720, and the pixel electrode 730 are formed. Subsequently, the doped amorphous silicon pattern 60 that is not covered by the data line 700, the source electrode 710, the drain electrode 720, and the pixel electrode 740 is etched to separate the patterns 610. 620 is formed, and then, a silicon nitride (SiNx) is deposited to a thickness of about 2,000 kPa to form a protective film 80. As such, when the second chromium layer 703 completely covers the aluminum-neodynium alloy layer 702, the aluminum-neodynium alloy layer 702 may be damaged by chlorine gas during etching of the doped amorphous silicon pattern 60. There is no worry.

Subsequently, the passivation layer 80 and the gate insulating layer 40 are patterned to form contact holes 810, 820, 830, and 840, and the entire surface is etched to expose aluminum-neodynium through the contact holes 810, 820, and 840. After removing the alloy layer 202, an indium tin oxide (ITO) is deposited and patterned to form the auxiliary data line 900, the auxiliary gate pad 910, and the auxiliary data pad 920. In this case, the auxiliary data line 900 is connected to the data line 700 and the data pad line 220 through a contact hole 840 exposing the data line 700 and the data pad line 220 together.

Next, the structure of the thin film transistor substrate for a liquid crystal display according to the second embodiment of the present invention and the manufacturing method thereof will be described.

First, the structure will be described.

FIG. 8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 9, 10, and 11 are lines VII- ′, VII- ′, and XI- of FIG. 8, respectively. It is sectional drawing about XI 'line.

A gate line 20 and a common electrode line 30 formed of a double layer of a chromium layer 21 and an aluminum-neodynium alloy layer 22 are formed on the insulating substrate 1 in a horizontal direction, and a chromium layer ( A data pad line 24 composed of a double layer 21 and an aluminum-neodynium alloy layer 22 extends from the inside of the sealing line 12 to the outside. At this time, the common electrode line 30 has a common electrode 31 in the form of a branch, and the gate line 20 has a gate pad part 23 and a gate electrode.

A gate insulating film 4 is deposited on the gate line 20, the common electrode line 30, and the data pad line 24, and an amorphous silicon pattern is formed on the gate insulating film 4 on the gate electrode that is part of the gate line 20. (5) is formed, and on the amorphous silicon pattern 5, doped amorphous silicon patterns 61 and 62 are separated on both sides of the gate electrode.

A data line 7 made of chromium in the vertical direction is formed on the gate insulating film 4 to intersect with the gate line 20. At this time, the data line 7 is separated from the data pad line 24 and is connected to the data line shorting bar 74 on the same layer. In addition, a source electrode 71 formed as a branch of the data line 7 extends over the first doped amorphous silicon pattern 61, and the drain electrode 72 is placed on the second doped amorphous silicon pattern 62. ) Is formed, and the drain electrode 72 is extended to be connected to the pixel electrode 73 of the same layer. A portion of the pixel electrode 73 overlaps with the common electrode line 30 to form a storage capacitor, and has pixel electrode branches that are alternately disposed with the common electrode 31.

A protective film 8 is deposited on the data line 7 and the pixel electrode 73. The protective film 8 includes a gate pad portion, a data pad portion of the data pad line 24, and a data pad line 24. An end portion that exposes an end portion of the data line 7, an end portion of the data line 7, an end portion of the gate line 20, and a far end portion from the data line 7 of the data pad line 24, respectively. First to sixth contact holes 81, 82, 83, 84, 85, and 86 are formed.

The auxiliary data line 90, the auxiliary gate pad 91, the auxiliary data pad 92, the first and second gate line shorting bars 93 and 94, and the first to third auxiliary data line shorting are formed on the passivation layer 8. Bars 95, 96, and 97 are formed. At this time, the auxiliary data line 90 is formed to be slightly wider than the data line 7, and the data line 7 and the data pad line 24 are formed through the third and fourth contact holes 83 and 84. Is connecting. The auxiliary gate pad 91 and the auxiliary data pad 92 are connected to the gate line 20 and the data pad line 24 through the first contact hole 81 and the second contact hole 82, respectively. In addition, the first gate line shorting bar 93 and the second gate line shorting bar 94 are alternately connected to the gate line 20 through the fifth contact hole 85, and the first to third auxiliary data. The line shorting bars 95, 96, and 97 are connected to the data pad line 24 alternately through the sixth contact hole 86. The first and second gate line shorting bars 93 and 94 and the first to second auxiliary data line shorting bars 95, 96 and 97 protect the thin film transistor circuit from static electricity and inspect the operating state of the thin film transistor substrate. The liquid crystal display panel is formed outside the cutting line 11, which is a line to be cut when the liquid crystal display panel is separated by cells.

In this case, since the data pad line 24 is positioned under the gate insulating film 4, the portion exposed in the air even after the liquid crystal injection and sealing is conventionally covered can be covered with the gate insulating film 4, so that the metal wire, especially aluminum The made data line can be prevented from being corroded outside the sealing line 12 or exposed to impurities, and it is also possible to prevent the occurrence of defects due to scratches. According to the present invention, the auxiliary gate pad 91 and the auxiliary data pad 92 are exposed to the outside, but this part is protected by the ACF.

A method of manufacturing a thin film transistor substrate having such a structure will be described.

12A, 13A, and 14A are layout views of a thin film transistor substrate according to a sequence of a process of manufacturing a thin film transistor substrate according to a first embodiment of the present invention, and FIGS. 12B, 12C, and 12D are respectively shown in FIG. XIIb-XIIb 'line, XIIc-XIIc' line, and XIId-XIId 'line are sectional drawing, FIG. 13B, FIG. 13C, FIG. 13D are XIIIb-XIIIb' line, XIIIc-XIIIc 'line, XIIId-XIIId, respectively, of FIG. 14B, 14C, and 14D are cross-sectional views taken along lines XIVb-XIVb ', XIVc-XIVc', and XIVd-XIVd 'of FIG. 14A, respectively.

First, as shown in FIGS. 12A to 12D, a chromium and an aluminum-neodynium alloy are deposited on the transparent insulating substrate 1 to a thickness of 500 kPa and 2500 kPa, respectively, and simultaneously patterned to form a gate line 20 and a common electrode 31. After forming the common electrode line 30 and the data pad line 24 including the silicon nitride, amorphous silicon, doped amorphous silicon deposited to a thickness of 4500 Å, 2000 Å, 500 각각, respectively, the amorphous silicon layer and the doped amorphous silicon layer Are patterned together to form an island-shaped amorphous silicon pattern 5 and an undoped amorphous silicon pattern 6.

Next, as shown in FIGS. 13A to 13D, chromium is deposited and patterned to a thickness of about 500 GPa, and is separated from the data pad line 24 so that the data line 7 extends in the vertical direction, and the doped amorphous silicon pattern ( Doping not separated as branches of the data line shorting bar 74 and the data line 7 connecting the data lines 7 to one in order to protect the data lines 7 from static electricity which may occur when etching 6). A source electrode 71 extending up to the top of the amorphous silicon pattern 6, a drain electrode 72 and a drain electrode 72 positioned on the doped amorphous silicon pattern 6 which is not separated from the source electrode 71. ), And then, the source electrode 71 and the drain electrode 72 are formed as etch barriers to be separated from both sides of the undoped amorphous silicon pattern 6.

Subsequently, as shown in FIGS. 14A to 14B, silicon nitride is deposited and patterned to a thickness of about 2000 GPa to form first to sixth contact holes 81, 82, 83, 84, 85, and 86.

Finally, aluminum is deposited and patterned to a thickness of about 4000 Å to form the auxiliary data line 90, the auxiliary gate pad 91, the auxiliary data pad 92, the first and second gate line shorting bars 93 and 94, and First to third auxiliary data line shorting bars 95, 96, and 97 are formed.

In this case, since the data pad line is positioned under the gate insulating film, the exposed portion in the air even after the liquid crystal injection and sealing is conventionally covered with the gate insulating film, so that the data wiring made of aluminum is corroded or impurities outside the sealing line. It can prevent the exposure to, and also prevent the occurrence of defects by the scratch (scratch). In addition, the redundancy of the data line can be formed with ITO while avoiding the contact between ITO and aluminum, and the ITO can be covered with the gate pad and the data pad to ensure reliability.

Claims (23)

Insulation board, A gate line formed on the substrate, A data pad line formed separately from the gate line on the substrate; A gate insulating layer covering the gate line and the data pad line and having first and second contact holes exposing a portion of the data pad line; A data line formed on the gate insulating film, A thin film including a gate electrode connected to the gate line, a channel layer formed on the gate insulating layer on the gate electrode, a source electrode connected to the channel layer and the data line, and a drain electrode connected to the channel layer. transistor, A pixel electrode connected to the drain electrode, A passivation layer covering the data line, the pixel electrode, and the thin film transistor and having third and fourth contact holes corresponding to the first and second contact holes, respectively, and a fifth contact hole exposing the data line; An auxiliary data line formed on the passivation layer and connected to a data pad line through the second and fourth contact holes and connected to the data line through the fifth contact hole; Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The data line includes a lower chromium layer, an intermediate first metal layer, and an upper chromium layer, wherein the upper chromium layer completely covers the first metal layer and the lower chromium layer. In claim 2, The first metal layer is a thin film transistor substrate for a liquid crystal display device made of aluminum or aluminum-neodymium alloy. The method according to any one of claims 1, 2 and 3, A sixth contact hole exposing the gate pad portion of the gate line is formed in the gate insulating film, The protective layer is formed with a seventh contact hole corresponding to the sixth contact hole, An auxiliary gate pad formed on the passivation layer and covering the gate pad portion exposed through the sixth and seventh contact holes, and an auxiliary data pad covering the data pad line exposed through the first and third contact holes. Thin film transistor substrate for a liquid crystal display device further comprising. In claim 4, The gate line and the data pad line include a chromium layer and an aluminum-neodymium alloy layer stacked in succession. In claim 5, The auxiliary gate pad, the auxiliary data pad, and the auxiliary data line are made of ITO and are in contact with the chromium layer of the gate line and the chromium layer of the data pad line. The method according to any one of claims 1, 2 and 3, The data line is a thin film transistor substrate for a liquid crystal display device is formed only inside the sealing line. In claim 1, And the fifth and fourth contact holes closest to the second and fourth contact holes and the data pad line are integrally formed. In claim 1, Sixth and seventh contact holes exposing a part of the gate line and an eighth contact hole exposing a part of the data pad line are formed in the gate insulating layer, and the protective layer corresponds to the sixth through eighth contact holes, respectively. 9 th to 11 th contact holes are formed, A data line shorting bar connecting the data lines as one; An auxiliary gate pad formed on the passivation layer and connected to the gate line through the sixth and ninth contact holes; An auxiliary data pad formed on the passivation layer and connected to the data line through the first and third contact holes; First and second gate line shorting bars formed on the passivation layer and alternately connected to the gate line through the seventh and tenth contact holes; First to third auxiliary data line shorting bars formed on the passivation layer and connected to the data pad lines in alternating manner through the eighth and eleventh contact holes; Thin film transistor substrate for a liquid crystal display device further comprising. In claim 9, The auxiliary data line, the auxiliary gate pad, the auxiliary data pad, the gate line shorting bar and the auxiliary data line shorting bar are made of aluminum. In claim 10, And the data line and the data line shorting bar are made of chromium. The method according to any one of claims 9, 10 and 11, The gate line and the data pad line may include a double layer in which a chromium layer and an aluminum-neodymium alloy layer are sequentially stacked. Forming a gate line and a data pad line together on the insulating substrate; Sequentially laminating a gate insulating film, an amorphous silicon layer, and a doped amorphous silicon layer, Patterning the amorphous silicon layer and the doped amorphous silicon layer together to form a semiconductor pattern, Forming a data line, a source electrode, a drain electrode, and a pixel electrode, Laminating a protective film, Forming a contact hole in the passivation layer and the gate insulating layer to expose a portion of the data line and the data pad line; Forming an auxiliary data line connected to the data line and the data pad line through the contact hole on the passivation layer; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 13, Forming the data line, the source electrode, the drain electrode and the pixel electrode Stacking and patterning the first metal layer and the second metal layer in sequence to form a double layer of data lines; Stacking and patterning a first metal layer to form the source electrode, the drain electrode, and the pixel electrode together with an upper layer covering the double layer of the data line. The method of claim 14, The first metal layer is made of chromium, and the second metal layer is made of aluminum or an aluminum-neodynium alloy. The method according to any one of claims 13, 14 and 15, The forming of the gate line and the data pad line together is a step of depositing and patterning together a chromium layer, an aluminum, or an aluminum-neodynium alloy layer, in order to manufacture a thin film transistor substrate for a liquid crystal display device. The method of claim 16, In the forming of the contact hole, a contact hole for exposing the gate pad part of the gate line and the data pad part of the data pad line is formed together, and the auxiliary gate pad and the auxiliary data pad are further formed in the step of forming the auxiliary data line. The manufacturing method of the thin film transistor substrate for liquid crystal display devices. The method of claim 17, And etching the aluminum or aluminum-neodymium alloy layer exposed through the contact hole after the forming of the contact hole. The method of claim 18, And the auxiliary data line, the auxiliary gate pad, and the auxiliary data pad are formed of ITO. In claim 13, And forming a data line shorting bar connecting the data lines as one in the forming of the data line, the source electrode, the drain electrode, and the pixel electrode. The method of claim 20, In the forming of the contact hole, a contact hole for exposing the beginning of the gate line and a contact hole for exposing a far end from the gate line of the data pad line are formed together. In the forming of the auxiliary data line, the auxiliary gate pad, and the auxiliary data pad, a gate line shorting bar connected to the gate line is exposed through a contact hole exposing the start of the gate line, and an end portion far from the gate line of the data pad line is exposed. And forming a data line auxiliary shorting bar connected to the data pad line through a contact hole. The method of claim 21, And the gate line shorting bar is two lines of metal lines alternately connected to the gate line, and the data line auxiliary shorting bar is three lines of metal lines alternately connected to the data line three times. The method of claim 22, The data line is formed of chromium, and the auxiliary data line, the auxiliary gate pad, the auxiliary data pad, the gate line shorting bar, and the data line auxiliary shorting bar are formed of aluminum.