KR20000028695A - A large combined broadband and narrowband switch - Google Patents

Abstract

An apparatus and method for switching digital signals of different protocols in a large switching network. Protocols different from signals are wrapped in a common protocol by a set of input modules. The signal of the common protocol is then switched by a large central stage and directed to a number of output modules, where the signal is later generated with the correct protocol. The narrowband signal is converted into a wideband signal so that the central stage switches only the wideband signal. This simplifies the design of the central stage, but also enables the large scale economical central stage switch. This configuration has the advantage of being able to switch large volumes of traffic with multiple protocols with a single large switch.

Description

Large Combined Wideband and Narrowband Switch {A LARGE COMBINED BROADBAND AND NARROWBAND SWITCH}

This application is related to an application entitled “Flexible Communication Switching Network”, filed by CJ Chrin and MJ Zola at the same time as this application and assigned to the same applicant, and also to CJ Chrin and MJ Zola as of 15 May 1997. It also relates to a patent application entitled “Improved Communication Switching Unit” of Serial No. 08 / 856,842, filed by and assigned to the same applicant as the present application.

The present invention relates to digital communication switching systems, and more particularly to narrowband and wideband digital communication switching systems.

As is well known, the demand for communication services is changing rapidly. Many of these needs are for services such as video, which requires more broadband than conventional audio bands. The combination of cable television distribution systems with telephones and other on-premises equipment communication systems is making it easier and easier to use loop plants that can transmit broadband signals to individual customers. At the same time, the development of switching systems that process both broadband and narrowband signals in an efficient and integrated manner has not kept pace with this demand. Thus, one of the problems with the prior art is that there is no satisfactory large scale switching system for handling both narrowband and wideband traffic in an efficient and integrated manner.

According to the present invention, which solves this problem and has made technological advances over the prior art, a core central network receives input in a standard format from multiple access modules and switches these signals in the module. In order to efficiently handle a large amount of broadband traffic, each of these signals involves a large number of baseband channels, which are combined into a single signal. According to the preferred embodiment of the applicant, the standard signal is a signal carrying a 2.048 Mb / s payload, which is equivalent to a 32 DS0 voice channel. Each such signal is switched through a central core entity without changing the information on the payload.

According to one aspect of Applicant's invention, when a narrowband signal, i.e. a single voice channel is switched through the core, this narrowband signal only occupies a single DS0 payload and the remainder of the signal is a "fill" bit. Is occupied by This has the advantage of allowing individual voice channels to be switched through the central core from any connected module to any other connected module.

According to Applicants' preferred embodiment, modules connected to the line and trunk signals convert these signals into standard format signals. These modules include microprocessor-based switches, where the microprocessor receives input pulse code modulated signals generated by standard line and trunk interface cards, converts them into standard intermediate stage signals, and specifies the signals. Switch from standard lines and trunks to standard signals from the other end to the appropriate module at the other end. In addition, there are output interface units for interfacing between facilities such as SONET / SDH {synchronous optical network / synchronous digital hierarchy} facilities, and cores connected to core switches. Where communication is standard signals. These output interface units convert between standard signals and ATM or IP signals for transmission over the virtual channels of the SONET facility.

The standard signal of this embodiment is a VT2 signal and involves 32 64 Kbit channels and is specified in more detail through the discussion of FIGS. 17-20.

Advantageously, using the 1999 technology, a core network to support 12288 (768 × 16) VT2 signals can be accommodated on a single custom silicon chip. In-chip wiring is a big advantage over paying for many chips for these circuits because the interface circuit is unnecessary and the allowable very narrow circuit wiring can be used on the silicon chip. With complete interconnection among the modules connected to the core network, it is advantageous to allow one narrowband signal to fully occupy the VT2 signal without allowing the core network to switch anything but the VT2 signal. .

According to another aspect of the applicant's invention, a connection to a module of the prior art is possible. 5ESS manufactured by Lucent Technologies Inc. Prior art modules, such as switch communication modules, communicate via proprietary link signals that are encapsulated into VT2 signals at the input of the core network. These NCT links can carry both narrowband and wideband signals. Communication module is 5ESS Can be connected to the switch module of the switch.

According to another aspect of the applicant's invention, groups of modules are interconnected by a number of central stage modules, as in the Clos network, a well-known configuration for ensuring the absence of blocking from any input to any output.

1 is a block diagram of a microprocessor based time-slot exchange module,

2 is a block diagram of an internal microprocessor of this TSI module;

3 is a block diagram of memory and buffer placement of this TSI module;

4 is a flowchart of a program for controlling a TSI module;

5 shows a modified version of the program of FIG. 4 when multiple sub-frames encounter between each frame synchronization pulse; FIG.

6 shows a program for controlling a microprocessor operating as a time multiplexing switch;

7 shows a TSI program when groups of time slots are bundled and switched into bundles,

8 illustrates a cell header of an asynchronous transmission mode (ATM) cell,

9 is a diagram showing a basic processing operation of an ATM cell;

10 shows a programmer module showing a memory arrangement of a microprocessor operating as an ATM switch;

11 is a flowchart showing an input processing operation of a microprocessor ATM switch;

12 illustrates processing of an output queue of a microprocessor program for an ATM switch;

13 is a diagram illustrating a process of processing an ATM cell with an output link of a microprocessor ATM switch;

14 is a block diagram illustrating a configuration for extending the size of a microprocessor control switch by replicating it into a microprocessor complex;

15 shows a CLOS network of a switching microprocessor;

16 is a conceptual diagram illustrating a three-stage network used as a combined circuit and packet switch;

17 is a detailed block diagram of such a three phase network;

18 illustrates in detail the connections to the main structure of FIG. 17;

FIG. 19 illustrates a configuration for interconnecting a plurality of main steps of FIG. 17;

20 is a more detailed block diagram of the core structure of FIG.

Explanation of symbols for the main parts of the drawings

1700: central structure 1810, 1820: narrowband paddle card

1840, 1850: Broadband Paddle Card

1830 narrowband peripherals

1860 Peripheral Structure 1870 Broadband and Narrow-Band Peripherals

The techniques of FIGS. 1-14 relate to a single-stage network for implementing the TSI function, the TMS function, and also for implementing packet switching for switching ATM signals or signals of Internet Protocol (IP) within the same module. Figure 14 shows how fewer groups of modules can be in parallel to implement the functionality of a larger module. 15 shows a Clos network made by the modules described above. 16 is a conceptual diagram illustrating a three-stage network used as a combined circuit and packet switch. The subject matter of FIGS. 17-20 is the majority of the claimed subject matter of this application, using the modules described in the previous part of the application, but interconnecting these modules with a new form of central stage to create a very large switch. .

This specification describes a method and configuration for implementing multiple hardware functionality by suitable software on a reduced instruction set computer (RISC) microprocessor. These are described in the case of RISC microprocessors, but other types of microprocessor implementations (eg, Complex Instruction Set Computer (CISC)) may be applied. Multiple functions may exist simultaneously in the same microprocessor or only a single function may be provided. The type of processing each input and / or output will receive (eg time slot switch (TSI), time multiplexing switching (TMS), cross-connect (XCON)}, asynchronous mode (ATM) switching, Internet Protocol (IP) router, dynamic synchronous transfer mode (DTM), frame relay (FR) switch, etc.] may be determined and reconfigured by software control. Conversion from input to output format, for example from / to ATM format in circuit switched PCM format, may also be provided. A method of organizing a large scale configuration using multiple microprocessors for applications that are not suitable on a single microprocessor is also presented.

Another advantage is that

1. VLSI is rarely or wholly useless. Fast commercialization (removes development time)

2. Microprocessor Self-Diagnostics-(Reduces investment in chip and board test tools.)

3. Follow the technical curve directly according to Moore's Law. -(Good technological progress)

4. The core architecture is available in many applications.

5. Less development effort is possible (for all of the above reasons).

The basic technique used is:

1. The input bit stream is input to a shift register with serial input and parallel output in synchronization with the clock and read in parallel to the microprocessor data bus under the control of the microprocessor address bus.

2. This data is then stored in the on-board microprocessor cache memory, which can be expanded by level 2 caches external to or within the microprocessor chip and / or auxiliary memory external to the microprocessor, and stored by program control. It can be manipulated to provide the desired switching function.

3. More frequently used parts of stored programs are advantageously stored in cache.

4. The resulting output is read in parallel into a shift register with parallel input, serial output, and output as a serial bit stream in synchronization with the clock.

1 is a block diagram of a basic system architecture. The heart of the system is a microprocessor comprising on-board program and data caches and an external input / output consisting of a serial-parallel shift register as an input buffer and a parallel-serial shift register as an output buffer. An input / output decoder under the control of the microprocessor selects an input buffer to load data on the data bus, or selects an output buffer to read data from the data bus. Control registers can be used to receive or send control messages to / from the outside world. External memory can be used to store data structures that are too large to be cached, as well as backup and maintenance code. Microprocessor software can be used to provide the switching functions that have traditionally been provided by hardware implementations. Thus, many different functions can be provided simultaneously by a single microprocessor architecture. Different sets of functions can be provided by changing the onboard software.

1 shows an input and output data stream of a time slot exchange unit 100 in accordance with the applicant's invention. In one preferred embodiment of the applicant's invention, a 300 MHz PowePC, EC603e chip manufactured by Motorola is capable of switching 192 serial input and output streams consisting of 32 time slots each operating at a bit rate of 2.048 Mbits per second. The input includes n serial input streams, stream 0 is connected to the input buffer 101, ..., and n-1 serial input streams are connected to the input buffer 102. The first input stream is collected in the shift register of the input buffer 101 and sequentially transmitted in parallel to four buffers of 64 bits each stage. The final stage of this buffer is connected to a series of 64-bit tri-state bus drivers to drive the parallel bus 105. The n output buffers 111,... 112 are also connected to the parallel bus 105. These output buffers also contain four levels of 64-bit registers, whose inputs are connected to 64 bus receivers connected to bus 105, and the outputs are connected to shift registers to generate a serial output stream. The bus 105 is also coupled to a microprocessor 120, each of the n input buffers 101, ..., 102 in accordance with the read operation of four corresponding 64-bit data buses under the control of a program stored therein. Accepts a 256-bit burst input from Similarly, after the microprocessor reads an input under the control of its own program and control map to generate an output burst, the 256-bit burst into each of the n output buffers in accordance with the write operation of four corresponding 64-bit data buses. Export the output.

Under control of the microprocessor, an I / O decoder unit 130 is used to gate the tri-state output of the input buffer to the bus, and output the bus from n output buffers 111,..., 112. Gating to The I / O decoder receives input from the microprocessor address bus.

And memory for storing infrequently used data and program text, such as backups for data stored in microprocessor caches such as microprocessor program text and path memory, uncached TSI code, and data required for testing or diagnostics. 122 is also connected to this bus 105. Bus 105 is also coupled to a control register 124 that interfaces with call processing controllers or other communication network switches and receives and transmits control messages.

2 is a block diagram of the major parts of a microprocessor in accordance with an understanding of the invention. The microprocessor includes a program cache 201 to store a control program that controls the operation of the time slot exchange unit. The output of the program cache goes to the instruction queue 203 where a number of instructions are stored, thereby enabling fast execution of simple loop operations that are made possible using pipelined techniques. The command queue is interfaced with the command control block 205 so that appropriate commands are sent to the arithmetic logic unit (ALU) 207. The ALU executes the received instruction to control the load storage unit 213 to execute the steps required by the instruction, which then accesses the data cache 211. The ALU 207 also controls a group of internal registers 215 for control of the microprocessor or for short term storage. The bus interface 217 communicates with the bus 105 (FIG. 1), communicates with the data cache 211 inside the microprocessor, and also with the program cache 201 for software exchange or backup.

3 illustrates associated memory data stored in data cache 211 of microprocessor 120. The contents of the data cache include, in addition to other matters, data received from the input buffers 101, ..., 102 and data to be output to the output buffers 111, ..., 112. Data received from the input buffers 101,... 102 are stored in the TSI buffers 301 or 303. In Applicants' preferred embodiment, data from the various input buffers is stored sequentially in one of these buffers. The TSI buffer includes a buffer 301 to handle n x 64 kilobit connections per second, and a second buffer 303 to store another frame of this serial input data. The buffers 301 and 303 may be used interchangeably. The control map 311 controls the reading of the contents of the TSI buffer 301 or 303 to generate an output stored in the TSI output buffer 321 for transmission to one of the output buffers 111,..., 112. Used. The TSI write pointer 315 is used to track where in the TSI buffer 301 or 303 is stored one of the input buffers 101,... 102. The control pointer 313 is used to indicate the appropriate portion of the control map 313 to control the access of the TSI buffer to obtain the time slots required to fill the TSI output buffer 321. The input buffer count 331 is used to control the cycle of acquiring input from the appropriate one of the n input buffers 101,... 102 selected by the input buffer address register 332, and the output buffer count 333. ) Is used to control the output distribution collected in the TSI output buffer 321 into one of the n output buffers 111,..., 112 selected by the output buffer address register 334. Link status memory 341 is used to indicate any of the n non-serviceable input links, or any of the n output links. This state can be checked before receiving input from one of the n input buffers 101,... 102, or sending the output to one of the output buffers 111,..., 112.

The control map is changed under the control of the microprocessor program when the microprocessor receives a control message from the connection request register 351 in the control register 124 of FIG. 1, which control message is established or connected at the time slot exchange unit. Indicates a request for release. Control processing of the control map is well known in the art.

4 is a flowchart illustrating the operation of a program for implementing a time slot exchange (TSI) in accordance with the applicant's invention. This process begins with waiting for a frame synchronization pulse (block 401). When the frame synchronization pulse arrives, this signal initiates the synchronized loading of the input buffers 101,... 102 from the serial input stream and initiates a number of initialization steps. The memory write address (TSI write pointer) is initialized (operation block 402), whereby the correct positions of the TSI buffers 301 and 303 for writing information from the input buffers 101, ..., 102 are set. . The buffering offset in step 2 is toggled (block 403) to select one of the frame memories 301 or 303 of the TSI buffer to store input data in alternating frames. The microprocessor then waits for an input buffer load signal indicating that the input buffers 101, ..., 102 are full (operation block 404), after which the input buffer address is initialized (operation block 405), so that the first The input buffer 101 is indicated. In order to ensure that operation block 406 reads new data from the input buffer so as not to spoil the cached data from the previous period, operation block 405 invalidates the cache data associated with the input buffer address before initiating the read. . Thereafter, with four connected 64-bit data bus operations, the input buffer indicated by the input buffer address is read into the burst (406 operation block), and the TSI buffer 301 or 303 is Stored in the microprocessor cache memory. Test 407 determines whether all inputs of this frame have been recorded. If not, the buffer address is incremented (operation block 409) and the next buffer is read into the TSI buffer (operation block 406 already described). This loop continues until test 407 indicates that all inputs in this frame have been recorded.

At this point, the TSI read cycle begins. The output buffer address 334 is initialized (operation 421), the TSI output buffer address is initialized (operation 423), and the control map pointer 313 is initialized to point to the top portion of the control map (operation 425). block). The contents of the control map are read into the index register (427 operation block), and the index register is used to read an 8 bit time slot from the TSI buffer (429 operation block); {Frame 301 or 303 is accessed according to the two stage buffering offset set in operation block 403). The read byte is then written to the TSI output buffer on the cache with an appropriate offset determined by which of the 32 bytes is to be written {TSI output buffer 321} (operation block 431). Test 433 is used to determine if 32 bytes have been written; If not, enter operation block 427 again, the loop repeats operation blocks 427, 429, 431. After 32 bytes have been written, the result of the test 433 is positively recognized and four bound 64-bit data buses to the output buffers 111, ..., 112 indicated by the output buffer address 334. 32 bytes are written from the cache by the data cache block flush operation in which the write operation is bursted (441 operation block). Test 443 determines whether all output has been recorded. If not, the TSI output buffer read address is reinitialized (445 operation block). The output buffer address (output buffer address 334) is then incremented (operation block 447) and the write loop from operation block 427 to the output buffer is resumed. If it is determined in test 443 that all output has been written, the operation for this frame is terminated, and the processor returns to block 401 to wait for the next frame synchronization pulse.

The above flow chart provides double buffering for all time slots, whether they represent n × 64 kilobit signals per second, such as 256 kilobits of data for all time slots, or a single 64 kilobits per second voice or data time slot. . If the additional frame delay introduced by this double buffering is not desired in a single 64 Kbit / sec voice or data time slot, the flow chart can be modified to provide optional double buffering, i.e. a single voice or data time slot can be doubled. You can prevent it from being buffered. This single buffered time slot is indicated in the control map 311 to invert the effect of the double buffer offset so that this time slot is read from the other of the two TSI buffer frames 301 and 303. Thus, a single buffered time slot can be read from the frame opposite to the double buffered time slot.

Generalized TSI Flow

The flow diagram shown in FIG. 4 shows that each serial input stream consists of 32 time slots and in this implementation is written to the microprocessor cache in a single 32 byte burst as described when operation block 406 is discussed. It is assumed that it will only go once per frame. It is possible to modify Fig. 4 relatively simply, which is shown in Fig. 5 to provide a high bandwidth serial link.

(1) Another decision state 451 is required at the "yes" output of decision state 443. This determines if the entire frame of the time slot has been processed. If yes, the process returns to the waiting state of block 401. If no, return to input buffer load wait block 404 and wait for a burst of the next 32 time slots.

(2) The read control map pointer initialization step, which is operation block 425, is performed from the TSI read loop to the beginning of the TSI write cycle (after the initialization operation block 402 of the memory write address) since the entire frame has not yet been written. Transferred.

The RISC microprocessor hardware of FIG. 1, the block diagram of FIG. 2, and the programmer data model of FIG. 3 may also be used to implement a time multiplexing switch (TMS). The fundamental difference is that TSI applications need to store and maintain one or two of the time slots in memory (single or double buffered applications), whereas TMS applications switch as soon as possible after the time slot appears at the input to the TMS. Is required. This means that the serial input streams (which have been written to the TSI buffer in FIG. 3) shown at terminals 101, ..., 102 are read into the serial output streams 111, ..., 112, and they are stored in the TSI buffer. That means you no longer need to save it. Thus, subsequent write bursts to this buffer during the frame interval can overwrite previous data. This means that TMS applications require less than one byte or two frames of memory, but only 32 bytes per serial input (write / burst size), resulting in lower memory requirements than TSI applications. There is also no need for double buffering in the n × 64 kbit / s stream because the time slots are read immediately and there is no possibility of time slots being out of order.

6 is a flowchart for implementing a TMS. Similar to the TSI basic flow diagram (FIG. 4), the differences described above for TMS as well as the changes already described in the generalized TSI flow diagram. In order to assist the reader, the same operation as in FIG. 4 is given the same number. TMS requires high bandwidth functionality much greater than the 2.048 Mbit / s assumed in the basic TSI flow chart. Accordingly, the addition of the test 449 and the step of initializing the read control pointer (operation 425) to manipulate the entire frame in FIG. 6 from the TSI read cycle to the frame initialization portion near the beginning of the TMS write cycle in FIG. It is necessary to move. These two steps are the same as described in the generalized TSI flowchart.

The only two changes in the flow chart for implementing TMS functionality are:

(1) Move operation block 402 from the frame initialization portion of the TSI write to the buffer-loaded inner loop so that this data has already been output, as described in the previous section, so that it can overwrite the previous burst.

(2) Eliminate operation block 403 used to implement double buffering. The TMS flowchart of FIG. 6 implements a time multiplexing switching function.

One variation on sequentially writing the input buffers 101, ..., 102 to the cache is that instead of taking a 32 byte burst from a single input buffer, 8 bytes are written from each of the four input buffers. This has the advantage of reducing the number of bytes of buffering required by the input buffers 101, ..., 102 from 32 bytes per buffer to 8 bytes. Taking 16 bytes per two buffers can also be implemented.

7 is a flowchart illustrating operation of a system used to simultaneously switch groups of time slots. These could be used in place of digital cross-connects such as the Digital Access And Cross-Connect System (DACS), a system manufactured by Lucent Technologies.

Blocks 461, 463, 465, 467 replace the functions performed by blocks 429, 431, 433 in FIG. 6. In the implementation described in FIG. 7, only blocks 461 and 463 have been repeated eight times. Blocks 465 and 467 are shown at the end of this iteration, where the program is described in-line instead of using a loop. Operation block 461 is essentially equivalent to operation block 429 of FIG. 6, and operation block 463 is essentially equivalent to operation block 431 of FIG. 6; However, instead of including the test 433, the code was simply repeated eight times before entering the operation block 441.

The flow chart above describes an 8-bit time slot in which the amount of bytes is read and written in operation blocks 429 and 431. 16-bit and 32-bit time slots can also be readily provided by simply replacing half word or full word microprocessor instructions in the corresponding load and store instructions. To further generalize the width of time slots, the use of a load / store string command to send a series of time slots at blocks 429 and 431 allows group switching to cause adjacent time slots to be switched in groups. It can be included. Since the loop overhead from operations blocks 427 to 433 is reduced in proportion to the time slots of one byte width, the total number of bytes of information switched during the unit time is determined by the time slot width or group. Increases with increasing size. This is very efficient for switching 32 time slot PCM (E1) facilities to implement cross wiring. Some group sizes, such as in T1 facilities in a 24 byte wide group, can be switched most efficiently by padding this 24 time slot into a 32 byte group. The groups can be connected in series to form a higher bandwidth transfer rate such as DS3 at the output of the output buffer; This is particularly useful for implementing digital access cross wiring systems (DACS).

The block diagram of FIG. 1 may also be used to implement an ATM switch. 8 shows a header structure of an ATM cell. ATM cells can be switched most efficiently by padding 53 time slots into a 64 byte group. This requires some control logic in the input and output buffers. The general purpose flow control bits 5-8 in octet 1 are used for overall control to prevent the ATM system from being overloaded. The virtual path identifier is split over the first 4 bits of the first 8 bits and the last 4 bits of the second 8 bits. The virtual path identifier identifies the user. All virtual channels of the same user use the same virtual path identifier. The virtual path identifier is the main identifier used to switch ATM cells within the switch and identifies the incoming ATM cells so that they can be switched to the appropriate destination. The virtual channel identifier (the first 4 bits in 8-bit unit 2 and all 8-bit units 3, and the last 4 bits in 8-bit unit 4) is used by the user to identify a particular communication among a plurality of communication between terminal users; This particular communication is on a particular channel. The first 4 bits of 8 bit unit 4 are payload type (2 bits), 1 bit reserved for future use, and cell loss priority bits. The cell loss priority bit is used to determine if a particular cell can be removed upon overload. Finally, the header error control 8-bit unit 5 is a cyclic redundancy check (CRC) bit across the header.

9 is a functional schematic of the software control elements of an ATM switch. These consist of CRC checking, input link control, VPI / VCI processing, shaping, quality of service (QOS) processing, output link control and CRC generation. CRC check 901 operation block is executed on the header of each ATM cell as it enters the system. Input link control (903 operation blocks) brings incoming data into the memory of the microprocessor. VPI / VCI processing (905 operation block) finds a VPI / VCI data block containing an input VPI / VCI indication, an output VPI / VCI indication, and a quality of service (QOS) pointer. The test 907 is used to determine if a shape alignment test is needed. The shape alignment test is not executed for every cell, but usually every tenth cell. If the shape alignment function needs to be executed in one cell, the shape alignment function is executed (909 operation block). The shape alignment function determines whether the peak or average allowed data rate is exceeded. If so, the shape alignment function introduces a throttle into the information transfer, which performs the adjustment by putting the packets in a shape sized queue of limited size, so that if the peak rate is exceeded for too long or the average rate is exceeded As there is no more space in the queue, the input is blocked and packets are dropped.

Next, quality of service processing (operation block 911) is executed. Each output link has a number of queues for providing cells to that output link. These queues contain different priority information so that certain queues are serviced preferentially over other queues. Finally, output link control (operation block 913) sends cells from one of the QOS queues to the output link and generates a new CRC. Before inserting a cell into one of the QOS links, the output VPI / VCI is inserted into the cell header. In some implementations, the CRC function is performed in hardware to increase the switching capacity of the ATM switch.

FIG. 10 illustrates a Programmers' Data Model including a data structure and register allocation used in an implementation. The ATM cell distribution defined by the virtual path VP, and the virtual channel VC identifier are implemented by table look-up using a hashing algorithm in off-chip SRAM or level 2 cache. Queuing of cells is implemented using linked lists associated with each output port and a shared buffer area of cache memory. There is also a linked list associated with the unused memory area, which is used as a pool for adding components / areas at random. Each output link includes multiple output queues, each of which is associated with a particular quality of service (QOS). Each output link provides an identifier for the next QOS queue to be output using the priority table look-up. This allows access to the QOS queues in any desired priority order.

In this preferred embodiment everything is on the cache, but in other implementations, especially for high processing power, many of the data and some of the more specialized programs may reside in external memory.

The functions of the various blocks of FIG. 10 are as follows.

Block 1001 represents an input buffer to the switch.

The input buffer address register 1003 determines which buffer the system processes.

Cell header address register 1005 and cell header register 1007 are used to process the header of a particular cell.

Block 1009 is used to check and generate the header CRC (in some alternative configurations the CRC may be automatically checked and generated by the circuit).

Hashing function register 1011 and hashing calculation register 1013 are used to locate the VPI / VCI specified in the header of the input cell.

Block 1015 is typically occupied only 50 percent to enable efficient hashed access to the VPI / VCI table.

Some of the blocks indicated by table 1015 are block 1017, which is a VPI / VCI block for VPI / VCI (1), block 1019, which is an empty block, and block which is the block for the final VPI / VCI ( 1023).

Block 1017 includes an identifier of the input VPI / VCI, an identifier of the output VPI / VCI that the cell should be switched to, a pointer to quality of service (QOS), and a queue used to assemble the cells to be sent to the output link.

The third column of FIG. 10 uses a shared memory spectrum, with one set 1031,..., 1033 for link 1 and another set 1035,... For link n being the final link. Multiple QOS queues, including. Block 1031 includes an identifier of the link on which the cell is being queued and a pair of pointers for entries on the queue. The entries on the queue are each linked next time, using the head cell pointer to find the cell to be sent to the output link on the queue, and the tail cell pointer to find the entry on which the next cell can enter. Finally blocks 1041 and 1043 are used to select a particular cell to be sent to the output buffer in one of the QOS queues. Each output buffer has one link controller, such as link controller 1043. Link controller 1043 includes a head cell pointer to QOS queues. In a high priority QOS queue, a number of entries are made in table 1043, where there are 16 entries, which are typically more than 4 QOS queues per output buffer. The output link register is used to select which link is to be processed and the priority counter register is used to select the head cell pointer for that output buffer. When the header cell pointer of block 1043 is read, it will point to the head cell pointer of one of the QOS queues, which head cell pointer will subsequently point to the oldest cell in the queue, that is, the cell to be placed in the output buffer. Finally block 1051 shows output buffer 1 1053, ..., output buffer " n " 1055 as the 'n' output buffer. The output address register 1057 is used to select which output buffer is to be processed.

11 is a flow chart illustrating cell input and VPI / VCI flow. The cell input section illustrates writing a 32 byte burst from the input buffer selected by the input buffer address to cache memory. Header and VPI / VCI processing are shown in the rest of the figure. The CRC check can be performed in software if desired and is implemented one byte at a time using a header for indexing into a 256 byte table. If an error is detected, a routine is entered that results in correcting the error or missing the cell. After the CRC check, an empty cell code check is performed. Empty cells are ignored but the routine flows to the normal "single thread" output routine ("E" input in Figure 13). The 32-bit hashing function is then used in conjunction with VPI / VCI to generate a hashing address for indexing the SRAM or Level 2 cache and to read the 32-byte data burst for that VPI / VCI. If the address does not have the correct VPI / VCI, alternate hashing addresses are repeatedly attempted until the correct VPI / VCI is found or an exception handling routine is initiated. Hashing algorithms are well described in the literature. In the VPI / VCI table, which only occupies 50%, the average number of searches required by the implemented algorithm is 1.5, providing reasonable access time at the expense of memory consumption. If the search is successful, shaping is performed if necessary, and the "output VPI / VCI", i.e., the destination of the cell, is extracted from the table and inserted into the cell header.

12 is an output queue flow diagram. This consists of inserting the cell into the appropriate output queue based on the output link and the QOS specified in the data related to the VPI / VCI discovery described in the previous section. There are "m" QOS queues associated with each output link and each queue is defined by a linked list (see "m" QOS queues per output link table in FIG. 10). Linked lists are well known in the art. There is also a list of all unused memory regions defined by an unused region link list called " unused region queue " (ULQ). 12 details the pointer and data manipulation for implementing this linked list queue.

13 is a flow chart of writing to an output link. The priority order used for the output queue uses the static per-link link priority table (see FIG. 10) to set the order of queue reads on a per link basis. The per link priority table shown in FIG. 10 has (e.g.) 16 entries, each of which may specify any of the "m" (e.g. m = 4) queues set for the link. . If the selected queue on the link is empty, each of the other queues is examined until a queue with data is found or until all queues associated with that link are determined to be empty. If a cell is found in one of the queues, a CRC is generated and inserted into the header and the cell is sent to the output buffer. If there is no cell in the queue, a CRC is generated for the idle code and the idle code cell is sent to the output buffer. Then some pointer manipulations related to housekeeping the linked list are done. There is additional housekeeping related to priority and buffer address manipulation. In addition, some decision points regarding all link writes, shaping, and all cell reads will properly loop back to the entry points in FIG. 11 or move to the shape alignment routine.

The shape alignment (operation block 909) occurs during multiple periodic cell intervals to ensure that the peak and average bandwidth determined per VPI / VCI have not been exceeded. The cells may be missing, delayed or just passed. Shape sorting is performed on a per VPI / VCI basis using linked list auxiliary queues. Details of conformation are well known in the art. Additional information is included in the VPI / VCI table of FIG. 9. At the morphological intervals under discussion (eg peak rate every 10 cells, sustained rate every 100 cells), the following information is provided in the VPI / VCI table: Contracted Peak Cell Rate (PCR), Time stamp for PCR, contracted sustained cell rate (SCR), time stamp for SCR, and maximum size of shape alignment queue.

The individual blocks of FIGS. 11-13 are now described. 11 begins at block 1101, where the system waits for a frame synchronization pulse. When the frame synchronization pulse arrives, this signals the start of synchronized loading of the serial input stream into the input buffers 101,... 102. Operation block 1103 represents a wait for a signal indicating that an input buffer has been loaded. When the input buffer is loaded, the memory write address for unloading the buffer into the microprocessor memory is initialized. The cell is then read from the input buffer (operation block 1107) and the input buffer address is incremented (operation block 1109). At this point, the cell is loaded into the microprocessor's memory so that the microprocessor is ready to process the cell. The header of the cell is loaded into a register (1121 operation block), and a CRC check is performed (1123 operation block). CRC checks are performed only on the contents of the header. CRC checks may be performed by special circuitry or may be performed relatively quickly using a 256 byte table; Each byte corresponds to one of 256 possible CRC bytes. Next, a check is made to see if the cell is empty (test 1125). Empty cells have VPI / VCI identifiers predetermined as industry standards. Test 1127 determines if the cell is actually empty so if so, subsequent processing is aborted and the output processing routine of FIG. 13 is started. If the cell is not empty, you need to find the VPI / VCI table entry for this cell. Processing block and tests 1129, 1131, 1133, 1135, 1137, 1139, 1141, 1143, 1145 describe this processing. Find the VPI / VCI table (Table 1015) of FIG. 10 (block 1129). Thereafter, a known constant hashing function is loaded into the register of the microprocessor (1131 processing block). This register is multiplied by the contents of the register containing the VPI / VCI (1133 operation block). In one example of this embodiment, there are up to approximately 2,000 VPI / VCI entries as in block 1017 of FIG. 10. In the table, the result of multiplying 12 bits in processing block 1133 is generated, in which case the entry of the VPI / VCI table is read using the last significant 12 bits. The table is 4,096 entries long and corresponds to a 12-bit access queue. In operation block 1137 the true value of the VPI / VCI is compared with the VPI / VCI value found in the accessed VPI / VCI table (operation 1137), and a test 1139 is used to determine if the two values are equal. If it is the same, it means that an appropriate VPI / VCI table entry was found. If not, test 1141 is used to determine if the "nth attempt" has already been reached, and if so, anomalous processing routine 1143 is initiated. This routine searches the list of VPI / VCI table entries used to support when n attempts fail to locate the VPI / VCI (not shown in the secondary table). Entries in this table are created when the attempt to load into the table fails "n" times. If this is not the "n" attempt, another 12 bits of the 32-bit product generated in operation block 1133 are used (operation 1145) to access another entry in the table of VPI / VCI (operation 1135). ).

The reason for using the hashing scheme is that the total number of possible VPI / VCI combinations is over one million (the VPI indicator is 8 bits long and the VCI indicator is 12 bits long), so even though only 2,000 are used at a time, ²⁰ This is because there are (more than one million) possible VPI / VCI values.

Once the appropriate VPI / VCI table entry is found (as the output of the 1939 test), the test 1151 is used to determine if shape alignment is needed in the current case. In this embodiment, the form alignment is performed only for every "nth" cell, where the "n" value may be, for example, a value of 10. Shape alignment is used to monitor the input rate of a particular VPI to ensure that the VPI does not transmit more cells than allowed at the peak rate. Peak rate is defined as the number of cells that can be transmitted during a particular interval. If a larger number of cells are sent, a slow-down message is sent to the cell's source while the extra cells are either simply excluded or temporarily passed through. After the shape sort function is executed (operation block 1153), or if shape sorting is not required in the current cell, an output VPI / VCI identifier is loaded from the VPI / VCI table into the cell and replaces the input VPI / VCI. Thereafter, the output queue routine of FIG. 12 is started.

The system reads the QOS pointer stored in the VPI / VCI block. This pointer points to a tail cell pointer in the QOS queue to service that VPI / VCI. QOS queues (eg, block 1037 in FIG. 10) are used to queue cells for transmission to the output link. As mentioned above, a number of QOS queues are provided on a special output link, and cells are stored in different queues, depending on the quality of service provided to a particular VPI / VCI, preferably different QOS queues are provided to output the contents. Carried by a link. The contents in each QOS queue are stored in linked form, with the tail cell pointer pointing to the last entry. It is this pointer that the QOS pointer of the VPI / VCI block points to. The "m" pointer of the QOS queue is read (operation block 1203), and the "n" link from its idle queue area to the next idle queue area is temporarily stored in a register of the microprocessor (operation block 1205). The cell is then queued to the location specified by the original "n" cell pointer (operation 1207), and the address of the next free cell is processed.

To dynamically and efficiently share the available memory space, a list linked to each output queue is used. In addition, there is a "unused area" linked list, which is a global resource that contains an empty (unused) area available for storing information in the queue. When a queue needs to add information, it gets the available area from this "unused area" linked list. As a result, both the "unused region" linked list and the linked list of queues requesting an available region collide. There is a separate head cell pointer and tail cell pointer associated with all queues, including the unused location queue (ULQ).

The head cell of the ULQ is the next available area for storing the queued cells, and the tail cell of the ULQ is the last cell that has returned to the ULQ pool. The head cell of the queue is the last cell stored in the queue, and the tail cell of the queue is the next cell to be output from the queue. The head cell of the ULQ becomes the tail cell of the queue requesting the storage area, and both linked lists are modified to support this memory area movement function. Specifically, operation block 1204 expands the queue to include the cell stored at operation block 1207, and operation block 1211 updates the pointer to reflect the expansion of this linked list. Operation block 1213 changes the head cell pointer of the ULQ to reflect the removal of the available cell area.

Following the execution of the operation block 1213, the output processing of FIG. 13 is executed. Block 1043 of FIG. 10 is a series of 16 pointers to "m" QOS queues of a particular output link, where the value of "m" is typically 4, much less than 16, and differs even with 16 entries. It can be used to support more or less frequent QOS queues. Related to the output queue, priority counter 1045 is used to select the appropriate entry from the priority table. In operation block 1301, a priority counter is used to index into the priority table of the output link being serviced (different output links are serviced according to rotation order). The priority counter is then incremented and ready to service the next link (operation block 1303). The queue pointed to by the priority table is then checked to see if it is empty (operation block 1305). Test 1307 is used to determine if the queue is empty, and if empty, determines if this is the last (fourth) queue (operation 1309). If not, the queue counter is decremented by one (1311 operation block) and the corresponding queue is checked to see if it is empty (1305 operation block). From the beginning, or after the progress of the loops 1309, 1311, and 1305, if the result of the test 1307 indicates that the queue is not empty, a CRC is generated in the cell header (1313 operation block), and the cell header Is stored in the output buffer (1315 operation block). The output buffer address is incremented to prepare for subsequent processing (1317 operation block), and the queue in which the current cell is transferred to the output buffer stores the cell transferred to the buffer as a list of empty areas on the queue, and then updates and updates the head cell. To the queue.

Operation blocks 1321 and 1325 represent linked list pointer operations for reading from a queue to an output link, and are similar to the writing steps of operation blocks 1204, 1211 and 1213 described above. In this case, however, the cell position is added to the ULQ pool, and the cell position is removed from the queue that outputs the cell.

The test 1335 is used to determine if the output on all links has been sent. If not, the output link priority table is incremented (1337 operation block), causing the next link to be serviced in the next processing. Operation blocks 1339 and 1341 are used to unload the shape sort queue. If output to all links occurs (the result of the 1335 test is positive), the output link priority counter is incremented (1351), the input buffer address is initialized (1353 operation block), and the first input buffer is serviced. The output buffer address is initialized (operation block 1355) so that the initial output buffer is serviced during the next pre-loop processing, and the output link address register is initialized (operation block 1357). Test 1359 determines whether all cells have been read from the input buffer, and if not, operation block 1103 of FIG. 11 resumes. If all cells have been read, operation block 1101 of FIG. 11 is initiated.

11-13 show flow diagrams for implementing an ATM switch except for shape alignment, which occurs only during multiple cell intervals to ensure that the peak and average bandwidths per VPI / VCI have not been exceeded. The flow diagram deliberately shows how a single cell is processed from input to output at a time before the next cell is entered to represent the design logic, ie design logic. The efficiency of the processor utilization is such that by implementing "multiple thread" ATM cell processing, functions such as I / O read / write and read / write of off-chip memory and level 2 cache can be added to overlapping functions. Is possible by

This implementation of ATM switching assumes that the ATM cell entering the switch is in the format of 53 consecutive time slots, which is important for application. There is another application where an ATM cell enters a T1 / E1 fractional T1 / E1 using lower bandwidth pipes, for example 128 kbps, 384 kbps and the like. In this case, the ATM cell needs to examine and aggregate a number of frames until all 53 byte cells are available. There are several ways to implement this. One way is to consider this function as part of a peripheral and provide this functionality by providing a separate RISC microprocessor. The second method is to include an aggregation function in the ATM switching structure described above. There may be different tradeoffs for different applications, for example the size of switching operations under consideration and the amount of real time available, as well as the ratio of split ATM to complete cell ATM.

The block diagram of FIG. 1 may be used to implement an Internet Protocol (IP) switch as well as an ATM switch described in FIGS. 9-13. Unlike the case of ATM, the IP packet is variable length and contains a destination address field for which a longest prefix match is required for switching. Variable length means a more flexible buffer allocation technique, and possibly packet fragmentation and reassembly may be necessary depending on the maximum transport unit size of the different networks to which the IP switch switches. The order of the processing steps may be similar to that of ATM and consists of header checksum check, input link control, destination processing, quality of service processing, output link control, and header check-sum verification. In some implementations, header check-sum processing may be performed in hardware to improve the processing capacity of the IP switch.

After the IP header checksum verification is complete, the IP packet distribution step examines the destination address field of the IP header to perform hashing based on a look-up algorithm that can perform the longest prefix match search as well described in the literature. The search returns information about the appropriate output link. Further analysis of the packet headers yields processing information that can implement various levels of quality of service and can locate specific output queues associated with the output links and the quality of the assigned processing. If the length of the packet is larger than the maximum transmission unit size of the output link, split the packet and link it into a series of packets to the appropriate output queue. Output link processing selects the packet from the highest priority queue at that moment, and makes final adjustments to the selected IP header, such as the time to the active field or the header checksum of the modified IP header before sending the packet to the actual physical output link. Do it. The time to live field is the number of switching points that are used to drop the Internet packet if it is not carried within this time, or via the one specified in the field.

In less flexible implementations, it will often be implemented in hardware, such as a field programmable gate array (FPGA) in the workplace, based on a state machine, while IP (Internet Protocol) switching emulates its functionality in software. emulation can be performed in a general-purpose switching structure. In all implementations well formed packets are eventually given to the switching and routing software. The headers of these packets are examined to classify the processing type via hashing to determine the output queue. The classification of the processing flow may use various protocols and port data from the packet to be switched in addition to the IP destination in keying the hashing process. The hashing search finally yields output link and queue information that enables QOS (quality of service) processing. Various IP fields, such as TTL {time to live}, are updated as packets are linked to output queuing. Routing information specified in the hashed lookup table that depends on the processing flow is maintained throughout the gateway protocol processing. Output processing always determines the next optimal output queue on a per link basis to unlink packets for actual packet transmission. As mentioned above in the case of packet formation, the case of packet output may also be embodied in a number of different implementations. IP switching uses many of the mechanisms described in more detail in the ATM section. Depending on the trade-off of performance, different implementations of this concept may shift the functionality of packet formation from serial streams; Instead of a single processor, various separate and sequential cooperating processors may be used to form packets from within the TSI time slots that are marked to contain packet stream data.

Frame relay switching can also be implemented within a software based general purpose switching architecture. In the case of frame relay, HDLC-based processing can be optimally performed by the input adaptive hardware, because bit-oriented processing is often not cost effective for general-purpose switch software. Assuming well-formed frames come in with frame switching software, a hashing search across DLCI field information will yield output link and queue information. Separate operation, administration and maintenance (OA & M) software will maintain routing information specified in the frame hashing distribution table. Subsequent output processing will unlink the frames from the output queue for transmission inside the HDLC format by the output adaptation hardware.

So far this document describes a single function switching architecture implementation that can be implemented by and mounted on a conventional RISC microprocessor architecture. Such single function switching structures may be implemented simultaneously on the same microprocessor.

In its simplest form, different types of structural functions may be assigned to the shift register of FIG. 1 on an interface per serial link. This will be done under the control of software that can be downloaded if necessary. When processing the link for each link time, a program for processing the link's protocol is executed. For example, if the circuit switched time slots and ATM time slots to which the TSI function is to occupy separate serial link interfaces, the link time slots burst into the cache as described in a single functional implementation. Will be entered. The bandwidth of these serial links, for example the number of time slots, may vary depending on the application and the particular serial link. Since the TSI time slot must be maintained for one or two frame intervals (depending on whether the time slot is single buffered or double buffered), reading subsequent ATM cells that do not have this frame retention request may cause TSI data in the cache to be lost. It may result in damaging. If a cache line is locked until after data is no longer required after each input burst, this potential problem can be avoided.

It can be extended to two or more coexisting architecture types, including positional switching (eg TSI, TMS, and XCON) and packet switching (eg ATM, IP routing, and frame relay). have. In switching data transmitted over different protocols, many types of traffic can be mounted on the same serial link if a chunk of a specific bandwidth is allocated for each protocol type. Allocation can be unnecessarily limited. This can also be accomplished by downloading the appropriate data or software. This can be done using the "recently change" mechanism if the consumer chooses or changes the service type.

In the description of the TSI interface, it has been described that 24 bytes can be padded into 32 bytes of the input / output shift register. Similarly, it has been proposed that for an ATM interface, a 53 byte cell can be filled with 64 bytes of an input / output shift register. While this is reasonable when only a single function type is assigned to a shift register, it can add too much complexity when multiple function types are assigned to a particular shift register. Therefore, it is desirable that reads (burst inputs) or writes (burst outputs) to and from the link into and out of the cache remain as is, i.e., a continuous stream of time slots, and padding operations are done in software inside the microprocessor. Do.

If a linked list of data structures is used to describe sequential memory bytes from each serial interface, the bandwidth allocated to different traffic types within a given serial link can be flexibly manipulated by the subject microprocessor. For example, you can specify the type of traffic with special indicators, indicators, and length information in applications where packet data should be buffered for reassembly, or where circuit switched data belongs within the TSI. Separate input and output lists can be interpreted for each interface by the microprocessor with the descriptive code. This switch holds control data for the frame.

For example, a microprocessor may interpret from the linked data structure for a given interface to mean that the next M byte data should be treated as circuit switched data to be sent to the next M TSI consecutive positions. The next linked data structure may then include a code and a length indicating that the next N bytes contain a portion of the IP packet to be assembled, in the reassembly area indicated by the data structure. Finally, for example, the final linked data structure may indicate that the next P consecutive bytes contain an ATM cell.

This linked list of input and output descriptor data structures can flexibly describe any type of traffic type within the input and output interfaces. Descriptors may also indicate how data should be interpreted within distinct virtual branches of the same physical interface. OA & M software can be used to maintain the contents of the descriptor data structure.

In the prior art, one small T1 facility for PCM circuit-switched voice traffic, another for frame relay-based IP world-wide-web traffic, and a third T1 facility for ATM-based video conferencing for small businesses. Although we have leased separate partial T1 installations, we have the advantage that these concepts can be used within a single microprocessor general-purpose switch application. If a general-purpose switching element can be used, the lease cost of such separate installations can often substantially exceed the cost of a single installation, even if more bandwidth is possible. General-purpose switching devices also have the advantage of being able to dynamically adjust the bandwidth between different traffic types within a fixed lease T1 installation.

Having multiple concurrently running switching structures in a single microprocessor results in only a small impact on the processing capacity of the switching because of the real-time effects described above. The 300MHz EC503e PowerPC chip is said to be capable of supporting approximately 480 Mb / sec (7500 time slots) in single time-slot TSI switching and 1.5 Gbit (3 million cells per second) in ATM cell switching. Sharing features on a single microprocessor reduces the processing capacity of each application in proportion to their real-time usage. For example, a single microprocessor can simultaneously support approximately 240 Mb / sec (3750 timeslots) in TSI and 750 Mb / sec (750,000 cells per second) in ATM cell switching. The rate of a particular application depends on traffic mixing and may include proportional amounts of frame relay and IP router switching.

The foregoing paragraphs illustrate the simultaneous operation of circuit switching and packet switching structures. RISC also provides SAC (Synchronous-Asynchronous Conversion), which is a function required for switching between packet (asynchronous) worlds and circuits (synchronous) such as AAL1, AAL2, and AAL5 as well as IP layering through Frame Relay or IP through ATM ) Can be supported. Thus, there is not only connectivity within each switching domain, but also integrated interconnectivity between these switching domains.

FIG. 14 illustrates a configuration for increasing the size of the TSI of FIG. 1. FIG. 14 illustrates an implementation that may be applied regardless of the number n of input signals, regardless of the number k of microprocessor complexes, and regardless of the value of n / k that may be provided by the speed and memory capacity of these complexes. do. In the particular embodiment of Figure 14, n is 32, k is 8, n / k is 4. Each input stream terminating at buffer amplifiers 521-1, ..., 521-32 is connected to a shift register input buffer similarly to input buffer 101. Microprocessor complex 501-1 and shift registers 511-1, ..., 511-32 are connected to local bus 541-1 from which microprocessor complex 501-1 receives input. do. The same configuration is available for each of the seven other microprocessor complexes 501-2, ..., 501-8. Each microprocessor complex outputs with only four of its 32 output buffers. For example, the microprocessor complex 501 outputs only to the output buffers 531-1, ..., 531-4. The processing capacity of each microprocessor complex must be sufficient to accept input from the full range of input shift registers, but the output stream only needs to drive 1 to k. Fortunately, the input signal is loaded into the sequential positions of the TSI buffers 301 and 303 of each microprocessor, so the absorption of the input is in parallel. Thus, a very large amount of input data can be absorbed into the microprocessor cache at unit time. Only output data is required by the microprocessor for time slot or group sequential processing.

The configuration with local shift registers per microprocessor complex has the corresponding disadvantage of having to repeatedly shift shift registers for each microprocessor, but has the advantage of limiting high bandwidth connections to the local location proximate each microprocessor. . In other configurations, which may often be desirable, a single global set of shift registers in which each microprocessor is in lockstep may be used, absorbing the same input data at the same time. In this case, the complexity of high-band global access and global microprocessor synchronization will be traded for the reduction of all shift register sets except for one microprocessor.

In theory, it is possible to receive or process input data serially to generate pre-ordered output data. The configuration of Figure 14 is because each input word is received in parallel, and each microprocessor can process different numbers of bytes to generate an output stream at its output, so different microprocessors are required for different amounts of processing. It does not work satisfactorily for this kind of configuration (processing inputs in series to produce parallel outputs).

15 shows a three stage Clos network of a switching microprocessor. The nature of this type of network is that a minimum number of time slots are required to provide a non-blocking network ("intersection point" in the prior art). For “n” inputs to the input microprocessor in FIG. 14, 2n−1 outputs are required to not block. As the number of time slots increases, 2n becomes a very close approximation and only conservative matters. Let's look at Figure 15 for a large-scale TSI implementation. Input and output microprocessors have symmetrical processing capacity. The throughput of this TSI is "k" times compared to a single microprocessor. There is a control RISC microprocessor that receives control messages from an external source that defines the required end time slot connection. The control microprocessor calculates the proper path through the Clos network and sends an appropriate control message to each microprocessor requesting this information. This operation is performed only once for each call. Each input microprocessor must assemble the time-slot link and send it to the appropriate output microprocessor. The output microprocessor receives data from the central stage and makes appropriate output connections to complete the path. The "j" central stage provides a space switch path between the input and output microprocessors and switches the group of assembled time-slots to the appropriate destination. Thus, the central stage provides "group switching" as previously defined in this document, and the "group switching" microprocessor has more than five times the number of time slots switched compared to a single time slot switching. Again, this document can be known. Thus, the central stages "1" through "j" each have five times the processing power of one of the "k" I / O processors. The central stage needs to double the number of timeslots (" 2n ") compared to the I / O stage (" n ") per processor, but has five times the processing power as described above. The number of required center stages is "k" rounded up to the next integer number of input or output stages, and n / s = 1/5 is group switching of "j" stage of "k" stage TSI When j is the ratio of the processing power to, j = 2 (n / s) k. For example, when "k" = 5, j = 2 (1/5) 5 = 2. Thus, a TSI of five times the size of a single microprocessor TSI requires five inputs, five outputs, and two central stage processors using a benchmark 200 MHz PowerPC for five times the throughput, or 25,000 timeslots. In total, 12 microprocessors are required.

15 is used for packet switching, for example ATM. In the case of ATM, much of the real time is involved in VPI / VCI table look-ups and QOS queuing and priority processing. These functions can be shared between the input and output microprocessors of FIG. 15 in a functional distribution manner. Thus, roughly twice the switching throughput can be provided by simultaneously using input and output microprocessors for different functions. However, the net access bandwidth of the central stage closely matches the bandwidth needs of the I / O. Thus five input stages, five output stages and five central stages are required. However, the throughput of this network is approximately 10 times that of a single ATM microprocessor due to the distribution of functions. Thus, when using the benchmark 200 MHz PowerPC, 15 microprocessors provide 10 times the processing power of a 10Gbps ATM switch. Proportionally, higher bandwidths can be achieved with higher performance PowerPCs.

Figure 16 shows a three stage network using an ASIC or FPGA to implement a central stage as a crossbar switch (circuit switching). Although the upfront time required to obtain an ASIC or FPGA is consumed, it can be cost-effective for larger configurations.

15 and 16 illustrate a three stage network for obtaining output from input. There is a structure in which the network shown in these figures comprises a single entity of a larger interconnected structure, comprising a number of entities and connected to a global central stage in order to interconnect these entities. In this configuration, the central stage of FIG. 15 or FIG. 16 can be directly connected to the global central stage. Thus, the multiple substantiations of FIGS. 15 and 16 can be interconnected via this global central step. These central stages combine with the global central stage to form a new three stage configuration. The input and output microprocessors implement the same functionality as FIGS. 15 and 16.

As in the case of a single microprocessor, multiple or single function switching structures can be mounted and implemented simultaneously on the same microprocessor.

Although the technology so far has focused on the "switching structure", RISC microprocessors may be used to implement other functionality.

RISC microprocessors may be used to terminate the serial communication link. For example, a link such as a dedicated PCT (Peripheral Control and Timing) link may be considered. These serial optical fiber links have 1024 time slots, of which 768 are used for data transmission, the rest for control, synchronization, and other functions. Frame synchronization is established by a fixed code set in multiple adjacent time slots. As in the switching scheme, the serial bit stream is shifted to an external register and bursted into the cache as byte information. RISC examines adjacent byte sequences to see if they correspond to synchronization codes. If not, a bit shift instruction is executed and the resulting contiguous bytes are examined. As subsequent bytes come in through the I / O, the lookup process for the input bit stream to find this correct code continues until the synchronization code is found. This establishes the frame synchronization moment and synchronizes the serial link. Super-frame boundaries are set by the additional bytes in the sequence and search for them also achieves macro-frame synchronization. Still other required functions can be similarly realized by appropriate manipulation on the bit stream. Multiple links can also be supported on a single microprocessor. 5ESS Known standard DS1, DS3, DSn, as well as dedicated serial links such as Peripheral Interface Data Bus (PIDB), Network Control and Timing (NCT), PCT, etc. used by the switch Other serial communication links may also be implemented, including E1, E3 and other 32 channel based facilities, SONET, SDH.

One protocol can be used to transfer data to another. For example, the frame relay protocol or ATM protocol can be used to transfer data to the IP protocol. The switching system can then switch data with the accompanying protocol, and the accompanying protocol data can be extracted from the switched data.

Certain microprocessors can be used to terminate one type of serial link or multiple types of such serial links simultaneously. Multiple microprocessor configurations shown in FIGS. 14 and 15 may also be used.

Although the general switching architecture and universal serial link termination are described as separate objects above, they can be combined within a single microprocessor. For example, a single microprocessor may terminate any of the serial links described above and also provide ATM switching simultaneously within the same microprocessor. If necessary, a universal serial link terminator (any / all of the links described above in this document) may be combined with a general-purpose switching structure (any / all of the structures described above in this document) to operate simultaneously on the same microprocessor. Can be. The multiple microprocessors shown in FIGS. 14 and 15 also apply. Of particular importance is the extension of the post-combination link of the peripheral and switching structures on the same microprocessor to the central stage of FIG. 15 to provide a distributed structure with integrated peripherals.

This approach can be used to provide a higher level of combined switching functions. For example, 5ESS dedicated to trunk on a single microprocessor There is an implementation of the functionality of an object such as a switching module. This includes service circuits such as tone generators that are hardware-based in the microprocessor's floating-point decimal unit or the microprocessor's vector manipulation unit, the NCT interface to the TMS, the trunk terminator, and the TSI. On the same microprocessor, a switching module processor (SMP) may be implemented simultaneously (in native or emulation mode) for call processing and maintenance software on a software basis. In the case of the SM (Switching Module), it also includes a subscriber line so that all of the above can be used to support the subscriber line implemented in the usual way as well as the built-in trunk circuit.

Microprocessors can also be used to implement cost-effectively if generalized logic functions, especially sequential logic constructs, dominate. Therefore, this approach can be useful to provide the features implemented in today's FPGAs, which can be more cost-effective and faster in development. This approach can also be used to replace application specific integrated circuits (ASICs) using single or multiple microprocessors, depending on the application.

Although the preferred embodiment stores the input time slots sequentially and reads the data based on the contents of the control memory, it is also possible to use a method of storing the input time slots based on the contents of the control memory in combination with the sequential reading. Will be operated less efficiently. The configuration of FIG. 14 results in a satisfactory result for broadcasting due to this undesirable configuration (storage and sequential read based on control memory) because different microprocessors are required to perform different amounts of processing for each input word received. Can't give

The approach discussed here has the inherent flexibility of stored program control. It may therefore be used to implement new and different protocols, such as the dynamic synchronous transfer mode (DTM) recently proposed by the European standards body.

RISC microprocessor technology is advancing at a very rapid pace. Thus, microprocessors operating at higher frequencies beyond current limits will be able to achieve higher throughput on a single chip. Moore's Law will push this capacity further in the future.

17-20 illustrate a large scale switch in which the core configuration is switch 1700 for switching any input VT2 signal to any output VT2 signal. This switch provides a line card for asymmetric digital subscriber lines (ADSL) lines, a line card for handling plain old telephone service (POTS) lines, and input digital or analog trunks. It is input by a number of access interface units (AIUs) containing trunk cards for processing. The output of these cards is assembled into an input stream, which in turn is input into a microprocessor based communication switching network architecture configuration 100 as shown in FIG. Modules 1711 and 1725 carry and receive narrowband DS0 signals to narrowband modules; Modules 1710 and 1720 are wideband modules that carry and receive wideband (VT2) signals. Module 1711 connects only to POTS lines and / or ISDN lines, all of which communicate at or below the DS0 rate. Module 1710 can also be connected to an ADSL line.

Each VT2 signal contains a payload of 256 bits and is generated at a repetition rate of 8KHz per second. In addition to the 256 payload bits, there are two signal bits, and one bit to distinguish the narrowband signal (with an 8bit payload) from the wideband signal (payload of a product of up to 32 8bit bytes). have. The ISDN signal is transmitted in three narrowband signals because two B-channel signals may go to different destinations and the D-channel is connected to a packet switching unit. In this preferred embodiment, all narrowband signals are transmitted in the form described above; There is no case where the narrowband signal is bundled with the VT2 signal. This is because the interface ports of the core structure 1700 can only process information for a single logical communication for the physical VT2 channel.

The core structure is also connected to a wideband output interface unit (OIU) 1730, narrowband OIU 1725, which interfaces with a broadband transmission facility such as SONET / SDH. On the other hand, a SONET / SDH facility may involve virtual trunks with circuit switched signals, such as PCM signals, or packet switched signals, such as ATM signals or IP signals. When one communication leaves this switch, a connection is established between VT2 connected to one AIU and VT2 connected to an OIU, or between VT2s connected to OIUs, such as 1710 and 1711.

5ESS manufactured by Lucent Technologies Inc. In order to be compatible with existing plants such as switches, the core structure is also 5ESS. 5ESS connected to the communication module 1730 of the switch It can also communicate with links such as network control and timing (NCT) links. When narrowband NCT 1730 terminates on a core structure, the signal is converted to a VT2 signal. Wideband NCT 1732 already carries a VT2 signal. The core structure is controlled by the switching module processor controller 1790, which communicates with the control circuits in the structure or the control circuits of the AIU and OIU through the channels of the structure.

For ease of understanding, FIG. 17 is depicted as track modules 1710 and 1711 are input modules and trunk modules 1720 and 1725 are output modules. In practice, the central cell structure 1700 can switch signals from any port to any other port; Therefore, it supports line-to- trunk traffic as well as line-to-line traffic or trunk-to- trunk traffic. In addition, any line or trunk signal is a two-way signal. Thus, modules 1710, 1711, 1720, and 1725 are all “input” modules to cell structure 1700, where the cell structure returns between signals from any connected port to any other connected port ( hairpin) You are connecting. This structure is a three step structure; First a module for carrying signals to the cell structure; Second, cell structure 1700, third, a module that carries signals from the cell structure.

18 illustrates a connection between AIU units 1710 and 1711 and OIU units 1720 and 1725 and core structure 1700. Each connection to the central architecture terminates at one port, such as narrowband port 1809 or wideband port 1839. For narrowband ports, the port must recover the clock from the input signal, buffer the input, generate flow bits for the unoccupied 248 bits of the payload, perform framing, It receives the information to control the control register of the port. For broadband port 1839, it is necessary to buffer the input, recover the clock, perform framing, and receive input information for the control register. Narrowband peripherals, that is, peripherals that generate narrowband signals, such as peripherals 1830 including peripherals 1711 and 1725, are connected to the central structure 1700 via a pair of paddlecards. Connected. The basic function of the paddle card is to go through an optical fiber or wiring link that requires interface circuitry to restore synchronization and framing, allowing transmission in either the optical or electrical domain (possibly between them). The paddle card also provides a 1: N split of the VT2 stream so that N sets of peripheral structures can be connected to one broadband port. This is indicated by reference numeral 1855 in FIG. 18.

1830 includes hard-coded PCM circuit stream processing equipment and cannot do any kind of work such as protocol processing or switching. This is in contrast to 1860, where each type of stream may be its own protocol, packet- or circuit-switched per stream, and actually interpret the bit stream.

For example, in an acceptable broadband and narrowband peripheral such as an AIU or OIU, the peripheral device 1870 is sent to the broadband paddle card 1850 for transmission to the broadband paddle card 1840 interfaced with the central structure 1700. It is input in a structure included in an AIU such as 1710 or an OIU such as 1720. The broadband paddle card supplies an input to port 1839.

768 VT2s are divided into six streams of 128 VT2s each. The main reason for this is because 128 VT2 represents 250+ Mb / s reads and writes from the stream and 250+ Mb / s reads and writes to peripherals, representing a total of 1 Gbps reads and writes and protocol processing. to be. This is the multi-protocol of 1999 and large-scale treatment with heterogeneous treatment. In practical terms, this is large enough to handle all different protocols with a single processor complex. This is also because it is the most cost-effective unit in terms of scalability. Thus the "N" port of the central structure actually drives the "6 * N" peripheral structure.

Central structure

Central structure 1700 switches the elements of the VT2 size. VT2 (virtual tributary) is a SONET / SDH standard signal and contains 32 time slots per 8KHz frame, 256 bits per frame and 2,048,000 bits per second. Each VT2 is bidirectional with 2.048 Mb / s in each direction.

The central structure does not know what type of service or bit stream is in the VT2 cell. The interpretation on the bit stream is not performed. From each port of each VT2 timeslot the contents of the VT2 cell are duplicated to the appropriate outbound port and the correct timeslot (TSI function).

The central structure includes ports of the form

N_in = narrowband input port

N_out = narrowband output port

B_in = broadband input port

B_out = broadband output port

And the accompanying data path,

N_in_N_out = narrowband to narrowband path

N_in_B_out = narrowband to wideband path

B_in_N_out = broadband to narrowband path

B_in_B_out = broadband to broadband path

Under the above definition, the central structure performs simple cloning according to the following rules.

No matter how the port is defined in the control RAM, or which of the above paths is defined, the amount of data of 32 bytes (256 bits) + signal bits from the input port are duplicated to the output port. There is no concept of port type in the TSI itself.

The key to supporting both port types is the interface to the data RAM protocol. The N_in port will always duplicate signal bits and data to the signal bit storage, the first 8 bits of 256-bit data RAM. The remaining 248 bits are loaded in "fill" pattern from internal resources. The B_in port will duplicate the signal bits and data into the signal bit storage, i.e. all 256 bits of data. The N_out port will always read only the signal bits, ie only the first 8 bits of RAM in the time slot.

The B_out port is special. Here, a special 259th bit (extra signal bits) is written based on the control RAM storage contents. This bit indicates whether a particular timeslot is narrowband or broadband. In any case, all signals and 256 bits are read into the link. Paddle cards that connect outgoing data to peripherals can use the 259th bit. If it is a broadband peripheral, this bit is ignored and all bits are written on the optical link, and the issue of narrowband or broadband services is deferred to the peripheral structure. If it is a wideband network interface, it actually contains both wideband and narrowband inter-SM connections on the same paddle card. Each logical port includes one narrowband time slot and one wideband time slot. The narrowband time slot is recorded when the 259th bit indicates that this is a narrowband service.

As shown in Figure 19, the narrowband service is Lucent Technologies Inc. 5ESS manufactured by It is distributed to communication modules such as the switch's CM3, which today is usually the case for all narrowband switches. The broadband time slots into the switch central stage broadband structure are recorded as "fill" information. If the 259th bit indicates that this time is a broadband service, the broadband time slot is recorded as a broadband service. This link is connected in a switch central stage broadband architecture. Narrowband time slots to CM3 are recorded with appropriate "fill" codes. The 259th bit is written as a "broadband service code" by a broadband structure access command. If the register is not written at the time of the connect command, the hardware defaults to loading the "narrowband service code" on the 259th bit.

The wideband output of the central structure 1700 for traffic between the central structures is connected to the parallel VT2-TSI interconnect structure 1910 via paddle cards 1930 and 1940. Parallel VT2-TSI 1910 takes advantage of the multiplicity of ports present in central stage 1700. "N" ports are available for the central stage 1700, with a balanced central stage typically having K = N / 2 ports attached to the peripheral device and K ports attached to the second stage central structure 1910. It is. Parallel TSI The basic process of configuring the second stage is to assign each of the second stage "S" TSIs to some of the K ports. The multiple first level stages interconnect several ports by assigning them to each first level stage of each second level stage. The largest and most economical output possible is to interconnect 2 * K = N first level steps. In this structure, each first level step is connected to all K network ports into K second level structures, one port per second level structure. Since the number of ports is actually N per central stage, N different first level stages can be interconnected. Peripheral devices that can be interconnected by multiplicity of N ports first level stages, connected in K second level stages, and where the first and second level stages use the same parts (this is an economical part) The total amount of ports (also K = N / 2) is K * N = N * N / 2. In practical applications, at the 1999 technical level, this enables total terabits of interconnection throughput per second.

Peripheral structure

The peripheral structure is to support broadband services but also supports narrowband services. This unit (especially supporting ADSL) will support both narrowband and broadband services simultaneously.

The peripheral structure may handle any service for the VT2 cell payload. Narrowband services will be treated as if only the first byte of the VT2's 32 byte data is needed. Broadband services will use 2 to 32 bytes of VT2. This is defined on a per-service basis.

The peripheral architecture supports the following major types of broadband bandwidth classes:

VT2 only

N × VT2 only

VT2 share (packet pipe)

N × VT2 share (larger packet pipe)

Peripheral structures are created by memory and processors containing actual software that determines how the structure is translated and how the payloads within the structure are interpreted. This structure is "universal" because any software program can execute any protocol on a per-stream basis. This heterogeneous processing power is supported for a variety of circuit qualities with the greatest effort and zero jitter.

The peripheral structure is connected at one side to a central VT2 TSI structure 1700 and at the other side to both narrowband and broadband peripherals. Peripheral architecture implements the appropriate bidirectional protocol on a per-stream basis to ensure that each consumer signal flow remains in the correct format and proceeds to the right location.

20 is an extension of the VT2 cell structure 1700. The overall structure consists of "P" ports. Each P port can be set to narrowband or wideband. Each port can support input and output flows (bidirectional). All payloads can be distributed from any input port "A" to any output port "B". This includes the special case of loop-around where A and B are the same.

Input port A 2001 includes an input port signal and timing recovery unit 2003. This is programmed from the information in the control state store 2000 depending on whether the port is performing a narrowband operation or a wideband program.

If the port is performing narrowband operation, the input port signal and timing recovery unit extracts the narrowband payload from the incoming signal. For each narrowband payload, proceed as follows: The payload is replicated to the TSI input storage area 2013. In particular, two bits of the signal payload will be copied to the signal bit storage 2010 through the path 2005 and 8 bits of the narrowband payload will be copied to the storage 2011 through the path 2006. In addition, the information going to the selector 2004 via path 2007 is absent because it is narrowband. Instead, the selector 2004 receives the "fill" bit from the input fill bit unit 2002 via the path 2008 and puts it on the path 2009 for transport to the storage location 2012. (2010, 2011, 2012) all constitute (2013).

If the port is performing broadband operation, the input port signal and timing recovery unit extracts the broadband payload from the incoming signal. For each broadband payload proceed as follows: The payload is replicated to the appropriate TSI input storage area 2013. In particular, two bits of the signal payload are stored in the signal bit storage 2010 through the path 2005 and the first 8 bits of the broadband payload are replicated to the storage 2011 through the path 2006. The remaining 248 bits of the broadband payload travel to selector 2040 via path 2007 and to storage 2012 through path 2009. The input "259th bit" is absorbed by the input port signal and timing recovery unit 2003.

Data and signal bits are transferred from input storage 2013 to output storage 2019 via internal buses 2014. The TSI output storage location 2019 consists of bit 259 (2015), signal bit storage location 2016, and data storage locations 2017 and 2018. Information at (2010) is sent to path (2016) via route 2020. Information in (2011) is sent to route (2017) via route 2021. The information at (2012) is sent to (2018) via the route 2022. In addition, bit 259 2015 is loaded from control step store information 2000. Bit 259 contains a "broadband or narrowband service indicator."

The final step for generating the output port signal is to apply certain information from the appropriate TSI output repository 2019 to output port B 2023, in particular output port generator 2024.

When output port B 2023 is programmed to a narrowband port, output port generator 2024 uses information from signal store 2015 and data store 2017 via paths 2026 and 2027, respectively. do. This signal is then sent to path 2029.

When output port B 2023 is programmed to a wideband port, output port generator 2024 outputs all information received from bit 259, 2015, signal storage 2016, and data storage 2017 and 2018, respectively. Export to route 2029 via route 2025, 2026, 2027, 2028.

20 shows only a single input time-slot and a single output time-slot of signal memory per port. The remaining time slots are not shown. In one preferred embodiment, memory for multiple time-slots is contained within a single integrated circuit chip. The output of the selected time slot of the memory is distributed via the bus system 2014 to the time slot of the memory of the selected output port. Sequential timeslots of memory are loaded sequentially, selectively sent to the selected time slot of the selected output port, or selectively loaded, and sequentially sent to the selected time slot memory of the selected output port. Each port selection process is independent of the other port selection process and is controlled by a separate memory at the control stage storage location.

If only a single input time-slot and output time-slot is used for each port, block 1700 becomes a time multiplexed switch.

Time Multiplexing Switch (TMS) Core Structure:

In a variation of the structure of FIG. 17, a time-slot switched structure (TSI) cell structure 1700 is replaced with an n × 64 Kbps time multiplexed switch (TMS). The TMS may assign groups of 64 Kbps time-slots (eg 128 Kbps, 384 Kbps, 1.5 Mbps, 2.0 Mbps, etc.) to any particular link. This implementation provides more granularity compared to the VT2 TSI 1700, ie less bandwidth is used for connections lower than 2.0 Mbps. Since TMS is a spatial switch, TSI functionality must be provided somewhere. The B-AIU 1710 and BB-OIU 1720 add peripheral device architecture 100 software to the microprocessor to provide TSI functionality. The peripheral architecture has real-time throughput equivalent to 6000 time slot TSIs for a 300 MHz PowerPC. Peripheral Structure 100 The TSI voice call request is 128 voice calls (up to 128) of one thousand time-slot processing capacity of the peripheral structure 100, as shown in FIG. Thus, 97% of the peripheral structure real-time is still available for ATM, IP and other switching methods and real-time operation.

However, since AIU 1711 and OIU 1725 do not include a peripheral structure, the TSI function must be somewhere else. Microprocessor-based TSI for narrowband AIU and OIU can be placed with TMS and can switch 128 × DSOs from multiple AIU and OIUs. Multiple TSIs can be used up to the throughput of TMS. This architecture allows for lower bandwidth position switches to be used in the peripheral structure 100, for example, in an early market where the proportion of customers using or requiring a full 2 Mbps is low or not very high. It will be cost effective or appropriate for entry. The same board can be used with only software changes to the TSI used for the peripheral structure 100 and the narrowband TSI.

Network connection:

The following half call scenario illustrates the connection of a network.

Half-call scenario 1: narrowband services on narrowband ports

This is the simplest case. It is the basis for current legacy narrowband interconnection between narrowband peripherals and narrowband structures. Remember that the broadband architecture does not know that the service is narrowband and will automatically duplicate 32 bytes per frame. As noted above, N_in and N_out ports 1809 provide special processing capability to add or subtract " fill " bits. The end result is that narrowband to narrowband connections are possible.

There are two streams of narrowband service.

The first flow is in the direction of the peripherals to the central structure. The second flow is in the direction of the central structure to the peripheral device. The first flow goes from the peripheral device 1830 to the narrowband paddle card 1820 for transmission to the central structure 1700. The reader will notice that prior to paddle card transmission, it is normal to provide one or more stages of concentration to reduce the number of narrowband ports needed. The narrowband link transmits multiple DS0 time-slots, each of which is also appended with internal specific signal bits for reliability and other purposes. The narrowband link terminates on another narrowband paddle card 1810 of the central structure. The next step is to send the bit stream to any N_in central structure port 1809. At this point, the "half call" can be switched in the central structure as described above.

The second flow is in the direction from the central structure to the narrowband peripherals. The bit stream is replicated to the N_out port 1809 buffer in the central structure as already described in the central structure stage. From there, the bit stream is sent to the narrowband paddle card and sent to the peripheral area. The stream is terminated by another narrowband paddle card 1820. Set up one or more fanout (opposite) stages to distribute a densely occupied time slot stream into a number of sparsely occupied streams, each of which flows to a specific number of peripherals on a particular sub-unit Note that letting is common. The flow then continues to the actual peripheral 1830 itself.

Half-call scenario 2: narrowband services on broadband ports

There are two flows.

The first flow is from narrowband peripheral 1870 to broadband port B_in. Narrowband streams flow into the peripheral structure, which can now perform traditional convergence functions without hardware steps. Peripheral structure 1860 places narrowband flows in their respective VT2. In this case, only one of the 32 data bytes contains the actual information, and the remaining 31 bytes contain the "fill" bit in each stream. The peripheral structure releases the flow to the broadband paddle card 1850, where it transfers to the central rescue location and ends at another broadband paddle card 1840. This paddle card then sends the flow to the broadband input port (B_in) 1839. As described in the central architecture stage, the entire VT2 (one real, 31 filled bytes) will be switched by the VT2 TSI. However, it does not matter whether other peripherals are wideband or narrowband. In any case, the correct byte will eventually reach the correct position in VT2, taking up the entire DS0.

The second flow is from the wideband port (B_out) 1839 to the narrowband peripheral device. This is a more interesting direction. Remember that the B_out port has a special property that the paddle card may or may not pay attention to the 259th bit of each VT2 frame. In this case, the 259th bit will be set to narrowband if this time is an inter-USM (ie SM) port. In this case, traffic will be distributed to narrowband CM3. However, in this case, this bit is ignored because the decision of how to handle each timeslot is postponed to the peripheral structure 1860. Thus, the flow continues to the broadband paddle card 1840, goes through the optical link to the location of the peripheral device, and ends at the paddle card 1840 of the peripheral structure. This paddle card sends the flow to peripheral structure 1860, which forwards the first byte of VT2 and the appropriate signal bits to narrowband peripheral 1870. Note that the peripheral structure can also perform a fan-out function.

Half-call scenario 3: broadband service on broadband port

There are two flows.

One is from the broadband peripheral 1870 to the central structure broadband port (B_in) 1839. Each wideband stream is sent to the peripheral structure 1860. The peripheral structure understands what type of protocol is in the stream, either by provisioning, or by dynamic connection order. The peripheral device structure performs the appropriate segmentation function, which loads the wideband stream to the VT2 cell and transmits it through the structure. Flow continues through paddle cards 1850 and 1840 and continues to B_in port 1839. As mentioned above, the broadband flow is switched in the central structure.

The second flow is from the central structure broadband port (B_out) 1839 to the broadband peripheral 1870. The B_out stream is more interesting. The 259th bit in this stream will be set here as "wideband". Because this is a peripheral paddle card, the 259th bit is ignored, but as discussed above, if this was a network port it would be appropriately distributed. Flow continues to peripheral structure 1860 via paddle cards 1840 and 1850 and is processed by the peripheral structure upon arrival. The peripheral structure executes the appropriate reassembly function in the output stream protocol format from the VT2 cell. The stream is then sent to the correct broadband peripheral 1870.

Half-call scenario 4: narrowband service on the broadband port (network-side)

This calling scenario involves an internal (network) connection. These connections exist to enable interconnection of multiple central structures. Thus this represents an "internal half-call" that is invisible to the customer but actually exists to perform the interconnection between the two customers if one customer exists in one central structure and the other customer is in a different central structure. In this case, the second level of the central structure interconnects the first level of the central structure.

There are two flows.

The first flow is from narrowband interconnect (second level) structure 1730 to input port B_in of first level central structure 1731. The first flow enters paddle card 1930 at port N2_in, which is a narrowband port. The paddle card has two choices per time slot. You can choose to use the information in N2_in or B2_in. In this case we will use N2_in to duplicate the signal + 8 data bit information into the stream destined for B_in. Paddle card 1930 must also add the remaining 31 bytes of “fill” bits to the timeslot and insert the 259th bit representing the narrowband service (third signal bit). Once this is done, the stream continues to the B_in port and can then be replicated to any other port as described above.

One question remains from the description above. How do you know that a paddle card needs to use N2_in timeslots rather than B2_in timeslots? The answer is that the stream going to N2_out contains timeslot signal bits (259th) set to "narrowband". This bit updates the storage register of the paddle card ASIC used by the "input" stream state machine as a decision function. The information of the outgoing stream therefore also includes the information of the corresponding input stream. This allows the TSI to operate the paddle card on a per time slot basis. Again as an updater, this allows us to interact with the legacy aspect of the system. Narrowband traffic is unaware of the existence of broadband services. This is a great advantage because no rework is required for existing applications, and applications can interact with the general-purpose structure SM in advance by directly processing data with each other through a second-level structure without knowing what happens to the general-purpose structure SM. Becomes

The second flow is from the output port of the first level central structure 1702 to the narrowband interconnect (second level) structure 1730. This flow leaves port B_out with the 259th bit set to narrowband. Upon arrival to paddle card 1930, this bit causes the ASIC to distribute it to the N2_out port. The first byte of data and the signal bits are placed in the N2_out stream. The remaining 31 bytes are ignored from the field of view of N2_out. At the same time, the B2_out port is loaded with 32 bytes of fill data because no valid information exists.

Half Call Scenario 5: Broadband Services on the Broadband Port (Network-Side)

This calling scenario involves an internal (network) connection. These connections exist to enable interconnection of multiple central structures. Thus it appears to be an "internal half call" that is not seen by the customer, but in fact exists, performing the interconnection of two customers if one customer exists in one central structure and the other customer exists in another central structure. In these cases, the second level of the central structure interconnects with the first level of the central structure.

There are two flows.

The first flow 1732 is from the broadband interconnect (second level) structure 1910 to the input port B_in of the first level central structure 1702. The first flow enters the paddle card 1930 at port B2_in, which is a broadband port. The paddle card has two choices per time slot. You can choose to use the information in N2_in or B2_in. In this case we will use B2_in to duplicate the signal + 256 data bits into the stream destined for B_in. The paddle card must also insert the 259th bit representing the broadband service (third signal bit). Once this is done, the stream continues to the B_in port and can be replicated there to any other port as described above.

One question remains from the description above. How can the paddle card 1930 need to use the timeslot of B2_in, not the timeslot of N2_in? The answer is that the stream going to B2_out contains timeslot signal bits (259th) set to "wideband". This bit updates the storage register of the paddle card ASIC used by the "input" stream state machine as a decision function. The information of the outgoing stream therefore also includes the information of the corresponding input stream. This allows the TSI to operate the paddle card on a per time slot basis. Again as an updater, this allows us to interact with the legacy aspect of the system. Narrowband traffic is unaware of the existence of broadband services. This is a great advantage because no rework is required for existing applications, and applications can interact with the general-purpose structure SM in advance by directly processing data with each other through a second-level structure without the application knowing what happens. Becomes

The second flow is from the output port B_out of the first level central structure 1702 to the broadband interconnect (second level) structure 1910. This flow leaves port B_out with the 259th bit set to broadband. On arrival to the paddle card, this bit causes the ASIC to distribute it to the B2_out port. All 32 bytes and signal bits of data are placed in the B2_out stream. At the same time, the N2_out port is loaded with one byte of fill data because no valid information exists.

Half-call scenario 6: narrowband services on narrowband ports (network-side)

This calling scenario involves an internal (network) connection. These connections exist to enable interconnection of multiple central structures. Thus this represents an "internal half-call" that is invisible to the customer but actually exists to perform the interconnection between the two customers if one customer exists in one central structure and the other customer is in a different central structure. In this case, the second level of the central structure interconnects the first level of the central structure.

There are two flows.

The first flow is from narrowband interconnect (second level) structure CM3 1730 to input port N_in of first level central structure 1701. The first flow arrives at the first level structure via a path through the narrowband paddle card (NCT2 / 3 termination). The N_in port performs a "fill" bit operation and the like as described above, so that the narrowband payload and signals are mapped to the VT2 and the signal storage. Once this is done, this stream can be replicated to any other port as described above.

The second flow 1731 is the narrowband signaling of the second level structure from the output port N_out of the first level central structure 1701. The N_out port properly extracts the DS0 payload and signal bits from the TSI's internal VT2 + signal format. The flow then leaves the N_out port of the structure and proceeds through the narrowband paddle card NCT2 / 3 to the second level central structure.

The paddle card also provides a 1: N split of the VT2 stream so that the N sets of peripheral structures can be connected to one broadband port. This is given by reference numeral 1855 in FIG. 18.

1830 includes hard-coded PCM circuit stream processing equipment and is incapable of any kind of protocol processing or switching. This is in direct contrast to 1860, which actually interprets the bit stream and each stream's type may be its own protocol or may be packet or circuit switched per stream.

768 VT2s are divided into six streams of 128 VT2s each. The main reason for this is that 128 VT2 is 250+ Mb / s reads and writes from the stream and 250+ Mb / s reads and writes to the peripherals, representing a total of 1 Gbps reads and writes and protocol processing. Because. This is the multi-protocol of 1999 and large-scale treatment with heterogeneous treatment. In practical terms, this is large enough to handle all different protocols with a single processor complex. This is also because it is the most cost-effective unit in terms of scalability. Thus the "N" port of the central structure actually drives the "6 * N" peripheral structure.

conclusion :

The foregoing is one of the preferred embodiments of the applicant's invention. Many other embodiments are apparent to those of ordinary skill in the art without departing from the scope of the present invention. It is intended that the scope of the invention only be limited by the appended claims.

The present invention provides the effect of switching a large amount of traffic with multiple protocols with a single large switch.

Claims (18)

In a communication switching network, A plurality of modules for receiving input signals with different protocols and generating an output signal encapsulated with a standard protocol, A central stage switch to switch signals of the standard protocol from an input port of the central stage to an output port of the central stage, And the plurality of modules convert signals of the output port of the standard protocol into any of the plurality of protocols of the input signal. The method of claim 1, Said central stage switching only a wideband signal, wherein the narrowband signal transmitted to said central stage is converted into a wideband signal. The method of claim 2, And an extra bit is added to all signals to the central stage to distinguish between wideband and narrowband signals. The method of claim 2, Wherein said central step adds a "fill" bit to the received narrowband signal. The method of claim 1, Said central stage being a time slot exchange switch. The method of claim 1, Wherein said central step is a time multiplexing switch (TMS). The method of claim 1, Further includes at least one additional said communication switching network, A central stage switch of each said communications switching network is connected to at least one separate communications module for interconnection with other central stage switches. The method of claim 7, wherein One of said separate communication modules is a time multiplexed switch. The method of claim 7, wherein One of said separate communication modules is a time-slot switched switch. The method of claim 7, wherein Wherein said input signal comprises narrowband and wideband signals, wherein one of said separate communication modules is for switching a wideband signal. The method of claim 1, And the input signal comprises a narrowband signal and a wideband signal. The method of claim 1, And the input signal comprises a multiplexed signal from an analog Plain Old Telephone Service (POTS) line. The method of claim 1, And the input signal comprises an Asynchronous Transfer Mode (ATM) signal. The method of claim 1, And the input signal comprises an Internet Protocol (IP) signal. The method of claim 1, And the input signal comprises a frame relay signal. The method of claim 1, And the input signal comprises a pulse code modulation (PCM) signal. The method of claim 1, Wherein one of the input modules receives inputs from analog narrowband telephone lines and asynchronous digital subscriber lines (ADSL). The method of claim 1, Further comprising an additional plurality of central stage switches, wherein each central stage switch is connected to each of the plurality of modules, and the central stage switch and the plurality of modules are interconnected in a Clos network structure. Switching network.