KR19990006953A - Liquid crystal display device having matrix type electrode structure - Google Patents

Abstract

The present invention provides a liquid crystal display device having a matrix type electrode structure in which flicker of an image displayed on the panel (10) is not seen. The scan electrodes Y1 to Yn of the matrix are driven by an AC voltage including a voltage for holding an image displayed on the panel. The refresh pulse voltage is applied to the scan electrodes every time the polarity of the sustain voltage is inverted, so that the brightness of the image does not change before and after the polarity inversion of the sustain voltage. Interlaced scanning is employed to further reduce the flicker by making the screen frame frequency higher. In addition, the same polarity of the selected voltage is maintained for a predetermined time period to reduce the flicker due to the asymmetric characteristics of the liquid crystal 10c.

Description

Liquid crystal display device having matrix type electrode structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a liquid crystal display device, and more particularly to a liquid crystal display device having a matrix electrode structure for driving n x m pixels.

Japanese Patent Application JP-A-7-43676 discloses a liquid crystal display device having a simple matrix type electrode structure capable of displaying an image with intermediate brightness as well as a contrast image. As the liquid crystal for display, an anti-ferroelectric material is used. This kind of semi-ferroelectric liquid crystal has at least one anti-ferroelectric state (first stable state) and two ferroelectric states (second and third stable states), and each of these states can be stably obtained .

According to the description of the above publication, the voltage applied to the liquid crystal panel is periodically inverted, and therefore the DC component is not applied to the panel. The transparent state of the panel is realized alternately by using two ferroelectric states, and the non-transparent state is realized by using the anti-ferroelectric state of the anti-ferroelectric liquid crystal. In order to display an image of intermediate luminance, an eliminating period is provided in which the pixel becomes temporarily dark before each selecting period.

The semi-ferroelectric liquid crystal panel exhibits different refractive anisotropies (n) between the two ferroelectric states when viewed in an oblique direction. Therefore, a flicker occurs in the display when the switching frequency between two ferroelectric states becomes, for example, 30 Hz or less. This kind of flicker is referred to as an oblique direction flicker. Also, since the dark state appears temporarily in the erase period even when the bright state continues before and after the erase period, this dark state also causes flicker. In order to remove the flicker, it is conceivable to select a switching frequency of 30 Hz or more.

However, considering the response speed of the semi-ferroelectric liquid crystal particularly when a large number of scan electrodes are required to achieve high definition of the display, there is a limit to increase the switching frequency.

For example, Japanese Patent Application JP-A-4-311920 discloses a proposal for preventing flickering. This aims at switching the polarity of the applied voltage at a frequency that does not indicate flicker during the holding period. However, since the holding voltage is switched or inverted at the same value, the luminance of the panel after switching does not maintain the luminance before switching. This is because the anti-ferroelectric liquid crystal does not respond as fast as the polarity change. Therefore, the brightness of the panel changes every time the polarity is switched, and the flicker on the panel caused by the frequency rewriting pictures on the panel can not be avoided. This problem becomes more significant when an image of intermediate luminance is displayed.

Japanese Patent Application JP-A-7-20441 also aims at reducing flicker by reducing the luminance change from a bright state to a dark state by partially rewriting a pixel without providing an erase period. However, since the erase period is not provided, the intermediate luminance can not be obtained. In this publication, it is also proposed to use interlaced scanning (scanning electrodes are not sequentially scanned but scanned in such a manner that one or more neighboring scanning electrodes are skipped). However, if interlacing is used with an erase period to obtain intermediate brightness, a change in luminance due to the erase period causes problems such as scrolling stripe or line flicker. The scrolling stripe is a phenomenon in which the luminance change moving in the scanning direction looks like a stripe, and the line flicker is a phenomenon in which the change in luminance appears parallel to the scanning electrode. These phenomena appear to be substantially the same phenomenon.

The present invention has been made in view of the above-mentioned problems. An object of the present invention is to provide a liquid crystal display device which does not exhibit a flicker when driven by an AC voltage. It is another object of the present invention to provide a liquid crystal display device in which a scrolling stripe and / or a line flicker are not actually displayed.

The liquid crystal display device substantially comprises a display panel including liquid crystal such as a matrix electrode structure and an anti-ferroelectric liquid crystal, a scan electrode drive circuit, and a signal electrode drive circuit. One scan field is composed of a selection period in which an image is written to a pixel, a sustain period in which the image is held, and an erase period in which an image recorded in the pixel is erased. A signal for transferring an image is applied to the signal electrode in synchronization with the scan voltage. In the sustain period, the polarity of the sustain voltage is inverted.

According to the present invention, a refresh pulse voltage is applied whenever the sustain voltage polarity is inverted to maintain the brightness of the image constant before and after the inversion of the sustain voltage polarity. The level and duration of the refresh pulse voltage are selected such that the positive and negative ferroelectric states are switched to each other so that the anti-ferroelectric state of the liquid crystal is not switched to the ferroelectric state. Further, in order to further reduce the flicker, interlaced scanning which skips one or more scanning electrodes is used. The appropriate number of jumps in the interlaced scanning is chosen such that the flicker is virtually absent, including line flicker and scrolling flicker.

The polarity of the voltage applied in the selection period can be inverted every selection period. However, it is desirable to maintain the same polarity for a predetermined time period, for example, 3 hours, in order to avoid a luminance change that may occur due to the asymmetric characteristic of the anti-ferroelectric liquid crystal. The polarity switching of the selection voltage may be performed by a timer installed in the control circuit, or whenever power supply to the display device is newly started, or whenever a screen saver is operating.

Various tests have been performed as to how the semi-ferroelectric liquid crystal responds to the voltage applied thereto. Generally, there are three types of response of an anti-ferroelectric liquid crystal. When there is a change from a half-ferroelectric state to a ferroelectric state, when the state changes from one ferroelectric state to another ferroelectric state, and from a ferroelectric state to an anti- There is a form of response when it comes. In order to achieve the object of the present invention, it is necessary that the brightness of the display panel does not change when the polarity of the applied voltage is reversed during the sustain period. In other words, it is required to maintain the brightness level of the panel after the polarity of the applied voltage is inverted during the sustain period to be equal to the level before the voltage is inverted. If this is realized, the polarity of the applied voltage can be reversed during the sustain period without causing flicker.

The graph of Fig. 38 shows the response time characteristic with respect to the applied voltage of the semi-ferroelectric liquid crystal. In this graph, the curve L1 represents the response time (tau r) when the ferroelectric material is changed from the anti-ferroelectric state to the ferroelectric state at a temperature of 40 DEG C, and the curve L2 is changed from the positive ferroelectric state to the negative ferroelectric state at 40 DEG C And the response time (τ) when it is changed in the opposite direction. According to this graph, when 20 V is applied, the response time tau r is 250 mu sec and the response time tau is 33.5 mu sec. It is clear that there is a significant difference between these response times tau r and tau.

Such a difference can be used to change the state of the liquid crystal in which one of the regions is in a ferroelectric state to another ferroelectric state while keeping the region in the anti-ferroelectric state in the same state. This means that it is possible to switch the polarity of the applied voltage during the sustain period without causing visibility flicker on the display. In other words, if a refresh voltage (recovery voltage) of 20V having a duration of 33.5 mu sec is applied during the polarity change during the sustain period, the change from the anti-ferroelectric state to the ferroelectric state is not caused, Only the change between the ferroelectric states occurs. Thus, visibility flicker is suppressed.

As shown in FIG. 39, by applying such a refresh voltage, the region in the anti-ferroelectric state is not changed, and the region of the pixel in one of the ferroelectric states can be changed to another ferroelectric state. Therefore, the brightness of the display can be maintained at the same level before and after the change of the polarity of the voltage applied during the sustain period. This can be done regardless of the luminance level, i.e., the bright level, the dark level and the intermediate level.

According to the graph of Fig. 38, when a refresh pulse of 20V to be applied during the sustain period, having a pulse width or duration in the range between curves L1 and L2 is selected, the brightness of the panel is maintained at the same level Or the brightness change can be minimized. By using the above-described phenomenon, the present invention can provide a liquid crystal display device having a matrix-like electrode structure in which the display flicker is not substantially exhibited.

In addition, the level of the signal voltage applied to the signal electrode group during the period when the refresh voltage is applied to the scan electrode is selected as the base level of the signal voltage change. For this reason, the signal voltage indicating the bright display or the dark display is not affected by adding the reference level of the signal voltage. Thus, the brightness of the pixel to be refreshed is not affected by the signal voltage, which indicates the brightness of another pixel on the same scan electrode as the pixel to be refreshed.

Further, the polarity of the sustain voltage of the scan electrode is opposite to the polarity of the scan electrode adjacent to the sustain electrode during at least half of the repetition cycle of the selection period. This causes the switching frequency of the sustain voltage polarity to appear faster than the frequency of the field inversion method, thus preventing flicker of the display due to polarity switching.

According to the present invention, a refresh voltage is added to the sustain voltage every time the sustain voltage polarity is inverted, so that the sustain voltage polarity at each of the scan electrodes is alternately inverted to prevent image sticking on the display without causing flicker .

Other objects and features of the present invention will become apparent from the understanding of the preferred embodiments described with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an overall structural view of a first embodiment of a liquid crystal display device having a matrix electrode structure according to the present invention; Fig.

2 is a sectional view of a liquid crystal display panel;

3 is a scanning electrode driving circuit diagram;

4 is a detailed view of a decoder circuit;

6 is a timing chart for explaining the operation of the scan electrode driving circuit;

7 is a circuit diagram of a signal electrode driving circuit.

8 is a detailed circuit diagram of a decoder.

9 is a timing chart for explaining the operation of the signal electrode driving circuit.

10 is a timing chart for explaining the operation of the liquid crystal display device;

11 is a timing chart showing the waveform of the voltage applied to the pixel G (i, 1) in the bright state.

Fig. 12 is a timing chart showing the waveform of the voltage applied to the pixel G (i, 2) in the dark state.

13 is a timing chart showing a waveform of a voltage applied to the pixel G (i, 3) in the bright state.

Fig. 14 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) in the bright state and the transmitted light intensity of the anti-ferroelectric liquid crystal in the first field.

15 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) in the dark state and the transmitted light intensity of the anti-ferroelectric liquid crystal in the first field.

16 is a timing chart showing a scan voltage supplied from the scan electrode driving circuit when a selection voltage of the same polarity is applied to the scan electrodes with respect to one or more fields and the sustain voltage polarity is switched once per field.

Fig. 17 is a timing chart continued from Fig. 16; Fig.

18 is a timing chart showing the scan voltage, the signal voltage, and the luminance of the display when the sustain voltage polarity is switched once per field;

19 is a timing chart showing the waveform of the voltage applied to the pixel G (i, 1) in the bright state.

Fig. 20 is a timing chart showing the waveform of the voltage applied to the pixel G (i, 2) in the dark state.

Fig. 21 is a timing chart showing the waveform of the voltage applied to the pixel G (i, 3) in the bright state.

22 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) in the bright state and the transmitted light intensity of the anti-ferroelectric liquid crystal.

23 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) in the dark state and the transmitted light intensity of the anti-ferroelectric liquid crystal.

FIG. 24 is a timing chart showing a scan voltage supplied from the scan electrode driving circuit when a select voltage of the same polarity is applied to the scan electrodes for one or more fields and the sustain voltage polarity is switched three times in one field; FIG.

25 is a timing chart showing the scan voltage, the signal voltage, and the luminance of the display when the sustain voltage polarity is switched three times in one field;

Fig. 26 is an overall configuration diagram showing a third embodiment of a liquid crystal display device having a matrix electrode structure according to the present invention; Fig.

27 is a scanning electrode driving circuit diagram;

28 shows a 2-bit register shown in Fig. 27; Fig.

29 is a timing chart for explaining the operation of the scan electrode driving circuit;

30 is a timing chart showing a scan voltage and a scan pattern;

31 is a timing chart showing a scan voltage and a signal voltage;

32 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) in the bright state and the transmittance of the anti-ferroelectric liquid crystal.

33 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) and the transmittance of the semi-ferroelectric liquid crystal when the state changes from the bright state to the intermediate state.

Fig. 34 is a timing chart showing the waveform of the voltage applied to the pixel G (i, j) and the transmittance of the anti-ferroelectric liquid crystal when the state changes from the bright state to the dark state.

35A is a diagram showing luminance and average luminance of each row under progressive scanning;

35B is a diagram showing luminance and average luminance of each row under interlaced scanning;

36 is a diagram showing flicker and scrolling stripes observed under progressive scanning and interlaced scanning (the number of skip scanning electrodes: 1,2,3, and 4);

37A, 37B and 37C are diagrams for explaining a scrolling stripe.

Fig. 38 is a graph showing the response time to the holding voltage of the anti-ferroelectric liquid crystal. Fig.

39 is a model diagram showing a state change in a semi-ferroelectric liquid crystal when a refresh voltage is applied;

DESCRIPTION OF THE REFERENCE NUMERALS

10: liquid crystal panel 20: control circuit

30, 40: power supply circuit 50: scan electrode driving circuit

60: Signal electrode driving circuit

DX1 to DXm, DY1 to DYn: decoder circuit

RX1 to RXm: 3-bit register

RY1 to RYn: 2-bit register

SY1 to SYn: Level shifter

WX1 to WXm, WY1 to WYn: Analog switch circuit

A first embodiment according to the present invention will be described with reference to Figs.

Fig. 1 shows an overall configuration of a liquid crystal display device having a matrix electrode structure. This apparatus includes a liquid crystal display panel 10 as shown in Figs. The display panel includes electrode substrates 10a and 10b, an anti-ferroelectric liquid crystal 10c filling a space between the two substrates, and two polarizing layers 10b and 10c attached to the surfaces of the electrode substrates 10a and 10b, respectively. and polarizer layers 10d and 10e.

2, the electrode substrate 10a includes a glass substrate 11, m red (R), green (G), and blue (B) electrodes arranged on the lower surface of the glass substrate 11, ) Stripe, a transparent electrode layer 13 having m stripes disposed under the color filter layer 12, and an orientation film disposed under the transparent electrode layer 13, (14).

The electrode substrate 10b includes a glass substrate 15, a transparent electrode layer 16 having n stripe disposed on the glass substrate 15 and an alignment film 17 disposed on the transparent electrode layer 16 .

M stripes of the transparent electrode layer 13 and n stripes of the transparent electrode layer 16 form an (m x n) matrix of pixels together with the semi-ferroelectric liquid crystal 10c as shown in Fig. Pixels, G (1,1), G (1,2), ..., G (m, n) are arranged as shown in FIG. The m stripe of the transparent electrode 13 corresponds to the signal electrode X1, X2 ... Xm of Fig. 1 and the n stripe of the transparent electrode 16 corresponds to the scan electrode of Fig. 1, Y1, Y2 ... Yn .

The polarizing substrates 10d and 10e are arranged in a cross nicol relationship. Due to this configuration, the semi-ferroelectric liquid crystal becomes non-transparent in its anti-ferroelectric state. The two electrode substrates 10a and 10b are maintained at a uniform interval of, for example, 2 mu m by a plurality of spacers not shown in the figure.

As the semi-ferroelectric liquid crystal material 10c, for example, the same materials described in JP-A-5-119746 can be used. Other materials such as a mixture of several kinds of semi-ferroelectric liquid crystals or a mixture of liquid crystal materials comprising one kind of semi-ferroelectric liquid crystal may also be used.

1, the display device includes a control circuit 20, a power supply circuit 30, another power supply circuit 40, a scan electrode drive circuit 50, and a signal electrode drive circuit 60. The control circuit 20 outputs an output signal, DP, DR, SI01, SI02, SCC, LCK, STD and SIC, and receives the vertical synchronization signal VSYC and the horizontal synchronization signal HSYC from the external circuit. One of the DP signals (the first DP), the DR signal, the SI01 signal, the SI02 signal, and the SCC signal are supplied to the scan electrode driving circuit 50. The other DP (second DP), LCK, STD, and SIC signals are supplied to the signal electrode driving circuit 60.

The signals SI01 and SI02 are signals for defining the states of the scan electrodes Y1, Y2 ... Yn. In this embodiment, the state in which the SI01 signal is L (low) and the SI02 signal is also L corresponds to the erase period of the scan electrode. Similarly, when the SI01 signal is H (high) and the SI02 signal is L, the scan electrodes are in the selection period, and when the SI01 signal is H and the SI02 signal is also H, the scan electrodes are in the sustain period, When the signal is L and the SI02 signal is H, the scan electrodes are in the refresh period.

The power supply circuit 30 outputs seven output signals VWP, VRP, VHP, VE, VHN, VRN and VWN (FIGS. 1 and 6), and the other power supply circuit 40 outputs eight levels of luminance V1, V2, V3, V4, V5, V6, V7, V8, and VG (FIGS.

The scan electrode driving circuit 50 generates eight voltage values corresponding to the erase period, the selection period, the sustain period, and the refresh period, based on the signals from the control circuit 20, the first DP, DR, SI01, SI02, Level are sequentially supplied to the scan electrodes Y1 to Yn. The driving circuit 50 also changes the polarity of the applied voltage for each selection period in order to drive the scanning electrodes by the alternating voltage (see FIG. 10).

Now, referring to Fig. 10, the operation of the scan electrode driving circuit 50, for example, the scan electrode Y1 will be described. During the erase period (E in FIG. 10), by applying the voltage VE to the scan electrode Y1, the display of all the pixels located on the scan electrode Y1 is erased. The selection period (S in Fig. 10) is divided into three periods. As shown in FIG. 10, during the positive selection period, the voltage VE equal to the voltage applied during the erase period is applied in the first period, the negative selection voltage VWN is applied in the second period, The polarity selection voltage VWP is applied. The image data coming from the signal electrode is applied to the pixel on the scanning electrode Y1 during the selection period. In the positive polarity sustain period (H + in Fig. 10), the positive sustain voltage VHP is applied to the scan electrode Y1, and the image data is held.

The negative refresh period (R in Fig. 10) is divided into two periods, i.e., a first period and a second period. In the first period, the negative refresh voltage VRN is applied to the scan electrodes. This first period corresponds to a period during which the voltage VG is transferred from the signal electrode driving circuit 60, and in this period, the polarity of the sustaining voltage is reversed while maintaining the image data as before. In the second period of the negative polarity refresh period, the negative sustain voltage VHN is applied. Next, a negative sustain period (H- in Fig. 10) follows. During this negative sustain period, the negative sustain voltage VHN is applied, and the image data is maintained as before. Next, the positive refresh period (R in Fig. 10) and the next positive polarity sustain period follow. After the positive sustain period, the erase period comes again.

Next, the next selection period is followed. This selection period is a negative polarity period as opposed to the preceding positive polarity selection period. In the first period of the negative selection period, the voltage VE is applied, and in the second period, the positive selection voltage VWP is applied. Next, in the third period, the negative selection voltage VWN is applied to the scan electrodes. The image data coming from the signal electrode is applied to the pixel on the scanning electrode Y1 during this selection period. Next, in the negative polarity sustain period, the negative polarity sustain voltage VHN is applied, and the image data is held. Next, a positive refresh period, a positive polarity sustain period, a negative polarity refresh period, and a negative polarity sustain period follow. Thereafter, they are repeated in this order.

The operation described for the scan electrode Y1 is applied in the same way to the other scan electrodes Y2 .... Yn. As shown in Fig. 10, the scanning from the electrode Y1 to the electrode Yn with the phase difference of the sustain period of the selection period is sequentially performed. In order to prevent flickering on the display, for example, the polarities of the neighboring scan electrodes are alternately selected in such a manner that Y1 is a positive polarity, Y2 is a negative polarity, and Y3 is a positive polarity.

Now, the operation of the scan electrode driving circuit 50 will be described with reference to Fig.

The scan electrode driving circuit 50 includes n 2-bit registers RY1, RY2 ... RYn, n decoder circuits DY1, DY2 ... DYn, n level shifters SY1, SY2 ... SYn And n analog switch circuits WY1, WY2 ... WYn. Each analog switch circuit includes seven analog switches. The scan electrode driving circuit 50 performs the above-described functions based on the five types of signals received from the control circuit 20. [

The two-bit registers RY1, RY2 ... RYn sequentially receive the SI01 and SI02 signals from the control circuit 20 in synchronization with the rising of the SCC signal and the decoder circuits DY1, DY2 ... DYn Bit data (bit-1, bit-2). The decoder circuits DY1, DY2 ... DYn are controlled based on the 2-bit data from the 2-bit registers RY1, RY2 ... RYn and the first DP signal and the DR signal from the control circuit 20, And generates seven kinds of signals for performing the switching operation of the analog switch circuits WY1, WY2 ... WYn.

Each of the decoder circuits DY1, DY2, ..., DYn is configured as shown in Fig. 5 and includes six logic circuits 51-56. The operation of the decoder circuit will be described by taking DY1 as an example.

5, the logic circuit 51 composed of four inverters and four AND gates decodes the 2-bit data (bit-1, bit-2) received from the 2-bit register RY1, DDE, DDW, DDR, and DDH, which perform the switching operation. During the erase period (SI01 and SI02 are both L), only the DDE signal becomes H and the other signal becomes L. During the selection period (SI01 is H and SI02 is L), only the DDW signal becomes H and the other signals become L. During the refresh period (SI01 is L and SI02 is H), only the DDR signal becomes H and the other signal becomes L. During the sustain period (SI01 is H and SI02 is H), only the DDH signal becomes H and the other signal becomes L.

5, the logic circuit 52 composed of four AND gates, one inverter, and two OR gates controls the switching signal from the logic circuit 51 based on the DR signal, and outputs the signals DEE, DWW, DRR, and DHH. When the DDE signal is high, only the DEE signal is high. When the DDW signal is H, only the DEE signal becomes H during the time when the DR signal becomes H, and only DWW signal becomes H during the time when the DR signal becomes L. When the DDR signal is H, only the DRR signal becomes H during the time when the DR signal becomes H, and only the DHH signal becomes H during the time when the DR signal becomes L. When the DDH signal is H, only the DHH signal becomes H.

The logic circuit 53 is composed of elements shown in Fig. In this logic circuit 53, the clocked inverters 53c and 53f are operated by the inverted output from the inverter 53a and the clocked inverters 53d and 53e are operated by the inverters 53a and 53b, Lt; RTI ID = 0.0 > cascade < / RTI > Depending on the operation of the clocked inverter and other logic gates, the logic circuit 53 is reset when the DDW signal is H, and inverts the output of the OR gate 53g in synchronization with the rise of the DDR signal.

The logic circuit 54 is constituted by elements shown in Fig. 5, and performs a function of latching data. In this logic circuit 54 the clocked inverter 54c is operated by the inverted output from the inverter 54a which inverts the DDW signal and the clocked inverter 54d is operated by the cascade from the inverters 54a and 54b It operates by output. Depending on the operation of the clocked inverter and other logic gates, the logic circuit 54 outputs the first DP signal intact when the DDW signal is H, and latches the first DP signal when the DDW signal is L.

The logic circuit 55 is constituted by an exclusive OR gate and outputs an exclusive OR of the outputs from the logic circuits 53 and 54 to the logic circuit 56 as a DPP signal. During the time when the DDW signal is at H, the DPP signal corresponds to the first DP signal and its voltage polarity is controlled by this first DP signal because the logic circuit 53 is reset, L, and the logic circuit 54 provides the same output as the output of the logic circuit 53. When the DDW signal is L, the DPP signal is independent of the first DP signal because the logic circuit 54 performs the latch function. Since the logic output from the logic circuit 53 is inverted in synchronization with the rise of the DDR signal, the DPP signal is inverted every time the DDR signal rises, and the voltage polarity is inverted every refresh period.

As shown in Fig. 5, the logic circuit 56 composed of six AND gates switches the voltage polarity in accordance with the signal from the logic circuit 52 and the DPP signal from the logic circuit 55. Fig. When the DWW and DPP signals are H, the DWP signal becomes H. When the DWW signal is H and the DPP signal is L, the DWN signal becomes H. When the DRR and DPP signals are H, the DRP signal becomes H. When the DRR signal is H and the DPP signal is L, the DRN signal becomes H. When the DHH and DPP signals are H, the DHP signal is H. When the DHH signal is H and the DPP signal is L, the DHN signal becomes H. Thus, these seven control signals, DEE, DWP, DWN, DRP, DRN, DHP and DHN are synthesized.

The DEE signal controls the analog switch (see Fig. 4) connected to the VE terminal of the power supply circuit 30 through the level shifter. The DWP signal controls the analog switch connected to the VWP terminal of the power supply circuit 30 through the level shifter. The DWN signal controls the analog switch connected to the VWN terminal of the power supply circuit 30 through the level shifter. The DRP signal controls the analog switch connected to the VRP terminal of the power supply circuit 30 through the level shifter. The DRN signal controls the analog switch connected to the VRN terminal of the power supply circuit 30 through the level shifter. The DHP signal controls the analog switch connected to the VHP terminal of the power supply circuit 30 through the level shifter. The DHN signal controls the analog switch connected to the VHN terminal of the power supply circuit 30 through the level shifter. When one control signal is H, the corresponding analog switch is closed (ON), and a corresponding voltage is supplied from the power supply circuit 30 to the scan electrodes. This applies to the respective control signals DEE, DWP, DWN, DRN, DHP and DHN.

Therefore, a voltage having a predetermined waveform as shown in Fig. 6 is supplied to each of the scan electrodes Y1, Y2, ..., Yn according to the signals SCC, SI01, SI02 and the first DP.

As shown in Figs. 1 and 7, the signal electrode driving circuit 60 includes m 3-bit registers RX1, RX2, ... RXm, m decoder circuits DX1, DX2 ... DXm, m Two level shifters SX1, SX2 ... SXm, and m analog switches WX1, WX2 ... WXm. This signal electrode driving circuit 60 outputs a signal voltage of nine levels from the power supply circuit 40 in accordance with the image signal DAP from the outside and the second DP, LCK, STD and SIC signals from the control circuit 20 To the signal electrodes X1, X2, ..., Xm. Since the liquid crystal panel displays an image with eight levels of brightness, the DAP signal is a three-bit signal.

The operation of the signal electrode driving circuit 60 will be described with reference to the timing chart shown in Fig. The image signal DAP having 3-bit data is transmitted from the outside to the signal electrode driving circuit 60 as serial data for all the signal electrodes X1, X2, ..., Xm. Image data is sequentially transmitted from the outside to the signal electrode driving circuit 60, that is, data for pixels on the scanning electrode Y1 comes first, then data for pixels on the scanning electrode Y2 comes, and in this way, The data up to the electrode Yn is continuously supplied. D (1, i) represents a series of image data for pixels on the scanning electrode Y1, and D (1,1) and D (1,2) X2, ..., Xm of the signal electrodes X1, X2, ..., Xm. When the STD signal is H, the image signal corresponding to the signal electrode X1 is supplied to the 3-bit register in synchronization with the rise of the SIC signal. Similarly, the image signals corresponding to the signal electrodes X2, X3 ... Xm are sequentially supplied to the 3-bit registers in synchronization with the rise of the SIC signal. Thus, the image data for the pixels on the scan electrodes are stored in the 3-bit registers RX1, RX2 ... RXm. The data stored in the 3-bit register is supplied to the decoder circuit.

As shown in Fig. 8, each of the decoders DX1, DX2 ... DXm includes five logic circuits 61, 62, 63, 64 and 65. The operation of these decoders is described with reference to Fig. 8, taking DX1 as an example.

The logic circuit 61 composed of three D-type flip-flops latches the 3-bit image data in synchronization with the rise of the LCK signal from the control circuit 20. [ The logic circuit 62 composed of three exclusive OR gates inverts the image signal latched by the logic circuit 61 when the second DP signal from the control circuit 20 is H. The logic circuit 63 is composed of three pairs of inverters and eight AND gates and forms a decoder. The logic circuit 63 decodes the 3-bit image data signal from the logic circuit 62 and converts it into 8 line outputs. A single inverter configured logic circuit 64 inverts the LCK signal from the control circuit 20. The logic circuit 65 including eight AND gates receives the signal from the logic circuit 63 and generates a control signal for switching the eight analog switches of the analog switch circuit WX1 in accordance with the output from the logic circuit 64 D1, D2 ... D8. Further, the decoder circuit DX1 outputs the LCK signal as the control signal DG.

The decoder circuit DX1 configured as described above is configured so that the 3-bit data latched by the logic circuit 61 is (L, L, L), (L (H, H, H), (H, H, L) and (H, H, H). (L, L, L), and (L, L, H), the 3-bit data latched by the logic circuit 61 is supplied to the decoder circuit DX1 under the condition that the second DP signal is H and the LCK signal is L, (H, H, L) and (H, H, H), the respective outputs D8 to D1 are brought into a high (H) state in that order. Under the condition that the LCK signal is H, the outputs D1 to D8 become L regardless of the 3-bit data, and only the output DG becomes H.

The outputs D1 to D8 and the output DG from the decoder control the analog switches respectively connected to the voltages V1 to V8 and VG of the power supply circuit 40 through level shifters (see Fig. 7). When the outputs D1 to D8 and the output DG are at H, the corresponding analog switch is turned on, and the output voltage from the power supply circuit 40 is supplied to the signal electrode.

After the image data for a pixel on one scan electrode is latched by the logic circuit 61 in synchronism with the rise of the LCK signal, the 3-bit registers RX1 to RX2 next receive the image data for the pixel on the next scan electrode Start typing. Therefore, as can be seen from the timing chart shown in Fig. 9, in response to the signals SIC, STD, LCK and the second DP and the image data DAP, the signal electrodes X1 to Xm are supplied with a voltage output having a prescribed waveform.

The output voltage VE from the power supply circuit 30 and the output voltage VG from the power supply circuit 40 are set to a common level. The signal SCC, the first DP and the LCK are synchronized with the signal DP, and all these signals are supplied from the control circuit 20. The image data for the pixel on the scan electrode in the selection period is input in advance by one selection period. Thus, the waveform shown in Fig. 10 is realized.

Now, the 1-frame display frequency is 5 Hz (the display period of one frame is 200 ms), the number of row electrodes is 220, the number of column electrodes is 960, the duty ratio is 1 / N (N = 1000), and the erase period is E (E = 100), will be described.

The driving voltage having the waveforms shown in Figs. 11, 12 and 13 is applied to the pixels G (i, 1), G (i, 2) and G . As shown in these figures, the driving voltage applied to the pixel is composed of the selection period voltage, the sustain period voltage, and the erase period voltage. The driving voltage applied during the sustain period consists of the refresh pulse voltage and the sustain voltage, and the polarity thereof is inverted to a frequency of 30 Hz or more. Each time the polarity is inverted, a refresh pulse is applied. One display frame consists of a first field and a second field. Now, the operation of the first frame will be described with reference to Figs. 11, 12 and 13. Fig.

First, the order of driving voltages applied to the pixels is described. During the selection period, a voltage VE having a pulse width t1 (t1 = 33.3 mu s), a voltage VWN having a pulse width t2 (t2 = 33.3 mu s), and a voltage VWP having a pulse width t2 are sequentially applied. During the sustain period following the selection period, the sustain voltage VHP is applied. The refresh voltage VRN having the pulse width t1 is applied after 10 ms calculated from the beginning of the selection period, and then the sustain voltage VHN is applied until the elapse of 10 ms from the start of the refresh voltage. Next, the refresh voltage VRP having the pulse width t1 is applied. Thereafter, the holding voltage VHP is applied until 10 ms has elapsed from the start of the refresh voltage VRP.

Thereafter, the cycle of the refresh pulse voltage and the sustain voltage is repeated every 10 ms while changing the polarity thereof. This continues to the end point of the Pth hold voltage (P = 9 in this example). The total time from the start of the selection period to the end point of the P-th sustain voltage is (NE) ^. is (t1 + ^{2. t2).} Next, the erase period, i.e., ^E. is applied to the voltage VE during (t1 + ^{2. t2).}

The second field is composed of the selection period, the sustain period, and the erase period in the same manner as the first field, but the polarity of all applied voltages is reversed.

Now, the order of the signal voltages applied to the pixels is described. The signal voltage in the selection period consists of three pulse voltages having pulse widths t1, t2 and t2, respectively, according to the driving voltage waveform applied to the scan electrodes. In order to display a bright image in the first field, a voltage VG having a pulse width t1 is applied, followed by a voltage V8 having a pulse width t2 and a voltage V1 having a pulse width t2. In order to display a dark image in the first field, a voltage VG having a pulse width t1 is applied, followed by a voltage V1 having a pulse width t2 and a voltage V8 having a pulse width t2. In order to display a bright image in the second field, a voltage VG having a pulse width t1 is applied, followed by a voltage V1 having a pulse width t2 and a voltage V8 having a pulse width t2. In order to display a dark image in the second field, a voltage VG having a pulse width t1 is applied, followed by a voltage V8 having a pulse width t2 and a voltage V1 having a pulse width t2. The aforementioned image signal is combined with the waveform of the scan voltage to determine the display state of the pixel.

The refresh pulse voltage applied to the scan electrode at the start of the sustain period is synchronized with the signal voltage VG. That is, the refresh pulse is applied during the period when the signal voltage is VG. Therefore, it is possible to always apply the refresh voltage VRP or VRN having the pulse width t1 irrespective of the combination with the image signal waveform for displaying the bright image or the dark image. Thus, the pixel that has been refreshed can display an image having the same brightness as before, without being influenced by the image signal waveform for another pixel on the same signal electrode, with only the polarity of the sustain voltage being inverted. The voltage applied during the refresh period is not necessarily limited to the voltage VG but may be a voltage corresponding to the reference level voltage of the signal voltage change. Even when a reference level voltage is used instead of VG, substantially the same result can be obtained.

In order to improve the angular visibility characteristics of the display, the polarities of the neighboring scan electrodes are inverted one by one or one group at a time.

In the above-described manner, a voltage having a waveform as shown in Figs. 11, 12 and 13 is applied to the pixels G (i, 1), G (i, 2) and G (i, 3), respectively. The waveform shown in the figure corresponds to a state in which G (i, 1) displays a bright image, G (i, 2) displays a dark image, and G (i, 3) displays a bright image. The voltage applied to each pixel thereof is (t1 + ^2. T2) is the phase shifted by the period. In other words, a series of voltages applied on the pixel G (i, 2) during the selection period, the sustain period and the erase period is compared with the series of voltages applied to the pixel G (i, 1) +2 ^. T2). Similarly, the phase of the voltage applied to the next pixel is shifted by the same period.

Next, the state of the pixel G (i, j) in a state for displaying a bright image will be described with reference to Fig. 14 showing the voltage applied to the pixel and the transmitted light intensity of the anti-ferroelectric liquid crystal. A driving voltage having a waveform as shown in Fig. 14 is applied. In the selection period of the first field, the anti-ferroelectric liquid crystal is in the second stable state (the positive polarized ferroelectric state shown by F + in Fig. 14), and this state continues also during the first sustain period following the selection period. This liquid crystal state is changed from the second stable state to the third stable state (the negative polarized state shown by F- in Fig. 14) by the refresh pulse voltage VRN having the pulse width t1, which is applied at the start of the second sustain period, And this state is maintained during the second sustain period by the sustain voltage. Next, the liquid crystal state is switched from the third stable state to the second stable state by the refresh pulse voltage VRP having the pulse width t1, which is applied at the start of the third sustain period, Lt; / RTI > Thereafter, the switching between the second stable state and the third stable state, which is performed each time the refresh pulse voltage is applied, is repeated. This switching frequency is selected to be, for example, 50 Hz so that the flicker of the display is invisible. At the end of all sustain periods, the state of the liquid crystal is switched to the first stable state (anti-ferroelectric state).

In the second field, the semi-ferroelectric liquid crystal is in the third stable state during the selection period, and this state is also maintained during the first sustain period following the selection period. This state of the liquid crystal is switched from the third stable state to the second stable state by the refresh pulse voltage VRP having the pulse width t1, which is applied at the start of the second sustain period, and this state is applied after the refresh pulse voltage And is maintained during the second sustain period by the sustain voltage. Next, the liquid crystal state is switched from the second stable state to the third stable state by the refresh pulse voltage VRN having the pulse width t1, which is applied at the start of the third sustain period, And is maintained during the third sustain period by the sustain voltage applied thereafter. Thereafter, the switching between the second stable state and the third stable state, which is performed each time the refresh pulse voltage is applied, is repeated. This switching frequency is selected to be, for example, 50 Hz so that the flicker of the display is invisible. At the end of all sustain periods, the state of the liquid crystal is switched to the first stable state (anti-ferroelectric state).

Next, the state of the pixel G (i, j) in a state for displaying a dark image will be described with reference to Fig. 15 showing the voltage applied to the pixel and the transmitted light intensity of the anti-ferroelectric liquid crystal. A driving voltage having a waveform as shown in Fig. 15 is applied. In the selection period of the first field, the anti-ferroelectric liquid crystal is in the first stable state (anti-ferroelectric state shown by AF in Fig. 15), and this state continues also during the first sustain period following the selection period. The liquid crystal state is not switched from the first stable state to the third stable state by the refresh pulse voltage VRN having the pulse width t1 applied at the start of the second sustain period, Is maintained during the second sustain period. Similarly, the state of the liquid crystal is not switched from the first stable state to the second stable state by the refresh pulse voltage VRP having the pulse width t1, which is applied at the start of the third sustain period, Is also maintained during the third sustain period due to the sustain voltage. Thereafter, the first stable state is maintained unaffected by the polarity change that occurs every time the refresh pulse voltage is applied. Further, the liquid crystal is maintained in the first stable state even in the erase period.

In the second field, the semi-ferroelectric liquid crystal is in the first stable state during the selection period, and this state continues also during the first sustain period. The state of the liquid crystal is not switched from the first stable state to the second stable state by the refresh pulse voltage VRP having the pulse width t1 applied at the start of the second sustain period and this state is applied after the refresh pulse voltage And also during the second sustain period by the sustain voltage. Similarly, the state of the liquid crystal is not switched from the first stable state to the third stable state by the refresh pulse voltage VRN having the pulse width t1, which is applied at the start of the third sustain period, And also during the third sustain period by the sustain voltage applied after the voltage. Thereafter, the first stable state is maintained unaffected by the polarity switching performed every time the refresh pulse voltage is applied. During the erase period, the first stable state of the semi-ferroelectric liquid crystal remains unchanged.

As described above, the switching between the positive ferroelectric state and the negative ferroelectric state of the anti-ferroelectric liquid crystal is performed without changing the state of the pixel in the anti-ferroelectric state. Therefore, the display luminance is not changed, and is maintained at the same level before and after the polarity change of the sustain voltage. Therefore, flicker on the display does not appear, and a good image can be obtained. In addition, in the embodiment according to the present invention, image contrast of 40 or more is achieved at 40 占 폚.

The number of times of applying the refresh pulse voltage in one field is not necessarily limited to eight, but may be changed to an appropriate number of times. The polarity of the refresh voltage applied to the scan electrodes is selected such that it alternates in the neighboring sustain periods. In this way, the anti-ferroelectric liquid crystal is driven by an AC voltage, thus preventing a picture stick or preventing it from being imprinted on a pixel.

In the embodiment described here, the polarity of the sustain voltage is selected such that neighboring scan electrodes have opposite polarities during their most sustain periods. However, this may be changed so that neighboring scan electrodes have polarities opposite to each other for a period longer than half of the repetition period of the selection period. The period in which the adjacent scan electrodes have opposite sustain voltage polarities can be determined according to the number of times of application of the refresh pulse voltage.

According to the invention, the polarity switching frequency of the holding voltage appears to be higher to the viewer than the field inversion method.

Thus, it is possible to prevent the flicker on the display caused by the switching of the sustain voltage polarity simultaneously, while maintaining the advantage brought about by the application of the refresh pulse voltage.

In the above-described embodiments, the configuration of the logic circuit may be replaced by a programmed routine of the microprocessor.

Now, a second embodiment according to the present invention will be described with reference to Figs. 16 to 25. Fig. In the second embodiment, the polarity of the selection voltage is not inverted after the erase period, as opposed to the above-described first embodiment, which is inverted every erase period.

As described above, the semi-ferroelectric liquid crystal has three states: an anti-ferroelectric state (AF), a positive ferroelectric state (F +), and a negative ferroelectric state (F-). The image on the panel is displayed by switching the state of the semi-ferroelectric liquid crystal. The switching characteristic between AF and F + and the switching characteristic between AF and F- are not always the same. That is, this characteristic may be asymmetric. If the characteristic is asymmetric and the selection voltage is inverted after the erase period, a flicker may occur in the display. In order to avoid such a problem, the polarity of the selection voltage in the second embodiment is not inverted for a long time, for example, three hours or one day by using a timer provided in the control circuit 20. [ Other configurations and operations of the second embodiment are the same as those of the first embodiment. Therefore, only the difference from the first embodiment will be described later.

16 and 17 (the timing chart of FIG. 16 continues with FIG. 17) is based on the signals (SCC, SI01, SI02, first DP and DR) from the control circuit 20 and the scan electrodes Y1, Y2 and Y3 As shown in FIG. In this timing diagram, E is an erase period, S is a selection period, H + is a positive sustain period, R is a refresh period, and H- is a negative sustain period, all of which are the same as in the first embodiment. In this timing diagram, a selection voltage of the same polarity is applied to the first four selection electrodes, and the polarity thereof is inverted at the fifth selection electrode. This is for illustrative purposes only and, as described above, the same polarity of the selection voltage is maintained for a longer period of time.

18 shows the scan voltage applied to the scan electrodes Y1, Y2 and Y3, the signal voltage on the signal electrode Xi and the brightness of the pixel G (i, 1) in the same manner as in Fig. 10 of the first embodiment. Fig. 19 shows the waveform of the voltage applied to the pixel G (i, 1) in the bright state. Fig. 20 shows the waveform of the voltage applied to the pixel G (i, 2) in the dark state. Fig. 21 shows the waveform of the voltage applied to the pixel G (i, 3) in the bright state. These waveforms are similar to the waveforms in Figs. 10, 11, and 12 of the first embodiment. However, in the second embodiment, the polarity of the selection voltage applied at the beginning of the second field is the same as the polarity of the voltage applied at the beginning of the first field.

Figs. 22 and 23 show waveforms of voltages applied to the pixel G (i, j) in the bright state and the dark state, respectively, in the same manner as in Figs. 14 and 15 of the first embodiment. In Fig. 22, the selection voltage is applied at the start of the first field, where the anti-ferroelectric liquid crystal has the state F + (the second stable state or the positive polarized state) in the first sustain period of the first field. Next, a negative refresh voltage is applied to change the sustain voltage polarity, and the anti-ferroelectric liquid crystal has a state F- (third safe state or negative polarized state) in the second sustain period of the first field. Next, the third, fourth, fifth ... sustain periods are followed, the polarities alternate, the state of the semi-ferroelectric liquid crystal is switched between F + and F-, and then the erase period E follows. At the start of the second field, a selection voltage having the same polarity as that in the first field is applied, and the same process as in the first field is repeated. In the dark state shown in Fig. 23, the anti-ferroelectric liquid crystal has state AF (anti-ferroelectric state or first stable state) from the start of the first field. The state AF is not switched to the F + and F- states by applying the refresh pulse voltage, as described above, and therefore, the state AF is maintained through the first and second fields, as shown in Fig.

Figures 24 and 25 show timing diagrams similar to Figures 16 and 18. However, in Figs. 24 and 25, the sustain voltage is inverted three times in one field, unlike the timings in Figs. 16 and 18, in which the sustain voltage is inverted only once in one field. The number of times the sustain voltage is reversed in one field can be arbitrarily selected as long as it is an odd number. As shown in FIGS. 24 and 25, a selection voltage having the same polarity is applied at the beginning of each field, and the sustain voltage polarity in the first sustain period in each field is maintained the same for a predetermined period. The inversion of the selection voltage polarity can be performed in various ways other than the timer provided in the control circuit 20. [ For example, when the power supply to the apparatus is started, or when the screen saver of the display panel 10 is operated.

Since the anti-ferroelectric state of the anti-ferroelectric liquid crystal is changed to the ferroelectric state of the same polarity for a predetermined long time in the second embodiment, the flicker on the display is further reduced, and even when the anti-ferroelectric liquid crystal has the asymmetric switching characteristic, .

Now, a third embodiment of the present invention will be described with reference to Figs. 26 to 37. Fig. In the third embodiment, in addition to the features of the first and / or second embodiments, the interlaced scanning method in which the scanning electrodes are jumped by one or more neighboring scanning electrodes is adopted. Since most of the configuration and operation of the third embodiment are similar to those of the first or second embodiment, only specific features of the third embodiment will be described later.

26 is an overall configuration diagram of a liquid crystal display device. Here, a control circuit 20A and a scan electrode drive circuit 50A are used in place of the control circuit 20 and the scan electrode drive circuit 50 of the first embodiment. The control circuit 20A outputs the first and second DP, DR, SCC, LCK, STD and SIC signals (which are the same as the output signal of the control circuit 20) SI01a and SI02a signals, and (as an additional signal) ACK signals in place of the SI01 and SI02 signals. Signals SI01a and SI02a determine the state of the scan electrode in the same manner as in the first embodiment, but the waveforms of the SI01a and SI02a signals are different from the signals SI01 and SI02. That is, a period in which SI01a and SI02a both become L corresponds to an erase period E, a period in which SI01a is H and SI02a is L corresponds to a selection period S, and a period in which SI01a and SI02a are both H Corresponds to the sustain period H, and the period in which SI01a is L and SI02a is H corresponds to the refresh period R. [

The scan electrode driving circuit 50A selects seven voltages from the power supply circuit 30 and applies a voltage to the scan electrodes Y1, Y2, Y3 .... in an interlaced manner. In this particular embodiment, interlace scanning is performed by jumping two scan electrodes.

Now, the operation of the scan electrode driving circuit 50A will be described taking the scan electrode Y1 as an example. FIG. 29 shows a scan voltage applied to the scan electrodes together with an input signal to the scan electrode driving circuit 50A, in a similar manner as in FIG. 29 and its subsequent figures, the selection period is represented by S + (positive polarity) or S- (negative polarity), the sustain period is H + or H-, the refresh period is R + or R-, the erase period is RS + . The selection period is divided into three periods, i.e., first, second, and third periods. In the positive selection period (S +), the voltage VE is applied in the first period, the voltage VHP is applied in the second period, and the voltage VWP is applied in the third period. In the negative polarity selection period S-, the voltage VE is applied in the first period, the voltage VHN is applied in the second period, and the voltage VWN is applied in the third period. In the positive polarity erase period (RS +), the voltage VWP is applied at the start point, followed by the voltage VE. In the negative erase period RS-, the voltage VWN is applied at the start point, followed by the voltage VE. This scan electrode driving circuit 50A operates in substantially the same manner as in the scan electrode driving circuit 50 except for the above-described points.

30 shows scan voltages applied to the scan electrodes Y1, Y2, Y3, Y4, Y5, and so on. In this embodiment, since the interlaced scanning method of jumping two neighboring electrodes is used, the scanning electrode Y1 is scanned first, and then, by delaying one selection period with respect to each of the scanned electrodes, in a staggered manner, , Y7, Y10, ... are scanned in that order. In addition, the selection voltage polarity is inverted with respect to each of the electrodes to be scanned. After the scanning of the first row is completed to the lowermost portion, the scanning of the second row is started from the electrode Y2, and then the electrodes Y5, Y8, Y11, ... are scanned in that order. Next, the scanning of the third row is started from the scanning electrode Y3, and then the electrodes Y6, Y9, Y12, ... are scanned in that order. When all of the scan electrodes are scanned in this manner, one screen frame is completed. Next, the scanning of the next screen frame is repeated from the scanning electrode Y1 by using the polarity reversed.

Now, the configuration of the scan electrode driving circuit 50A similar to the configuration of the scan electrode driving circuit 50 shown in Fig. 4 will be described with reference to Fig. 27 and Fig. In this embodiment, as shown in Fig. 27, the 2-bit registers RY1, RY2 ... RYn in Fig. 4 are replaced by 2-bit registers RY'1, RY'2 ... RY'n, , SI02 is replaced by signals SI01a and SI02a, and signal ACK is added. The two-bit registers RY'1 to RY'n receive the signals SI01a and SI02a from the control circuit 20A in synchronization with the rising edge of the ACK signal and output the decoders DY1 to DYn Bit data (bit-1, bit-2).

Fig. 28 shows a detailed view of the 2-bit registers RY'1 to RY'n. Now, the 2-bit registers RY'1 and RY'2 will be described as an example. The 2-bit register RY'1 is comprised of a pair of D-type flip-flops Fa, Fb forming a 1-bit and a pair of D-type flip-flops Fc, Fd forming a 1-bit other. The flip-flops Fb and Fd receive the signals SI01a and SI02a in synchronization with the rise of the ACK signal, respectively, and deliver the outputs from their respective Q terminals to the flip-flops Fa and Fc, respectively. The flip-flops Fa and Fc receive the outputs from the flip-flops Fb and Fd in synchronization with the rise of the SCC signal and output the respective outputs as 2-bit data (bit-1, bit-2) to the decoder DY1 . Similarly, the 2-bit register RY'2 consists of a pair of D-type flip-flops Fa and Fb and a pair of D-type flip-flops Fc and Fd. The flip-flops Fb and Fd of RY'2 receive the outputs from the respective Q terminals of the flip-flops Fb and Fd of RY'1 in synchronization with the rise of the ACK signal and output the outputs from their respective Q terminals And the flip-flops Fa and Fc of RY'2, respectively. The flip-flops Fa and Fc of RY'2 receive the outputs from the flip-flops Fb and Fd of RY'2 in synchronization with the rise of the SCC signal and output the respective outputs to the 2-bit data (bit-1, bit-2) to the decoder DY2. The other two-bit registers RY'3 to RY'n operate in the same manner and transfer their outputs to DY3 to DYn, respectively. The decoders DY1 to DYn are arranged in a manner similar to the first embodiment, in that the 2-bit data from the 2-bit registers RY'1 to RY'n, the first DP signal from the control circuit 20A, And generates seven signals for operating the analog switches WY1 to WYn based on the DR signal from the microcomputer.

The configurations of the decoders DY1 to DYn used in the third embodiment are the same as those of the decoder (shown in Fig. 5) of the first embodiment. The decoders DY1 to DYn operate in the same manner as in the first embodiment except that the signals SI01 and SI02 in the first embodiment are replaced by the signals SI01a and SI02a. As described above, the scan voltage shown in Fig. 29 is supplied from the scan electrode driving circuit 50A to the scan electrodes. Since one clock of the ACC signal corresponds to three clocks of the ACK signal of the third embodiment, interlaced scanning is performed by jumping two scanning electrodes in accordance with the signals SI01a and SI02a, as shown in Fig.

Since the signal electrode driving circuit 60 operates on the basis of the second DP, LCK, SRD, and SIC signals supplied from the control circuit 20A, which are all the same as those of the first embodiment, . Therefore, the signal voltage is applied to the signal electrode in accordance with the timing shown in Fig. 31 in which the signal voltage applied to the signal electrode X1 is illustrated.

Now, an example of the operation of the liquid crystal display device according to the third embodiment will be described with reference to FIGS. 32, 33, and 34. FIG. In this specific example, the frame display frequency is 20 Hz (the display period of one frame is 50 ms), the number of row electrodes (scan electrodes) is 1024, the number of column electrodes (signal electrodes) is 3840, (N = 512), and the erase period is E (E = 12). Fig. 32 shows the voltage applied to the pixel G (ij) and the light transmittance (transmitted light intensity) of the pixel when the pixel in the bright state maintains the same bright state even after the erase period. FIG. 33 shows the applied voltage and the light transmittance when the bright state pixel changes its state to the intermediate state after the erase period. Fig. 34 shows the applied voltage and the light transmittance when the bright state pixel changes its state to a dark state after the erase period. The sustain voltage polarity is inverted to a frequency of 30 Hz or more.

In the positive polarity selection period S +, the voltage VE having the pulse width t1 (t1 = 32.6 mu s) is applied first and then the voltage VWP having the pulse width t2 (t2 = 32.6 mu s) and the voltage VWP Are successively applied as the selection voltage. The pulse widths t1 and t2 correspond to the pulse widths of the first embodiment shown in Fig. 11, but the pulse widths are slightly short. Next, the sustain voltage VHP is applied during the sustain period H +. The refresh voltage VRN having the pulse width t1 is applied during the refresh period R- which starts from 9.7 ms after the start of the selection period S +. Next, the sustain voltage VHN is applied during the sustain period H-, which is calculated after 9.7 ms elapses from the start of the refresh period R-. In the subsequent refresh period R +, the refresh voltage VRP having the pulse width t1 is applied, and then the sustain voltage VHP is applied during the sustain period H +, which is 9.7 ms calculated from the start of the refresh period R + . Thereafter, the same process is repeated until the end point of the Pth sustain period (P = 5 in this specific example). The length of the first field from the start point of the selection period S + to the end point of the fifth sustain period is NE ^. is (t1 + ^{2. t2).} The end point of the fifth sustain period, the voltage VWN having a pulse width t1 is applied, and then, E for removing an image recorded on the pixel G (i, ^j). (t1 + ^2. t2) is the voltage VE applied over the period of -t1.

In the subsequent selection period S-, the voltages VE, VHN and VWN are sequentially applied to the scan electrodes in that order, thereby starting the second field. Thereafter, the same process as described in the first field is repeated.

To display a bright image in the first field, a voltage VG having a pulse width t1, a voltage V8 having a pulse width t2, and a voltage V1 having a pulse width t2 are sequentially applied to the signal electrodes in the selection period. In order to display a dark image in the first field, a voltage VG having a pulse width t1, a voltage V1 having a pulse width t2, and a voltage V8 having a pulse width t2 are sequentially applied to the signal electrodes in the selection period. Conversely, in order to display a bright image in the second field, a voltage VG having a pulse width t1, a voltage V1 having a pulse width t2, and a voltage V8 having a pulse width t2 are applied in that order. To display a dark image in the second field, a voltage VG having a pulse width t1, a voltage V8 having a pulse width t2, and a voltage V1 having a pulse width t2 are applied in that order. To display the intermediate luminance, intermediate voltages V2 to V7 are selected. The refresh voltage is applied to the scan electrode in synchronization with the voltage VG on the signal electrode. Therefore, the level of the refresh pulse VRP or VRN is not influenced by the level of the signal voltage, and the brightness before and after the sustain voltage polarity is inverted is maintained unchanged in the same manner as in the first embodiment.

In the erase period, the bright image or the intermediate image is erased, that is, the pixel becomes dark. The luminance change caused by the erasure is about 2% of the average luminance of one field. Such a change may be seen as a flicker having a frequency of the frame display frequency (20 Hz in the above example) when the progressive scanning method is adopted. In the case of adopting the interlaced scanning method as in the third embodiment, the flicker frequency is increased (in the example described above, three times the frame display frequency, that is, 60 Hz). Therefore, the flicker may become invisible. This will be further described with reference to FIGS. 35A and 35B.

FIG. 35A shows progressive scanning in which the scan electrodes are scanned from the top to the bottom without jumping the electrodes. The average luminance is changed to the same frequency as the frame frequency of 20 Hz as shown in the right graph, which can be seen by the viewer. FIG. 35B shows an interlaced scan in which the scan electrode is scanned by jumping two electrodes (n = 2) as in the third embodiment described above. In this case, the average luminance is changed to a frequency higher than the frame frequency 3 times, that is, 60 Hz, which is not seen as a flicker. The display contrast of the third embodiment becomes about 40 at a temperature of 40 DEG C, and flicker is not seen. Fig. 36 shows the relationship between the number (n) of electrodes jumping under interlaced scanning and the flicker. This figure also shows a scrolling flicker. The flicker and the scrolling flicker are inspected by taking an average luminance change as a parameter. The flicker under progressive scanning was checked for comparison purposes. It can be seen from the figure that flicker is seen when the average luminance change is 2% or more under progressive scanning. Under interlaced scanning (n = 1), flicker is observed when the average luminance change is 5% or more. Further, under the interlaced scanning (n = 2), when the average luminance change is 10%, the flicker is not seen, but a scrolling stripe (which will be described later using another drawing) is observed. Under interlaced scanning (n = 3), a scrolling stripe is observed when the average luminance change is greater than 5%. Under interlaced scanning (n = 4), a scrolling stripe is observed when the average luminance change is greater than 2%. Therefore, from the above description, it is concluded that the optimal number (n) is 2. However, the results shown in the figures are obtained when viewing the panel at a distance of 5 cm from the panel, and the scrolling pricker is no longer visible when viewing the panel at a greater distance. The number n can be two or more in actual use.

Now, with reference to Figs. 37A, 37B and 37C, a scrolling stripe will be described in detail. As shown in FIG. 37A, at time T1, a stripe having a width Ls appears at the top of the panel and moves downward. As can be seen from Fig. 37B, the stripe moves further down at time T2 and appears at the position shown in Fig. 37C at time T3. The scrolling stripe does not always move down, but it may move up depending on the viewer's position or the direction in which the eyes move. As the width Ls becomes narrower, the stripe becomes more invisible. In addition, as the distance from the viewer to the panel increases, the stripe becomes more invisible. If the width Ls is narrower than 5 mm and the distance from the viewer to the panel is in the range of 20 cm to 60 cm (normal distance), the scrolling stripe will normally not be visible.

The features of each of the above-described embodiments (first, second and third embodiments) can be used alone or in combination with features of other embodiments. Although semi-ferroelectric liquid crystals are used in these embodiments, other liquid crystals, such as smectic liquid crystals, having properties similar to those of semi-ferroelectric liquid crystals may be used.

Although the present invention has been shown and described with reference to preferred embodiments thereof, those skilled in the art will recognize that changes may be made in form and detail without departing from the scope of the invention as defined in the claims Can be achieved.

According to the present invention as described above, it is possible to provide a liquid crystal display device in which flicker is not visible.

Claims (14)

n × m pixels constituted by a matrix electrode structure having n rows of scan electrodes Y1 to Yn and m column of signal electrodes X1 to Xn and a liquid crystal 10c interposed between the scan electrodes and the signal electrodes A liquid crystal display panel (10); (20, 20A, 30, 50, 50A) for applying a scan voltage to the scan electrodes, wherein the means comprises a selection period (S) in which a selection voltage is applied and an image is written to the pixels, A sustain period (H) in which an image is held by a sustain voltage whose polarity is inverted at least once, and an erase period (E, RS) in which an image on a pixel is erased, Forming a scan field; (20, 20A, 40, 60) for sequentially applying a signal voltage representing an image to the signal electrode in synchronization with the scan voltage, thereby displaying an image on the display panel, / RTI > When a polarity of the sustain voltage is inverted, a refresh pulse voltage is applied to the scan electrode; The scan voltage is applied to the scan electrode in an interlaced manner by jumping at least one neighboring scan electrode Liquid crystal display device. The method according to claim 1, The liquid crystal 10c is an anti-ferroelectric liquid crystal exhibiting an anti-ferroelectric state (AF), a positive polar ferroelectric state (F +) and a negative polar ferroelectric state (F-), depending on a voltage applied thereto. The refresh pulse voltage applied to the scan electrode causes a change between the positive ferroelectric state (F +) and the negative ferroelectric state (F-), and the ferroelectric state (F + F-) to one of the states does not induce such a level and duration Liquid crystal display device. 3. The method according to claim 1 or 2, Interlace scanning is performed by jumping such a number of neighboring scan electrodes that the flicker on the display is virtually invisible with respect to the scan frequency Liquid crystal display device. The method of claim 3, The number of scanning electrodes jumped in interlaced scanning is in the range of 2 to 4 Liquid crystal display device. 3. The method according to claim 1 or 2, The erase period (E, RS) is shorter than 10% of the duration of one scan field Liquid crystal display device. 3. The method according to claim 1 or 2, The distance of the scan electrodes jumped in the interlaced scanning is selected such that the scrolling stripes on the display are practically invisible Liquid crystal display device. The method according to claim 6, The distance of the scanning electrode jumped in the interlaced scanning is 5 mm or less Liquid crystal display device. 3. The method according to claim 1 or 2, The polarity of the sustain voltage applied to the neighboring scan electrodes is opposite to that during one period longer than half of one scan field Liquid crystal display device. 3. The method according to claim 1 or 2, The refresh pulse voltage is applied to the scan electrode when the signal voltage applied to the signal electrode is at the reference level (VG) Liquid crystal display device. 3. The method according to claim 1 or 2, The polarity of the selection voltage applied to the scan electrodes in the selection period is inverted every field Liquid crystal display device. 3. The method according to claim 1 or 2, In the selection period, the polarity of the selection voltage applied to the scan electrodes is inverted for each of a plurality of fields Liquid crystal display device. 3. The method according to claim 1 or 2, The polarity of the selection voltage applied to the scan electrodes in the selection period is inverted every time the power supply to the display device is newly started Liquid crystal display device. 3. The method according to claim 1 or 2, The polarity of the selection voltage applied to the scan electrodes in the selection period is inverted every time the screen saver is in operation Liquid crystal display device. 3. The method according to claim 1 or 2, The polarity of the sustain voltage is inverted odd times in one scan field Liquid crystal display device.