KR19980065652A - Alignment Key Formation Method of Semiconductor Device - Google Patents
Alignment Key Formation Method of Semiconductor Device Download PDFInfo
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- KR19980065652A KR19980065652A KR1019970000764A KR19970000764A KR19980065652A KR 19980065652 A KR19980065652 A KR 19980065652A KR 1019970000764 A KR1019970000764 A KR 1019970000764A KR 19970000764 A KR19970000764 A KR 19970000764A KR 19980065652 A KR19980065652 A KR 19980065652A
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- alignment key
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
반도체소자 얼라인 키 제조방법을 개시하고 있다. 이는, 물질층과 플로우되는 성질을 갖는 절연막을 적층하여 형성하는 얼라인 키 제조방법에 있어서, 상기 얼라인 키는 오버-랩(Over-lap)될 각 층별로 분리하여 제작되는 것을 특징으로 하는 반도체소자 얼라인 키 제조방법을 제공한다. 각 공정단계별로 어미자 얼라인 키 세트를 분리하여 제작함으로써 어미자 얼라인 키의 축소가 4 방향에서 일어나도록 유도한다. 따라서, 어미자 얼라인 키의 4 방향에서 동일한 크기로 축소가 일어나기 때문에, 다음 단계에서 형성되는 아들자에 대한 어미자의 쉬프트는 발생되지 않는다.A method for manufacturing a semiconductor device alignment key is disclosed. This is an alignment key manufacturing method in which an insulating film having a property of flowing with a material layer is formed, wherein the alignment key is manufactured by separating each layer to be over-lapd. Provided is a device alignment key manufacturing method. By separating and aligning the mother alignment key set for each process step, the reduction of the mother alignment key occurs in four directions. Therefore, since the reduction occurs in the same size in the four directions of the mother align key, the shift of the mother with respect to the son formed in the next step does not occur.
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 얼라인 키 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an alignment key.
매몰 비트라인 형성시, 그 아래 및 위로 형성되는 층간절연막으로써 BPSG 또는 PSG와 같이 유동성 있는 산화물을 통상적으로 사용하고 있다. 이와 같은 BPSG 또는 PSG와 같은 물질들은 일정온도 이상에서 플로우(Flow)되는 성질을 갖고 있다. 예를 들어 비트라인 아래에 형성되는 제1 층간절연막으로서 BPSG층을 형성하고, 그 위에 비트라인으로서 폴리실리콘과 텅스텐실리사이드를 적층하고, 비트라인 위에 형성되는 제2 층간절연막으로서 BPSG층을 형성한다. 이 경우 제2 층간절연막의 평탄화를 목적으로 플로우를 실시하게 되는데, 이때 제1 층간절연막과 제2 층간절연막 사이에 위치하는 비트라인의 수축(Shrink)이 발생된다. 즉, 비트라인으로 형성된 텅스텐실리사이드층은 증착시의 비정질 상태에서 제2 층간절연막이 플로우되는 온도에서 결정화(Crystalization) 되어 축소된다.In forming a buried bitline, a fluid oxide such as BPSG or PSG is commonly used as an interlayer insulating film formed below and over. Such materials such as BPSG or PSG have a property of flowing above a certain temperature. For example, a BPSG layer is formed as a first interlayer insulating film formed under a bit line, polysilicon and tungsten silicide are laminated thereon as a bit line, and a BPSG layer is formed as a second interlayer insulating film formed over a bit line. In this case, a flow is performed for the purpose of flattening the second interlayer insulating film. In this case, shrinkage of the bit line positioned between the first interlayer insulating film and the second interlayer insulating film occurs. That is, the tungsten silicide layer formed of the bit line is crystallized at the temperature at which the second interlayer insulating film flows in the amorphous state during deposition and is reduced.
일반적으로 메모리 셀 내에서는 텅스텐 실리사이드층의 축소가 일어나도 항상 물질의 중심으로 향해 일어나기 때문에 큰 문제가 되지 않으나, 스크라이브 라인(Scribe Line)내의 얼라인 키(Align key)가 축소되어 다음 공정단계에 영향을 미치게 된다.In general, even if the tungsten silicide layer shrinks in the memory cell, it always occurs toward the center of the material, so it is not a big problem. Go crazy.
도 1은 종래의 얼라인 키를 도시한 평면도이고, 도 2 및 도 3은 종래의 비트라인 얼라인 키를 도시한 단면도 및 평면도이다.1 is a plan view showing a conventional align key, Figures 2 and 3 are a cross-sectional view and a plan view showing a conventional bit line align key.
도 1을 참조하면, 종래의 얼라인 키에 있어서 비트라인의 어미자 세트가 떡판 형태로 묶여 있는 경우, 어미자(1) 위에 아들자(3)가 다음 스텝에서 형성된다.Referring to Fig. 1, in the case of a conventional align key in which a set of bit lines is bound in a shape of a rice cake plate, a son 3 is formed on the mother 1 in the next step.
도 2 및 도 3을 참조하면, 비트라인 형성시 스크라이브 라인 내에 비트라인 얼라인 키도 함께 형성되는데, 이때 제1 층간절연막(5)과 제2 층간절연막(9) 사이에 형성된 텅스텐 실리사이드층(7)의 수축으로 인해, 비트라인 형성단계의 어미자가 축소된다. 따라서, 도 3에 도시된 바와 같이 여러 종류의 얼라인 키가 합쳐져 있는 경우, 얼라인 키의 양쪽 끝부분은 세 방향에서 수축되고, 가운데 부분은 아래 위 두 방향에서 수축된다. 이와 같이 어미자가 쉬프트됨에 따라 다음 단계에서 형성되는 아들자의 얼라인먼트 불량이 발생된다.2 and 3, a bit line align key is also formed in a scribe line when the bit line is formed, wherein a tungsten silicide layer 7 formed between the first interlayer insulating film 5 and the second interlayer insulating film 9 is formed. Due to shrinkage of the bitline forming step. Therefore, when several kinds of alignment keys are combined as shown in FIG. 3, both ends of the alignment keys are contracted in three directions, and the center portion is contracted in two directions. As the mother is shifted in this manner, alignment defects of the son formed in the next step are generated.
본 발명이 이루고자 하는 기술적 과제는, 어미자 얼라인 키의 축소가 일어나더라도 이의 쉬프트를 최소화할 수 있는 얼라인 키를 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an alignment key capable of minimizing a shift of the mother alignment key even if it is reduced.
도 1은 종래의 얼라인 키를 도시한 평면도이다.1 is a plan view showing a conventional alignment key.
도 2 및 도 3은 종래의 비트라인 얼라인 키를 도시한 단면도 및 평면도이다.2 and 3 are a cross-sectional view and a plan view showing a conventional bit line align key.
도 4는 본 발명의 일 실시예에 따른 얼라인 키를 도시한 평면도이다.4 is a plan view illustrating an align key according to an embodiment of the present invention.
상기 과제를 이루기 위하여 본 발명은, 물질층과 플로우되는 성질을 갖는 절연막을 적층하여 형성하는 얼라인 키 제조방법에 있어서, 상기 얼라인 키는 오버-랩(Over-lap)될 각 층별로 분리하여 제작되는 것을 특징으로 하는 반도체소자 얼라인 키 제조방법을 제공한다.In order to achieve the above object, the present invention, in the alignment key manufacturing method for forming an insulating film having a property of flowing with the material layer, the alignment key is separated by each layer to be over-lap (Over-lap) It provides a method for manufacturing a semiconductor device alignment key, characterized in that the manufacturing.
각 공정단계별로 어미자 얼라인 키 세트를 분리하여 제작함으로써 어미자 얼라인 키의 축소가 4 방향에서 일어나도록 유도한다. 따라서, 어미자 얼라인 키의 4 방향에서 동일한 크기로 축소가 일어나기 때문에, 다음 단계에서 형성되는 아들자에 대한 어미자의 쉬프트는 발생되지 않는다.By separating and aligning the mother alignment key set for each process step, the reduction of the mother alignment key occurs in four directions. Therefore, since the reduction occurs in the same size in the four directions of the mother align key, the shift of the mother with respect to the son formed in the next step does not occur.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명의 일 실시예에 따른 얼라인 키를 도시한 평면도이다.4 is a plan view illustrating an align key according to an embodiment of the present invention.
도 4를 참조하면, 본 발명에 따른 얼라인 키는 어미자 얼라인 키(50)를 분리하여 형성한다. 본 발명에 따르면, 제1 층간절연막과 제2 층간절연막이 플로우되는 성질을 갖는 물질로 형성되고, 그 사이에 온도에 대한 영향에 따라 쉽게 변형이 일어나는 물질, 예컨대 금속실리사이드층이 형성될 때 이 변형에 대한 영향을 최소화하기 위해 어미자의 형성을 여러층 묶어서 형성하지 않고 분리하여 형성한다. 즉, 각 공정단계별로 어미자 얼라인 키 세트를 분리하여 제작함으로써 어미자 얼라인 키의 축소가 4 방향에서 일어나도록 유도한다. 이와 같이, 어미자 얼라인 키의 4 방향에서 동일한 크기로 축소가 일어나기 때문에, 다음 단계에서 형성되는 아들자에 대한 어미자의 쉬프트는 발생되지 않는다.Referring to FIG. 4, the align key according to the present invention is formed by separating the mother align key 50. According to the present invention, the first interlayer insulating film and the second interlayer insulating film are formed of a material having a property of flowing, and when the material easily deforms in accordance with the influence on temperature, for example, when the metal silicide layer is formed, the deformation is formed. In order to minimize the impact on the mother, the formation of the mother layer is formed separately without forming a bundle. That is, by dividing the mother align key set for each process step, the reduction of the mother align key is induced in four directions. In this way, since the reduction occurs to the same size in the four directions of the mother alignment key, the shift of the mother relative to the son formed in the next step does not occur.
상술한 바와 같이 본 발명에 따르면, 각 공정단계별로 어미자 얼라인 키 세트를 분리하여 제작함으로써 어미자 얼라인 키의 축소가 4 방향에서 일어나도록 유도한다. 따라서, 어미자 얼라인 키의 4 방향에서 동일한 크기로 축소가 일어나기 때문에, 다음 단계에서 형성되는 아들자에 대한 어미자의 쉬프트는 발생되지 않는다.As described above, according to the present invention, by dividing the mother align key set for each process step, the mother align key is reduced in four directions. Therefore, since the reduction occurs in the same size in the four directions of the mother align key, the shift of the mother with respect to the son formed in the next step does not occur.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970000764A KR19980065652A (en) | 1997-01-14 | 1997-01-14 | Alignment Key Formation Method of Semiconductor Device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970000764A KR19980065652A (en) | 1997-01-14 | 1997-01-14 | Alignment Key Formation Method of Semiconductor Device |
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| Publication Number | Publication Date |
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| KR19980065652A true KR19980065652A (en) | 1998-10-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019970000764A Withdrawn KR19980065652A (en) | 1997-01-14 | 1997-01-14 | Alignment Key Formation Method of Semiconductor Device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100870316B1 (en) * | 2006-12-28 | 2008-11-25 | 주식회사 하이닉스반도체 | Overlay vernier of semiconductor device and manufacturing method thereof |
-
1997
- 1997-01-14 KR KR1019970000764A patent/KR19980065652A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100870316B1 (en) * | 2006-12-28 | 2008-11-25 | 주식회사 하이닉스반도체 | Overlay vernier of semiconductor device and manufacturing method thereof |
| US7595258B2 (en) | 2006-12-28 | 2009-09-29 | Hynix Semiconductor Inc. | Overlay vernier of semiconductor device and method of manufacturing the same |
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Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19970114 |
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