KR19980058576A - Area Array Bumped Semiconductor Package Molding Mold - Google Patents
Area Array Bumped Semiconductor Package Molding Mold Download PDFInfo
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- KR19980058576A KR19980058576A KR1019960077903A KR19960077903A KR19980058576A KR 19980058576 A KR19980058576 A KR 19980058576A KR 1019960077903 A KR1019960077903 A KR 1019960077903A KR 19960077903 A KR19960077903 A KR 19960077903A KR 19980058576 A KR19980058576 A KR 19980058576A
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- semiconductor package
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- bumped semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 에어리어 어레이 범프드 반도체 패키지 몰딩 금형에 관한 것으로서, 반도체 패키지의 저면으로 리드의 돌출부가 어레이 형태로 배열되는 에어리어 어레이 범프드 반도체 패키지 몰딩금형에 있어서, 상기의 몰딩금형에 리드의 돌출부가 위치되는 부분에는 돌출턱을 형성하여 몰딩 후 리드의 돌출부에 솔더볼 안착홈이 형성되도록 하여 상기한 솔더볼 안착부를 이용하여 솔더볼의 결합력을 증가시키는 에어리어 범프드 반도체 패키지 몰딩금형을 제공한다.The present invention relates to an area array bumped semiconductor package molding mold, wherein in the area array bumped semiconductor package molding mold in which the protrusions of the leads are arranged in an array form on the bottom surface of the semiconductor package, the protrusions of the leads are positioned in the molding mold. To form a protruding jaw to form a solder ball seating groove formed in the protrusion of the lead after molding to provide an area bumped semiconductor package molding mold to increase the bonding force of the solder ball using the solder ball seating portion.
Description
본 발명은 에어리어 어레이 범프드 반도체 패키지 몰딩금형에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 저면에 어레이 형태로 리드의 돌출부가 배열되어 있는 에어리어 어레이 범프드 반도체 패키지를 몰딩할 때, 반도체 패키지의 저면으로 배열되는 리드의 돌출부 주위에 솔더볼 안착부가 형성되도록 함으로써 솔더볼의 결합력을 증가시키도록 된 에어리어 어레이 범프드 반도체 패키지 몰딩금형에 관한 것이다.The present invention relates to an area array bumped semiconductor package molding mold, and more particularly, to a bottom surface of a semiconductor package when molding an area array bumped semiconductor package in which protrusions of leads are arranged in an array form on the bottom of the semiconductor package. The area array bumped semiconductor package molding mold is adapted to increase the bonding force of the solder balls by causing the solder ball seating portions to be formed around the protrusions of the arranged leads.
일반적으로 반도체 패키지는 패키지의 종류에 따라 수지 밀봉 패키지, TCP 패키지, 글래스 밀봉 패키지, 금속 밀봉 패키지 등이 있다. 이와 같은 반도체 패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology,SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array)등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array)등이 있다. 최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체 패키지 대신에 표면실장형 반도체 패키지가 널리 사용되고 있는 추세이다.In general, semiconductor packages include resin sealing packages, TCP packages, glass sealing packages, and metal sealing packages, depending on the type of package. Such semiconductor packages are classified into insertion type and surface mount technology (SMT) type according to the mounting method. Representative types of insertion type include DIP (Dual In-line Package) and PGA (Pin Grid Array). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array). Recently, in order to increase the mounting degree of components of a printed circuit board according to the miniaturization of electronic products, surface-mount semiconductor packages have been widely used instead of insertable semiconductor packages.
이와 같은 종래의 반도체 패키지에 대한 이해를 돕기 위하여, 대표적으로 BGA에 대하여 설명하기로 한다. 도 1은 종래의 BGA(Ball Grid Array ; 볼 그리드 어레이) 반도체 패키지의 측단면도이다. 도 1에 도시되어 있는 바와 같이 종래의 BGA반도체 패키지의 구성은, 기판(21)과, 상기한 기판(21)의 중앙 상면에 에폭시(22)로 접착되어 있는 반도체칩(23)과, 상기한 기판(21)의 표면에 형성되어 있는 메탈 트레이스(24)와, 상기한 반도체칩(23)의 입출력 패드(25)와 메탈 트레이스(24)를 연결하는 와이어(26)와, 상기한 메탈 트레이스(24)에 형성되어 있는 랜드 메탈(27)과, 상기한 랜드 메탈(28)에 융착되어 있는 솔더볼(28)과, 상기한 반도체칩(23)과 와이어(26)등을 외부환경으로부터 보호하기 위한 몰딩물(29)로 이루어진다.In order to help the understanding of such a conventional semiconductor package, a representative BGA will be described. 1 is a side cross-sectional view of a conventional ball grid array (BGA) semiconductor package. As shown in FIG. 1, the structure of a conventional BGA semiconductor package includes a substrate 21, a semiconductor chip 23 bonded to an epoxy 22 on a center upper surface of the substrate 21, and the above-mentioned. The metal trace 24 formed on the surface of the substrate 21, the wire 26 connecting the input / output pad 25 and the metal trace 24 of the semiconductor chip 23, and the metal trace ( To protect the land metal 27 formed on the ground metal 27, the solder ball 28 fused to the land metal 28, the semiconductor chip 23, the wire 26, and the like from the external environment. It consists of a molding (29).
그러나, 상기한 바와 같은 종래의 BGA 반도체 패키지는, 기판(21)이 고가이기 때문에 제품의 가격이 상승되는 문제점이 있고, 또한 상기한 기판(21)을 통해서 습기가 침투됨으로써 크랙이 발생하게 되는 문제점이 있다.However, the conventional BGA semiconductor package as described above has a problem in that the price of the product is increased because the substrate 21 is expensive, and cracks are generated due to moisture infiltration through the substrate 21. There is this.
이와 같은 문제점을 해결하기 위하여, BGA 반도체 패키지 방식이 아니면서도, 기판 접속리드를 패키지의 외부로 돌출시키지 않고 패키지의 저면으로 노출시킴으로써 실장면적을 줄일 수 있는 기술이 대한민국 실용신안 등록출원 공개번호 제96-3195호(공개일: 서기 1996년 1월 22일)의 버텀 리드형 반도체 패키지에서 개시된 바 있다.In order to solve such a problem, a technology that can reduce the mounting area by exposing the substrate connection lead to the bottom of the package without protruding the outside of the package without the BGA semiconductor package method is disclosed in Korean Utility Model Publication No. 96 -3195 (published: January 22, 1996) was disclosed in a bottom leaded semiconductor package.
그러나, 상기한 종래의 버텀 리드형 반도체 패키지는 단순히 리드를 일렬로 배열하여 놓았기 때문에 실장 면적을 효율적으로 줄일 수 없는 문제점이 있다.However, the conventional bottom lead type semiconductor package has a problem in that the mounting area cannot be efficiently reduced because the leads are simply arranged in a line.
이와 같은 문제점을 해결하기 위하여, 리드의 돌출부가 패키지의 저면에 어레이 형태로 배열되도록 함으로써 실장면적을 효율적으로 줄임과 동시에 저렴한 비용으로 구성할 수가 있는 반도체 패키지에 관한 기술이 대한민국 특허출원 출원번호 제96-22899호(출원일자: 서기 1996년 6월 21일)의 리드 어레이형 리드 프레임 및 이를 이용한 반도체 패키지에서 본 출원인에 의해 개시된 바 있다.In order to solve such a problem, a technology for a semiconductor package that can be configured at a low cost while efficiently reducing the mounting area by arranging the protrusions of the leads in an array form on the bottom of the package is disclosed in Korean Patent Application No. 96 -22899 (filed June 21, 1996 AD) has been disclosed by the applicant in a lead array type lead frame and a semiconductor package using the same.
그러나, 상기한 종래의 리드 어레이형 리드 프레임 및 이를 이용한 반도체 패키지는 리드팁에 솔더볼을 형성하는 경우에 솔더볼 안착부가 형성되어 있지 않기 때문에 상대적으로 결합력이 떨어지게 되는 문제점이 있다.However, the conventional lead array type lead frame and the semiconductor package using the same have a problem in that the bonding force is relatively lowered because the solder ball seating portion is not formed when the solder ball is formed on the lead tip.
본 발명의 목적은 상기한 문제점을 개선하여 보완하기 위한 것으로서, 리드의 돌출부가 패키지의 저면에 어레이 형태로 배열되어 있는 에어리어 어레이 범프드 반도체 패키지를 몰딩할 때, 상기한 돌출부의 주위에 솔더볼 안착부가 형성되도록 하는 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to remedy and to solve the above-mentioned problems, and when soldering an area array bumped semiconductor package in which the protrusions of the leads are arranged in an array form on the bottom of the package, the solder ball seating portion is formed around the protrusions. To provide an area array bumped semiconductor package molding mold to be formed.
도 1은 종래의 BGA 반도체 패키지를 나타낸 단면도1 is a cross-sectional view showing a conventional BGA semiconductor package
도 2는 본 발명의 제1실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 설명하기 위한 단면도2 is a cross-sectional view illustrating an area array bumped semiconductor package molding mold according to a first embodiment of the present invention.
도 3은 본 발명의 제1 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형의 요부를 도시한 도면3 is a view illustrating main parts of an area array bumped semiconductor package molding mold according to a first embodiment of the present invention;
도 4는 본 발명의 제1 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형에 의해 형성된 솔더볼 안착부에 솔더볼이 안착되는 상태를 도시한 도면4 is a view showing a state in which a solder ball is seated on the solder ball seating portion formed by the area array bumped semiconductor package molding mold according to the first embodiment of the present invention.
도 5는 본 발명의 제2 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 도시한 도면5 illustrates an area array bumped semiconductor package molding mold according to a second embodiment of the present invention.
도 6은 본 발명의 제3 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 설명하기 위한 단면도6 is a cross-sectional view illustrating an area array bumped semiconductor package molding mold according to a third embodiment of the present invention.
상기한 목적을 달성하기 위한 수단으로서 본 발명의 구성은, 반도체 패키지의 저면으로 리드의 돌출부가 어레이 형태로 배열되는 에어리어 어레이 범프드 반도체 패키지 몰딩금형에 있어서, 상기의 몰딩금형에 리드의 돌출부가 위치되는 부분에 돌출턱을 형성한 구조로 이루어지는 것으로, 이러한 몰딩금형을 이용하여 몰딩물로 몰딩을 하고 나면, 상기 리드의 돌출부 주위에는 솔더볼 안착홈이 형성되는 것이다.As a means for achieving the above object, in the configuration of the present invention, in the area array bumped semiconductor package molding mold in which the protrusions of the leads are arranged in an array form on the bottom surface of the semiconductor package, the protrusions of the leads are positioned in the molding mold. The protrusion jaw is formed in a portion to be formed. After molding with a molding using the molding mold, solder ball seating grooves are formed around the protrusion of the lead.
상기의 돌출턱은 제1 실시예에서와 같이 중앙부에 홈을 형성할 수 있고, 제3 실시예에서와 같이 홈을 형성하지 않아도 되는 것이다. 또한, 제2 실시예에서와 같이 상기의 돌출턱이 형성되는 부분에는 돌출턱을 형성하지 않고, 이젝터핀을 돌출되도록 형성하여도 되는 것이다.The protruding jaw can form a groove in the center portion as in the first embodiment, and it is not necessary to form the groove as in the third embodiment. Also, as in the second embodiment, the ejector jaw may be formed to protrude the ejector pin without forming the protrusion jaw at the portion where the protrusion jaw is formed.
이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조로 하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.
도 2는 본 발명의 제1 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 설명하기 위한 단면도이다. 도 2에 도시되어 있는 바와 같이, 본 발명의 제1 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형은, 반도체칩(31)과, 상기한 반도체칩(31)을 지지하고 있는 리드(32)와, 상기한 반도체칩(31)이 상기한 리드(32)의 위에 고정되도록 접착시켜주는 접착부재(33)와, 상기한 반도체칩(31)과 리드(32)의 위에 고정되도록 접착시켜주는 접착부재(33)와, 상기한 반도체칩(31)과 리드(32)를 전기적으로 상호 연결시켜주는 와이어(35)를 몰딩물(34)로 몰딩함에 있어서, 상기한 리드(32)의 돌출부의 주위에 솔더볼 안착부(37)가 형성되도록 몰딩금형(36)에 돌출턱(36a)을 형성시킨 형상으로 이루어진다.2 is a cross-sectional view illustrating an area array bumped semiconductor package molding mold according to a first embodiment of the present invention. As shown in FIG. 2, the area array bumped semiconductor package molding mold according to the first embodiment of the present invention includes a semiconductor chip 31 and a lead 32 supporting the semiconductor chip 31. And an adhesive member 33 for fixing the semiconductor chip 31 to be fixed on the lead 32, and an adhesive for fixing the semiconductor chip 31 and the lead 32 to be fixed. In molding the member 33 and the wire 35 which electrically connects the semiconductor chip 31 and the lead 32 to the molding 34, the periphery of the protrusion of the lead 32 is formed. The protruding jaw 36a is formed in the molding die 36 so that the solder ball seating portion 37 is formed.
상기한 바와 같은 구조를 갖는 몰딩금형을 이용한, 반도체 패키지의 제조과정은 다음과 같이 이루어진다. 먼저, 리드(32)의 위에 접착부재(33)를 이용하여 반도체칩(31)을 부착시킨 뒤에, 상기한 반도체칩(31)의 패드와 리드(32)를 전기적으로 연결하기 위하여 와이어(35)를 본딩시킨다. 와이어 본딩이 끝나면, 상기한 조립체를 몰딩금형(36)에 놓고 몰딩물(34)을 주입함으로써 몰딩이 이루어지도록 한다. 이 경우에, 상기한 리드(32)의 돌출부는 몰딩금형(36)에 형성되어 있는 돌출턱(36a)에 안착되어 이 부분에는 몰딩물이 침투되지 못하므로, 몰딩 공정이 끝난 후에 몰딩금형(36)이 제거되고 나면, 리드(32)의 돌출부의 주변에는 솔더볼 안착부(37)가 형성된다. 도 3은 이와 같이 솔더볼 안착부(37)를 형성하기 위해 몰딩금형(36)에 형성된 돌출턱(36a)의 요부를 보여주고 있다. 상기한 몰딩금형(36)의 돌출턱(36a)에는 중앙부에 홈(36a')이 형성되어 상기 홈(36a')에 리드의 끝단이 위치됨으로 몰딩 공정이 완료되면, 이 부분이 솔더볼 안착부(37)로 되고, 상기한 솔더볼 안착부(37)는 리드(32)의 돌출부에 솔더볼(38)이 놓여지는 경우에 솔더볼(38)이 접촉되는 부위를 증가시키게 됨으로써 상대적으로 솔더볼(38)의 결합력을 높여주게 된다. 도 4는 솔더볼 안착부(37)에 솔더볼(38)이 안착되어 있는 모습을 보여주고 있다.The manufacturing process of the semiconductor package using the molding mold having the structure as described above is performed as follows. First, the semiconductor chip 31 is attached to the lead 32 using the adhesive member 33, and then the wire 35 is used to electrically connect the pad and the lead 32 of the semiconductor chip 31. Bond the. After the wire bonding is finished, the assembly is placed in the molding mold 36 and the molding is injected by injecting the molding 34. In this case, the protrusion of the lead 32 is seated on the protrusion jaw 36a formed in the molding die 36 so that the molding does not penetrate the portion, and thus the molding die 36 is finished after the molding process. After removal of), the solder ball seating portion 37 is formed around the protrusion of the lead 32. 3 shows the main portion of the protruding jaw 36a formed in the molding die 36 in order to form the solder ball seating portion 37. A groove 36a 'is formed at the center of the protrusion 36a of the molding die 36 so that the end of the lead is positioned in the groove 36a'. When the molding process is completed, this portion is the solder ball seating portion ( 37), and the solder ball seating portion 37 increases the portion where the solder ball 38 is in contact with the solder ball 38 when the solder ball 38 is placed on the protruding portion of the lead 32, so that the bonding force of the solder ball 38 is relatively high. Will increase. 4 shows a state in which the solder ball 38 is seated on the solder ball seating portion 37.
도 5는 본 발명의 제2 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 의한 설명하기 위한 요부 확대도이다. 도 5에 도시되어 있는 본 발명의 제2 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형은, 도 2에 도시되어 있는 제1 실시예와 비교하여 볼 때, 리드(32)의 돌출부 하단이 위치되는 몰딩금형(36)에 돌출부를 형성하지 않고, 이젝터핀(39)을 추가로 돌출 설치되는 구조로 이루어진다. 상기한 이젝터핀(39)은 몰딩이 끝나게 되면 리드(32)를 밀어 올림으로써 반도체 패키지가 몰딩금형(36)으로부터 용이하게 분리되도록 하는 기능을 갖는다.5 is an enlarged view illustrating main parts of an area array bumped semiconductor package molding mold according to a second embodiment of the present invention. In the area array bumped semiconductor package molding mold according to the second embodiment of the present invention illustrated in FIG. 5, the lower end of the protruding portion of the lid 32 is positioned in comparison with the first embodiment shown in FIG. 2. Without forming a protrusion on the molding mold 36 to be formed, the ejector pin 39 is made of a structure that is additionally installed. The ejector pin 39 has a function of allowing the semiconductor package to be easily separated from the molding die 36 by pushing the lead 32 when the molding is finished.
도 6은 본 발명의 제3 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 설명하기 위한 단면도이다. 도 6에 도시되어 있는 본 발명의 제3 실시예에 따른 에어리어 어레이 범프드 반도체 패키지 몰딩금형(36)은, 도 2에 도시되어 있는 제1 실시예와 비교하여 볼 때, 리드(32)의 돌출부 하단이 위치되는 몰딩금형(36)에 형성된 돌출턱(36a)의 중앙부에 홈을 형성하지 않은 점을 제외하고는 동일하다. 즉, 도2에 도시되어 있는 제1 실시예에서는 솔더볼 안착부가 리드(32)의 돌출부의 주변에 형성되는데 반해서, 도6에 도시되어 있는 제3 실시예에서는 솔더볼 안착부가 리드(32)의 돌출부의 아래 부분에 형성된다.6 is a cross-sectional view illustrating an area array bumped semiconductor package molding mold according to a third embodiment of the present invention. The area array bumped semiconductor package molding mold 36 according to the third embodiment of the present invention shown in FIG. 6 is a projection of the lead 32 as compared to the first embodiment shown in FIG. 2. The same is true except that a groove is not formed in the center of the protruding jaw 36a formed in the molding mold 36 at which the lower end is positioned. That is, in the first embodiment shown in FIG. 2, the solder ball seating portion is formed around the protrusion of the lead 32, whereas in the third embodiment shown in FIG. 6, the solder ball seating portion is the protrusion of the lead 32. It is formed in the lower part.
이상에서와 같이 본 발명에 의하면, 리드의 돌출부의 주위에 솔더볼 안착부가 형성되도록 함으로써 솔더볼의 결합력을 상대적으로 강화시킬 수 있는 효과를 갖는 에어리어 어레이 범프드 반도체 패키지 몰딩금형을 제공할 수가 있다.As described above, according to the present invention, it is possible to provide an area array bumped semiconductor package molding mold having an effect of relatively increasing the bonding force of the solder balls by having the solder ball seating portions formed around the protrusions of the leads.
없음none
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960077903A KR100337462B1 (en) | 1996-12-30 | 1996-12-30 | Area Array Bumped Semiconductor Package Molding Mold |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960077903A KR100337462B1 (en) | 1996-12-30 | 1996-12-30 | Area Array Bumped Semiconductor Package Molding Mold |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980058576A true KR19980058576A (en) | 1998-10-07 |
| KR100337462B1 KR100337462B1 (en) | 2002-11-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960077903A Expired - Fee Related KR100337462B1 (en) | 1996-12-30 | 1996-12-30 | Area Array Bumped Semiconductor Package Molding Mold |
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| KR (1) | KR100337462B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505357B1 (en) * | 1999-12-14 | 2005-08-04 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| KR100575859B1 (en) * | 1999-06-18 | 2006-05-03 | 주식회사 하이닉스반도체 | Ball grid array package |
| KR100723532B1 (en) * | 2006-06-19 | 2007-05-30 | 삼성전자주식회사 | Mold for forming conductive bumps, method for manufacturing the mold, and method for forming bump on wafer using the mold |
-
1996
- 1996-12-30 KR KR1019960077903A patent/KR100337462B1/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100575859B1 (en) * | 1999-06-18 | 2006-05-03 | 주식회사 하이닉스반도체 | Ball grid array package |
| KR100505357B1 (en) * | 1999-12-14 | 2005-08-04 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| KR100723532B1 (en) * | 2006-06-19 | 2007-05-30 | 삼성전자주식회사 | Mold for forming conductive bumps, method for manufacturing the mold, and method for forming bump on wafer using the mold |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100337462B1 (en) | 2002-11-07 |
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