KR19980029365A - Method of manufacturing ferroelectric capacitor - Google Patents
Method of manufacturing ferroelectric capacitor Download PDFInfo
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- KR19980029365A KR19980029365A KR1019960048620A KR19960048620A KR19980029365A KR 19980029365 A KR19980029365 A KR 19980029365A KR 1019960048620 A KR1019960048620 A KR 1019960048620A KR 19960048620 A KR19960048620 A KR 19960048620A KR 19980029365 A KR19980029365 A KR 19980029365A
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
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- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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Abstract
강유전체 캐패시터의 제조방법에 대해 기재되어 있다. 이는, 캐패시터용 하부전극을 형성하는 단계와, 상에 피.지.티(PZT; PbZrTiO3) 박막을 형성하는 단계 및 피.지.티(PZT) 박막 상에 도전물질을 300℃ 이상의 온도에서 증착하여 상부전극을 형성하는 단계를 포함하는 것을 특징으로 한다. 따라서, PZT의 전기적 특성을 DRAM에 적용가능하도록 변화시킬 수 있으므로, 유전상수는 BST보다 크면서 퍼티그(fatigue) 현상이 나타나지 않는 PZT 박막을 형성할 수 있다.A method for producing a ferroelectric capacitor is described. This includes forming a lower electrode for a capacitor, forming a PbZrTiO 3 thin film thereon, and conducting a conductive material at a temperature of 300 ° C. or higher on the thin film P.T. And depositing an upper electrode to form the upper electrode. Therefore, since the electrical properties of the PZT can be changed to be applicable to DRAM, it is possible to form a PZT thin film having a dielectric constant greater than BST and no putig.
Description
본 발명은 강유전체 메모리장치의 제조방법에 관한 것으로, 특히 퍼티그(fatigue) 현상이 없는 피.지.티(PZT) 박막을 형성함으로써 디램(DRAM)의 제조에 적용가능한 강유전체 캐패시터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ferroelectric memory device, and more particularly, to a method of manufacturing a ferroelectric capacitor applicable to the manufacture of DRAM by forming a PZT thin film without a puttigue phenomenon. will be.
반도체 메모리장치가 고집적화되어 감에 따라 셀 면적도 감소하고 있다. 이러한 셀 면적의 감소에 따른 셀 캐패시턴스의 감소는 메모리 셀의 독출능력을 저하시키고 소프트 에러(soft error)율을 증가시킬 뿐만 아니라, 저전압에서의 소자동작을 어렵게 하여 소자동작시 전력소모를 과다하게 한다. 따라서, 메모리 셀의 동작특성을 저하시키지 않을 정도의 충분한 셀 캐패시턴스의 확보가 요구된다.As semiconductor memory devices become more integrated, the cell area is also decreasing. The decrease in cell capacitance due to the decrease of the cell area not only reduces the readability of the memory cell and increases the soft error rate, but also makes the device difficult to operate at low voltage, resulting in excessive power consumption during device operation. . Therefore, it is required to secure sufficient cell capacitance such that the operating characteristics of the memory cell are not degraded.
제한된 셀 면적에서 메모리 셀의 캐패시턴스를 증가시키기 위한 방법으로는, 유전체막을 박막화하는 방법, 캐패시터의 유효면적을 증가시키는 방법, 그리고 유전상수가 큰 물질을 유전체막으로 사용하는 방법 등이 있다. 이 중 유전체막의 두께를 100Å 이하로 박막화하는 경우에는, 파울러 - 노드하임 전류 (Fowler - Nodheim current)에 의해 소자의 신뢰성이 저하되므로, 대용량 메모리장치에 적용하기가 어렵다는 단점이 있다. 그리고, 캐패시터의 구조를 입체화하는 방법은 3차원구조의 캐패시터를 제조하기 위한 복잡한 공정이 수반되고, 이에 따라 제조단가의 상승을 피할 수 없는 단점이 있다.As a method for increasing the capacitance of a memory cell in a limited cell area, a method of thinning a dielectric film, a method of increasing an effective area of a capacitor, and a method of using a material having a high dielectric constant as a dielectric film. Among them, when the thickness of the dielectric film is reduced to 100 Å or less, the reliability of the device is reduced by the Fowler-Nodheim current, which makes it difficult to apply to a large-capacity memory device. In addition, a method of three-dimensionally reducing the structure of a capacitor involves a complicated process for manufacturing a three-dimensional capacitor, and thus, an increase in manufacturing cost is inevitable.
이에 따라, 최근에는 세 번째 방법인 유전율이 큰 페로브스카이트(Perovskite) 구조의 산화물로 이루어진 유전체(이하, 강유전체라 통칭함), 예를 들어 피.지.티(PZT; PbZrTiO3) 또는 비.에스.티(BST; BaSrTiO3) 계열의 강유전체를 사용하여 유전체막을 형성하는 방법들이 제안되고 있다. 이 중 상기 BST는 유전상수가 300정도로서, 기존의 실리콘질화막(SiN)의 유전상수인 7보다 40배 이상 크기 때문에, 캐패시터 구조의 입체화 없이도 원하는 크기의 셀 캐패시턴스를 확보할 수 있다. 그런데, PZT는 유전상수가 1,000 정도로서 BST에 비해 큰데도 불구하고 DRAM에 적용되지 못하고 있는 데, 그 이유는 PZT는 BST와는 달리 강유전성을 나타내고 퍼티그(fatigue)라는 독특한 특성을 가지고 있기 때문이다. 이 퍼티그(fatigue) 현상은 캐패시터에 데이터를 반복해서 기록할 때 그 저장능력이 계속적으로 열화되는 현상으로서, PZT의 경우 106싸이클(cycle) 이상이 되면 이러한 퍼티그(fatigue) 현상이 심하게 나타난다.Accordingly, in recent years, a third method, a dielectric having a high permittivity perovskite structure (hereinafter referred to as ferroelectric), for example, P. T. (PZT; PbZrTiO 3 ) or non- A method of forming a dielectric film using a ferroelectric of BST (BST; BaSrTiO 3 ) series has been proposed. Among these, the BST has a dielectric constant of about 300, and is 40 times larger than that of the silicon nitride layer (SiN), which is 7 times higher than that of the conventional silicon nitride layer (SiN), thereby securing a cell capacitance having a desired size without condensing the capacitor structure. However, PZT has a dielectric constant of about 1,000 and is not applied to DRAM even though it is larger than BST, because PZT has a ferroelectric property and a unique characteristic of fatigue, unlike BST. This putig (fatigue) is a phenomenon that the storage capacity is continuously deteriorated when the data is repeatedly recorded in the capacitor, and in the case of PZT, this putti (fatigue) is severe when more than 10 6 cycles (cycle) .
본 발명이 이루고자 하는 기술적 과제는, PZT의 강유전 특성을 paraelectric 특성으로 바꾸어 줌으로써, 고유전특성을 지니면서도 퍼티그(fatigue)가 없는 PZT막질을 얻을 있는 강유전체 캐패시터의 제조방법을 제공하는 것이다.The technical problem to be achieved by the present invention is to provide a method of manufacturing a ferroelectric capacitor which can obtain a PZT film having a high dielectric property and no puttigue by changing the ferroelectric property of the PZT into a paraelectric property.
도 1 및 도 2는 본 발명의 제1 실시예에 의한 강유전체 캐패시터의 제조방법을 설명하기 위한 단면도이다.1 and 2 are cross-sectional views illustrating a method of manufacturing a ferroelectric capacitor according to a first embodiment of the present invention.
도 3은 본 발명의 제2 실시예에 의한 강유전체 캐패시터의 제조방법을 설명하기 위한 단면도이다.3 is a cross-sectional view illustrating a method of manufacturing a ferroelectric capacitor according to a second embodiment of the present invention.
상기 과제를 이루기 위하여 본 발명에 의한 강유전체 캐패시터의 제조방법은, 캐패시터용 하부전극을 형성하는 단계; 상기 하부전극 상에 피.지.티(PZT; PbZrTiO3) 박막을 형성하는 단계; 및 상기 피.지.티(PZT) 박막 상에 도전물질을 300℃ 이상의 온도에서 증착하여 상부전극을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a ferroelectric capacitor according to the present invention includes the steps of forming a lower electrode for a capacitor; Forming a P. T. (PZT; PbZrTiO 3 ) thin film on the lower electrode; And depositing a conductive material on the PZT thin film at a temperature of 300 ° C. or higher to form an upper electrode.
상기 과제를 이루기 위하여 본 발명에 의한 강유전체 캐패시터의 다른 제조방법은, 캐패시터용 하부전극을 형성하는 단계; 상기 하부전극 상에 피.지.티(PZT; PbZrTiO3) 박막을 형성하는 단계; 상기 피.지.티(PZT) 박막 상에 상부전극을 형성하는 단계; 상기 상부전극 상에 장벽금속막을 형성하는 단계; 및 상기 장벽금속막을 열처리하는 단계를 포함하는 것을 특징으로 한다.Another method of manufacturing the ferroelectric capacitor according to the present invention for achieving the above object is the step of forming a capacitor lower electrode; Forming a P. T. (PZT; PbZrTiO 3 ) thin film on the lower electrode; Forming an upper electrode on the PZT thin film; Forming a barrier metal film on the upper electrode; And heat-treating the barrier metal film.
본 발명에 따르면, 페로브스카이트 구조로 PZT 박막을 형성한 후에 상부전극의 증착온도를 300℃ 이상으로 높이거나, 질소분위기 하에서 열처리를 실시하면 PZT의 전기적 특성을 DRAM에 적용가능하도록 변화시킬 수 있다. 그리하여 유전상수는 BST보다 크면서 강유전체에서 나타나는 퍼티그(fatigue) 현상도 나타나지 않는 PZT 박막을 형성할 수 있다.According to the present invention, after the PZT thin film is formed with the perovskite structure, the deposition temperature of the upper electrode is increased to 300 ° C. or higher, or heat treatment is performed under nitrogen atmosphere to change the electrical characteristics of the PZT to be applicable to DRAM. have. Thus, it is possible to form a PZT thin film having a dielectric constant greater than that of BST but without the fatigue phenomenon seen in ferroelectrics.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 1 및 도 2는 본 발명의 제1 실시예에 의한 강유전체 캐패시터의 제조방법을 설명하기 위한 단면도이다.1 and 2 are cross-sectional views illustrating a method of manufacturing a ferroelectric capacitor according to a first embodiment of the present invention.
도 1을 참조하면, 먼저 보론-인을 함유하는 실리콘막(BPSG)과 같은 절연막(10) 위에 접착층(adhesion layer)으로 티타늄(Ti)(20)을 증착한 후, 백금(Pt)을 증착하여 캐패시터의 하부전극(30)을 형성한다. 그 후, 상기 하부전극(30) 위에 PZT(40)를 코팅한 다음, 650℃ 정도의 온도에서 30분간 열처리한다. 상기 열처리에 의해 상기 PZT(40)가 페로브스카이트 구조로 결정화되면서 강유전 특성을 갖게 된다.Referring to FIG. 1, first, a titanium (Ti) 20 is deposited on an insulating layer 10, such as a silicon film (BPSG) containing boron-phosphorus, as an adhesion layer, followed by deposition of platinum (Pt). The lower electrode 30 of the capacitor is formed. Thereafter, the PZT 40 is coated on the lower electrode 30, and then heat-treated at a temperature of about 650 ° C. for 30 minutes. The PZT 40 crystallizes into a perovskite structure by the heat treatment, and thus has ferroelectric characteristics.
도 2를 참조하면, PZT(40)를 어닐링하여 고유전특성을 갖는 페로브스카이트 구조로 만든 후에, 300℃ 이상의 온도에서 백금(Pt)을 증착하여 상부전극(50)을 형성한다.Referring to FIG. 2, after annealing the PZT 40 to form a perovskite structure having high dielectric properties, platinum (Pt) is deposited at a temperature of 300 ° C. or higher to form an upper electrode 50.
이 때, 상기 상부전극용 백금(50)의 증착온도에 따라서 PZT(40)의 특성이 크게 변화한다. 즉, 상부전극용 백금(Pt)을 상온에서 증착하면 PZT의 강유전 특성이 그대로 유지되고, 300℃ 이상의 고온에서 증착하면 PZT의 전기적 특성이 paraelectric으로 변한다. 따라서, 페로브스카이트 구조로 PZT 박막을 형성한 후에 상부전극의 증착온도를 300℃ 이상으로 높이면, PZT의 전기적 특성을 DRAM에 적용가능하도록 변화시킬 수 있다. 그리하여 유전상수는 BST보다 크면서 강유전체에서 나타나는 퍼티그(fatigue) 현상도 나타나지 않는 PZT 박막을 형성할 수 있다.At this time, the characteristics of the PZT 40 vary greatly according to the deposition temperature of the upper electrode platinum 50. That is, when the upper electrode platinum (Pt) is deposited at room temperature, the ferroelectric properties of the PZT are maintained as it is, and when deposited at a high temperature of 300 ° C. or higher, the electrical properties of the PZT are changed to paraelectric. Therefore, after the PZT thin film is formed with the perovskite structure, if the deposition temperature of the upper electrode is increased to 300 ° C. or more, the electrical characteristics of the PZT can be changed to be applicable to DRAM. Thus, it is possible to form a PZT thin film having a dielectric constant greater than that of BST but without the fatigue phenomenon seen in ferroelectrics.
도 3은 본 발명의 제2 실시예에 의한 PZT 박막의 형성방법을 설명하기 위한 단면도이다.3 is a cross-sectional view for describing a method of forming a PZT thin film according to a second embodiment of the present invention.
도 3을 참조하면, 본 발명의 제1 실시예와 동일한 방법으로 PZT박막(40) 위에 백금을 증착하는데, 상온에서 증착함으로써 PZT의 강유전 특성을 유지시킨다. 다음에, 상기 상부전극(50) 위에 티타늄(Ti)을 얇게 증착한 후 질소(N2) 분위기하에서 약 400℃ 이상의 고온에서 열처리를 실시하면, 상기 티타늄(Ti)이 PZT박막(40) 속으로 확산되어 PZT(40)의 전기적 특성이 강유전성에서 paraelectric으로 바뀌게 된다.Referring to FIG. 3, platinum is deposited on the PZT thin film 40 in the same manner as in the first embodiment of the present invention. The ferroelectric properties of PZT are maintained by deposition at room temperature. Next, when titanium (Ti) is thinly deposited on the upper electrode 50 and heat-treated at a high temperature of about 400 ° C. or higher in a nitrogen (N 2 ) atmosphere, the titanium (Ti) is transferred into the PZT thin film 40. The diffusion causes the electrical properties of the PZT 40 to change from ferroelectric to paraelectric.
상기한 본 발명의 제1 및 제2 실시예에서 상기 캐패시터의 상부전극(50)과 하부전극(30)은 백금(Pt)뿐만 아니라, 루테늄(Ru; Ruthenium), 이리듐(Ir; Iridium) 등의 귀금속류와, 산화이리듐(IrO2) 또는 산화루테늄(RuO2) 등의 전도성 산화물을 사용하여 형성할 수 있다.In the first and second embodiments of the present invention, the upper electrode 50 and the lower electrode 30 of the capacitor are not only platinum (Pt) but also ruthenium (Ru) and iridium (Irdium). Precious metals and conductive oxides such as iridium oxide (IrO 2 ) or ruthenium oxide (RuO 2 ) can be formed.
이상 본 발명을 상세히 설명하였으나, 본 발명은 이에 한정되지 않고 본 발명의 기술적 사상내에서 많은 변형이 가능하다.Although the present invention has been described in detail above, the present invention is not limited thereto, and many modifications are possible within the technical idea of the present invention.
상술한 본 발명에 의한 강유전체 캐패시터의 제조방법에 따르면, 페로브스카이트 구조로 PZT 박막을 형성한 후에 상부전극의 증착온도를 300℃ 이상으로 높이거나, 질소분위기 하에서 열처리를 실시하면 PZT의 전기적 특성을 DRAM에 적용가능하도록 변화시킬 수 있다. 그리하여 유전상수는 BST보다 크면서 강유전체에서 나타나는 퍼티그(fatigue) 현상도 나타나지 않는 PZT 박막을 형성할 수 있다.According to the method of manufacturing the ferroelectric capacitor according to the present invention, after forming the PZT thin film with a perovskite structure, the deposition temperature of the upper electrode is increased to 300 ℃ or more, or heat treatment under nitrogen atmosphere, the electrical characteristics of the PZT Can be changed to be applicable to DRAM. Thus, it is possible to form a PZT thin film having a dielectric constant greater than that of BST but without the fatigue phenomenon seen in ferroelectrics.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100454582B1 (en) * | 1999-01-15 | 2004-10-28 | 오리온전기 주식회사 | LTCC-M Embedded Capacitor And Manufacture Method Thereof |
| KR100687433B1 (en) * | 2000-07-29 | 2007-02-26 | 주식회사 하이닉스반도체 | Method of forming lower electrode of capacitor |
| KR100541799B1 (en) * | 1998-08-06 | 2007-04-25 | 삼성전자주식회사 | Capacitor Manufacturing Method for Semiconductor Devices |
-
1996
- 1996-10-25 KR KR1019960048620A patent/KR19980029365A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541799B1 (en) * | 1998-08-06 | 2007-04-25 | 삼성전자주식회사 | Capacitor Manufacturing Method for Semiconductor Devices |
| KR100454582B1 (en) * | 1999-01-15 | 2004-10-28 | 오리온전기 주식회사 | LTCC-M Embedded Capacitor And Manufacture Method Thereof |
| KR100687433B1 (en) * | 2000-07-29 | 2007-02-26 | 주식회사 하이닉스반도체 | Method of forming lower electrode of capacitor |
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