KR19980026205A - Memory Cells in Nonvolatile Semiconductor Memory Devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell of a nonvolatile semiconductor memory device. In order to improve chip reliability, memory cells of a nonvolatile semiconductor memory device formed on a semiconductor substrate may include first and second impurity diffusion layers formed in the semiconductor substrate. A first selection transistor having a channel formed between the first and second impurity diffusion layers and having a gate formed on the channel via an oxide film; A capacitor having a gate poly layer formed on the second impurity diffusion layer via a dielectric layer; A second selection transistor having third and fourth impurity diffusion layers formed in the semiconductor substrate, a channel formed between the third and fourth impurity diffusion layers, and a gate formed through an oxide film on the channel Wow; And a sense transistor having a fifth impurity diffusion layer formed adjacent to the fourth impurity diffusion layer, a tunnel oxide formed on the fourth impurity diffusion layer, and having a gate having a width greater than that of the tunnel oxide. do.

Description

Memory Cells in Nonvolatile Semiconductor Memory Devices

The present invention relates to a memory cell of a nonvolatile semiconductor memory device, and more particularly to a memory cell of a nonvolatile semiconductor memory device for improving the reliability of a chip.

Recently, in the case of a nonvolatile semiconductor memory device such as a single polysilicon (Single PolySi) EEPROM, attention has been focused on reliability.

1 is a layout showing a memory cell of a single polysilicon EEPROM according to an embodiment of the prior art.

As shown in FIG. 1, since only a single polysilicon of the memory cell is used as a gate, the gate materials of the selection transistors T1 and T2 and the sense transistor T3 are the same. The voltage applied to the bit line BL and the control gate is designed to be transferred to the floating section and the control gate section through the word line WL, respectively. The floating gate is connected to the floating gate and the tunnel oxide layer through coupling with a sense transistor T3 which serves as a programming transistor having a thin oxide region, the tunnel oxide layer 104 at the bottom, for programming and erasing through Fowler Nordim tunneling. A coupling capacitor C1 having a dielectric layer of a high capacitor, for example, an ONO structure (an oxide film / nitride film / oxide film is sequentially stacked) between the control gate cushion and a high voltage can be applied to both ends of 104.

In the memory cell, reference numeral 105 denotes a gate 108 as an implantation region for forming the tunnel oxide layer 104 and the lower region of the coupling capacitor C1 as a high doped region. Before metal deposition. The operation of this basic memory cell is the same as that of a normal EEPROM.

The problem with the memory cell is that the tunnel oxide film 104 formed at the bottom of the programming transistor T3 having the floating gate extends toward the active region 101 than the programming transistor T3 of the floating gate 108 as shown in FIG. The tunnel oxide film 104 is exposed at both ends of the floating gate 108 because it is formed. That is, as both ends of the tunnel oxide film 104 are exposed out of the gate 108, damage may occur in a process after gate patterning. For example, damage to the tunnel oxide film can be caused by plasma damage in a subsequent etching step, impurity trapping in a subsequent implantation step, and wet etching damage in a subsequent cleaning step. This results in deterioration of the properties of tension and endurance.

Accordingly, an object of the present invention is to provide a memory cell of a nonvolatile semiconductor device capable of increasing the reliability of a memory chip.

It is another object of the present invention to provide a memory cell of a nonvolatile semiconductor memory device capable of preventing retention and durability degradation due to plasma damage or wet etching damage that may occur in a subsequent process after gate patterning.

1 is a layout schematically showing a memory cell of a nonvolatile semiconductor memory device implemented according to an embodiment of the prior art.

2 is a layout schematically illustrating a memory cell of a nonvolatile semiconductor memory device implemented according to an embodiment of the present invention.

3 is a cross-sectional view of the layout shown in FIG. 2 taken from A to A 'in accordance with another embodiment of the present invention.

4 is a cross-sectional view of the layout shown in FIG. 2 taken from B to B 'in accordance with another embodiment of the present invention.

5 is an equivalent circuit diagram of a memory cell of a general nonvolatile semiconductor memory device.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

2 is a layout of a memory cell of a nonvolatile semiconductor memory device constructed according to an embodiment of the present invention, and FIG. 3 is a process of cutting the layout shown in FIG. 2 from A to A 'according to another embodiment of the present invention. 4 is a cross-sectional view of the layout shown in FIG. 2 taken from B to B 'according to another embodiment of the present invention. 5 is an equivalent circuit diagram of a memory cell of a general nonvolatile semiconductor memory device.

2 to 5, unlike the related art, the tunnel oxide film 204 which is a path of electrons due to tunneling is completely included at the bottom of the floating gate 208 which serves to store the charge. In such a structure, since the tunnel oxide film 204 at the bottom of the floating gate is not affected by the process after the gate patterning, the characteristic of the oxide film can be maintained.

3 is a vertical cross-sectional view cut along A to A 'in accordance with the present invention wherein contact 207 represents a control gate metal contact and transistor T11 adjacent to contact 207 represents a select transistor by a wordline gate. The impurity diffusion layer 205, which is an N + and N- caption, is a high concentration en-type impurity ion implantation. The capacitor C11 between the gates plays the same role as the capacitor between the control gate and the floating gate in the normal EEPROM cell. In other words, the N-function substantially acts as a control gate.

4 is a vertical cross-sectional view of the layout shown in FIG. 2 taken from B to B '. It consists of a bit line contact 207 from the left, a select transistor T12 consisting of a word line WL gate and N + and N− options 302 and 305. The N-section is also formed by implanting N- ions into the semiconductor substrate 301, and has a gate oxide and a thin oxide tunnel oxide film 204 on top thereof, and a floating gate 202 on top of the tunnel oxide film 204. Has a sense transistor T13. The thin oxide 204 where the Fowler Nordim tunneling takes place is located inside the floating gate to avoid exposure to the process after gate patterning.

As described above, the present invention has the advantage of increasing the reliability of the memory chip. In addition, the present invention has the advantage of preventing retention and durability degradation due to plasma damage or wet etching damage that may occur in subsequent processes after gate patterning.

Claims (6)

In a memory cell of a nonvolatile semiconductor memory device formed on a semiconductor substrate: A first selection transistor having first and second impurity diffusion layers formed in the semiconductor substrate, a channel formed between the first and second impurity diffusion layers, and having a gate formed on the channel via an oxide film Wow; A capacitor having a gate poly layer formed on the second impurity diffusion layer via a dielectric layer; A second selection transistor having third and fourth impurity diffusion layers formed in the semiconductor substrate, a channel formed between the third and fourth impurity diffusion layers, and a gate formed through an oxide film on the channel Wow; And a sense transistor having a fifth impurity diffusion layer formed adjacent to the fourth impurity diffusion layer, a tunnel oxide formed on the fourth impurity diffusion layer, and having a gate having a width greater than that of the tunnel oxide. Memory cells of a semiconductor memory device. The memory cell of claim 1, wherein the second impurity diffusion layer is used as a source when the first impurity diffusion layer is used as a drain. The memory cell of claim 2, wherein the drain is connected to a control gate line. The memory cell of claim 1, wherein the fourth impurity diffusion layer is used as a source when the third impurity diffusion layer is used as a drain. The memory cell of claim 4, wherein the third impurity diffusion layer is connected to a bit line. The memory cell of claim 1, wherein the dielectric layer is a dielectric layer having a structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked.