KR19980025721A - Matching device between UTOPIA interface and FIFO interface at ATM terminal - Google Patents

Abstract

The present invention relates to the matching of UTOPIA (Universal Test and Operation Physical Interface for ATM) interface and FIFO (First In First Out) interface in an Asynchronous Transfer Mode (ATM) terminal, in particular, an ATM layer and a physical layer. It relates to a matching device of a UTOPIA interface and a FIFO interface in an ATM terminal to enable a multi-ATM configuration not supported by the standard UTOPIA interface.

Conventionally, multiple ATM configurations are not possible with the standard UTOPIA interface itself, and the FIFO interface provided by each manufacturer is compatible only with the corresponding manufacturer, and not with the corresponding UTOPIA interface.

According to the present invention, an ATM chip of a UTOPIA interface is matched to a physical layer chip of one FIFO interface providing a control signal, and a plurality of ports are provided in the FIFO interface. You can resolve the inconsistencies that occur when you take multiple ATM configurations that are not supported by the standard UTOPIA interface.

Description

Matching device between UTOPIA interface and FIFO interface at ATM terminal

The present invention relates to the matching of UTOPIA (Universal Test and Operation Physical Interface for ATM) interface and FIFO (First In First Out) interface in an Asynchronous Transfer Mode (ATM) terminal, in particular, an ATM layer and a physical layer. It relates to a matching device of a UTOPIA interface and a FIFO interface in an ATM terminal to enable a multi-ATM configuration not supported by the standard UTOPIA interface.

In general, the interface between the ATM layer and the physical layer includes the UTOPIA interface of the standard proposed by the ATM Forum, and interfaces implemented independently by each manufacturer. The UTOPIA interface is a level 1 that supports a single physical. There are Level 2 interfaces that support interfaces and Multi-Physical.

When the UTOPIA interface is adopted, the configuration of one physical chip and one ATM chip and the configuration of one ATM chip and several physical chips can be easily implemented. Configuration to the board is not possible. In other words, an inconsistency occurs when trying to take a multi-ATM configuration on an interface between an ATM layer and a physical layer, because the UTOPIA interface does not support multiple ATMs.

In other words, in the UTOPIA interface, a standard between the physical layer and the ATM layer, the data path is basically 8 (bits) and additionally 16 (bits) can be used, and control signals are enabled on the ATM layer chip. There are signal and interface byte clock, full / empty flag applied to the physical layer chip, and state of cell applied at the layer providing data. That is, the control of the UTOPIA interface is performed at the ATM layer chip side, and only the status signal (Empty Flag * / Full Flag *) is provided at the physical layer chip side, but one ATM layer chip manages several physical chips. A physical layer chip of a PC cannot control multiple ATM layer chips.

In addition, although there are many interfaces that are independently implemented by each manufacturer, for example, in the case of the FIFO interface, the FIFO interface controls the transmission of data on the physical layer side compared to the corresponding UTOPIA interface that controls the transmission of data on the ATM layer side. do. Accordingly, the FIFO interface can control multiple ATM layer chips from one physical layer chip, thereby implementing a multi-ATM configuration.

However, the FIFO interface is not a standard, so different manufacturers have different signals or methods between interfaces, and many chips that support the UTOPIA interface cannot be used.

As such, in the related art, multiple ATM configurations are not possible with the standard UTOPIA interface itself, and the FIFO interface provided by each manufacturer is compatible only with the corresponding manufacturer, but not with the corresponding UTOPIA interface.

In order to solve the above problems, the present invention provides a matching device of the UTOPIA interface and the FIFO interface in the ATM terminal to solve the inconsistency that occurs when taking a multi- ATM configuration that is not supported by the standard UTOPIA interface between the ATM layer and the physical layer. It aims to do it.

In order to achieve the above object, the present invention receives a first transmission enable signal and transmission data from an ATM layer chip of a UTOPIA interface, stores a corresponding transmission data, and then a second transmission is applied from a physical layer chip of a FIFO interface. A transmission FIFO for outputting to a physical layer chip of a corresponding FIFO interface in accordance with the enable signal; A receiving FIFO receiving the second receiving enable signal and data from the physical layer chip of the FIFO interface and storing the data and outputting the received data according to the first receiving enable signal applied from the ATM layer chip of the UTOPIA interface; The first transmit enable signal, the first receive enable signal, and the second transmit enable signal and the second receive enable signal are received from the physical layer chip of the FIFO interface by the ATM layer chip of the UTOPIA interface. A counter providing a number of bytes of data accumulated in the memory; In accordance with the number of bytes applied from the counter according to the synchronization of the transmit clock and the receive clock applied from the ATM layer chip of the UTOPIA interface, the transmit empty flag and the receive empty flag are applied to the physical layer chip of the FIFO interface. And control logic for applying the received empty signal to the ATM layer chip of the UTOPIA interface.

1 is a block diagram illustrating a matching device of an UTOPIA interface and a FIFO interface in an ATM terminal according to an embodiment of the present invention.

FIG. 2 shows a state machine at the time of transmission in FIG. 1; FIG.

3 shows a state machine at the time of reception in FIG.

Explanation of symbols on the main parts of the drawings

10: shift register 20: flip flop

30: data processing unit 40: voltage controlled clock oscillator

Hereinafter, with reference to the accompanying drawings will be described as follows.

In the ATM terminal according to the embodiment of the present invention, the matching device of the UTOPIA interface and the FIFO interface includes a transmitting FIFO 11, a receiving FIFO 12, a counter 20, and the like, as shown in FIG. 1. Is done.

The transmission FIFO 11 receives the first transmission enable signal TxEN1 * and transmission data TxD from the ATM layer chip of the UTOPIA interface and stores the transmission data TxD to compensate for the difference in transmission speed. Is output to the physical layer chip of the FIFO interface according to the second transmit enable signal TxEN2 * applied from the physical layer chip of the FIFO interface.

The receiving FIFO 12 receives the second receiving enable signal RxEN2 * and data from the physical layer chip of the FIFO interface, stores the data to compensate for the difference in transmission rate, and then stores the corresponding data from the ATM layer chip of the UTOPIA interface. The data is output as the reception data RxD according to the applied first reception enable signal RxEN1 *.

The counter 20 includes a first transmit enable signal TxEN1 * and a first receive enable signal RxEN1 * from an ATM layer chip of the UTOPIA interface, and a second transmit enable signal TxEN2 from a physical layer chip of the FIFO interface. *) And the second receive enable signal RxEN2 * are supplied to provide the number of bytes of data accumulated in the transmission FIFO 11 and the reception FIFO 12.

The control logic 30 generates when the bytes are idle according to the number of bytes applied from the counter 20 in synchronization with the transmission clock TxCLK and the reception clock RxCLK applied from the ATM layer chip of the UTOPIA interface. The transmit empty flag (Tx_EF *) and the receive empty flag (Rx_EF *) generated when the byte is n are applied to the physical layer chip of the FIFO interface, and the transmit pool signal (TxFULL *) generated when the byte is n-4 or more. The reception empty signal (RxEMPTY *) generated when the and bytes are 4 or less is applied to the ATM layer chip of the UTOPIA interface.

In the ATM terminal according to the embodiment of the present invention, the matching device of the UTOPIA interface and the FIFO interface operates as follows.

When implementing an ATM terminal, the first thing to know is that connecting multiple lines to the corresponding ATM terminal is inefficient and expensive. Therefore, it is important to connect only one line. In order to realize this, the physical layer chip must be able to control several ATM layer chips.

In order to be able to control as described above, the physical layer chip must support the FIFO interface and match the FIFO interface and the UTOPIA interface as follows.

When matching, the data transmission size is the same as 8 (bits), but the types and directions of control signals are different, and since the FIFO interface and the UTOPIA interface become masters to provide corresponding control signals, speeds are inconsistent with each other.

Therefore, in order to compensate for the difference in transmission speeds, the transmission FIFO 11 receives and stores transmission data (TxD) from the ATM layer chip of the UTOPIA interface and outputs it to the physical layer chip of the FIFO interface. 12) receives and stores data from the physical layer chip of the FIFO interface and outputs the received data (RxD) to the ATM layer chip of the UTOPIA interface.

The control logic 30 then applies the control signal to the physical layer chip of the FIFO interface and the ATM layer chip of the UTOPIA interface.

Then, the operation at the time of transmission in more detail, first, 8 (bit) data TxD is transmitted to the transmission FIFO 11 while applying the transmission enable signal TxEnb * from the ATM layer chip of the UTOPIA interface. The transmission FIFO 11 stores the data TxD. The transmission state machine describes the state of the transmission FIFO 11 as follows.

First, when the transmission enable signal TxEnb * is applied and the 0 data Txd is stored in the transmission FIFO 11, the state transitions to a 1 (byte) state, and then the transmission enable signal TxEnb * ) Is applied, then transitions to the 3 (byte) and 4 (byte) states as if transitioning to the 2 (byte) state. In addition, the last state n (byte) indicates the maximum number of bytes that the transmission FIFO 11 can store, and thus adjusts the corresponding n (byte) state according to the size of the transmission FIFO 11.

On the contrary, applying the transmit enable signal TxEn * from the physical layer chip of the FIFO interface reads 1 (byte) of data from the transmit FIFO 11, so that the state machine transmits the state of the transmit FIFO 11. The number of bytes indicated in the state becomes the number of bytes accumulated in the transmission FIFO 11 as a result of the transition to the direction in which the bytes decrease and the transition.

2 shows a condition for generating a plaque. The transmit empty flag Tx_EF * is required by the physical layer chip of the FIFO interface and is transmitted when the byte to be read is not present in the transmitting FIFO 11. Applied when the state machine is transmit idle (Tx_IDLE), the transmit pool signal (TxFULL *) is required by the ATM chip of the UTOPIA interface and can be used for up to 4 (bytes). Enabled when between n (bytes) states. Here, since data is stored in the transmission FIFO 11 by the transmission clock TxCLK, the transmission state machine should be operated in synchronization with the transmission clock TxCLK.

On the other hand, the operation at the time of reception, first, the reception FIFO 12 receives the second reception enable signal RxEN2 * and data from the physical layer chip of the FIFO interface to compensate for the difference in transmission speed. The data is stored and output as the reception data RxD according to the first reception enable signal RxEN1 * applied from the ATM layer chip of the UTOPIA interface.

However, since the state transition is the same as performing the operation at the time of transmission, the description thereof is omitted.

In addition, in FIG. 3, the generation condition of the flag is shown. The reception pull flag (Rx_FF *) indicates that data is no longer available in the physical layer chip of the FIFO interface. Since the reception empty signal RxEMPTY * is a signal that can be read up to 4 (bytes) from the ATM chip of the UTOPIA interface, it is enabled in the 4 (bytes) state or more. Since the data is stored in the reception FIFO 12 by the reception clock RxCLK, the corresponding transmission state machine should be operated in synchronization with the reception clock RxCLK.

In this way, by matching the ATM chip of the UTOPIA interface to the physical layer chip of one FIFO interface providing the control signal, the FIFO interface can provide multiple ports to implement multiple ATM configurations. A configuration is implemented to enable muxing and demuxing data of AAL1 (ATM Adaptation Layer 1), AAL3 / 4, and AAL5 in hardware.

As described above, since the ATM chip of the UTOPIA interface is matched to the physical layer chip of one FIFO interface providing the control signal and the multiple ports are provided in the FIFO interface, an ATM layer can be realized. It can resolve the inconsistencies that occur when taking multiple ATM configurations that are not supported by the standard UTOPIA interface between the physical and physical layers.

Claims (1)

In the matching device of the UTOPIA interface and the FIFO interface in an ATM terminal, the first transmission enable signal (TxEN1 *) and the transmission data (TxD) are applied from the ATM layer chip of the UTOPIA interface to compensate for the difference in transmission speed. A transmission FIFO 11 for storing the data TxD and outputting the data TxD to the physical layer chip of the FIFO interface according to the second transmission enable signal TxEN2 * applied from the physical layer chip of the FIFO interface; In order to compensate for the difference in transmission speed by receiving the second receive enable signal RxEN2 * and data from the physical layer chip of the FIFO interface, the first receive enable signal is stored from the ATM layer chip of the UTOPIA interface to store the data. A reception FIFO 12 outputting the reception data RxD according to the signal RxEN1 *; The first transmit enable signal (TxEN1 *) and the first receive enable signal (RxEN1 *) from the ATM layer chip of the UTOPIA interface and the second transmit enable signal (TxEN2 *) and the second receive from the physical layer chip of the FIFO interface. A counter 20 receiving an enable signal RxEN2 * and providing the number of bytes of data accumulated in the transmission FIFO 11 and the reception FIFO 12; Transmission empty flag Tx_EF * generated when the bytes are idle according to the number of bytes applied from the counter 20 in synchronization with the transmission clock TxCLK applied from the ATM layer chip of the UTOPIA interface. ) And the receive empty flag (Rx_EF *) generated when n is n to the physical layer chip of the FIFO interface, and the transmit pool signal (TxFULL *) generated when the byte is n-4 or more and when the byte is 4 or less And a control logic (30) for applying a receiving empty signal (RxEMPTY *) to the ATM layer chip of the UTOPIA interface. 2. The matching device of the UTOPIA interface and the FIFO interface in an ATM terminal.