KR102919819B1 - GaN-based E-mode transistor - Google Patents

Abstract

A GaN-based E-mode transistor capable of improving switching characteristics by reducing gate resistance is disclosed.
The disclosed GaN-based E-mode transistor is
A device comprising: a substrate; a buffer layer formed on the substrate; a channel layer formed on the buffer layer and including a two-dimensional electron channel; a source electrode and a drain electrode formed spaced apart from each other on the channel layer; a barrier layer formed between the source electrode and the drain electrode and inducing the two-dimensional electron channel to be formed at a boundary surface with the channel layer; a p-GaN layer formed on the barrier layer; a gate electrode formed on the p-GaN layer; a metal layer formed on the source electrode; and a gate feed line insulated from the metal layer and partially in contact with the gate electrode.

Description

GaN-based E-mode transistor

The present invention relates to a GaN-based E-mode transistor capable of improving switching characteristics by reducing gate resistance.

GaN (gallium nitride) is a material with a wide energy band gap and has advantages such as fast switching characteristics, high breakdown voltage, and high electron mobility. It is being actively studied for application in the power semiconductor field by overcoming the material limitations of Si, which has been commonly used in existing semiconductors.

In particular, the heterojunction structure of AlGaN and GaN causes spontaneous polarization and piezoelectric polarization due to differences in crystal structure and lattice constants, and forms a two-dimensional electron channel (2DEG) in which electrons accumulate between the AlGaN/GaN. The 2D electron channel has the advantage of having high electron density and electron mobility even without special doping.

FIG. 1a is a cross-sectional view illustrating a GaN-based D-mode transistor according to the prior art, and FIGS. 1b and 1c are cross-sectional views illustrating a GaN-based E-mode transistor according to the prior art.

Referring to FIG. 1a, a GaN-based D-mode transistor (10a) according to the prior art includes a substrate (1), a buffer layer (2), a channel layer (3), a barrier layer (4), a source electrode (S), a drain electrode (D), and a gate electrode (G). The channel layer (3) can be formed of GaN, and the barrier layer (4) can be formed of AlGaN, and a two-dimensional electron channel (2-DEG) is formed at the interface between the channel layer (3) and the barrier layer (4). Due to the two-dimensional electron channel (2-DEG), the field effect transistor of the AlGaN/GaN heterojunction structure has a normally-on characteristic. However, since the AlGaN/GaN heterojunction device has a normally-on characteristic due to the two-dimensional electron channel, it is important to manufacture it as a normally-off device.

As a representative method for implementing normally-off operation characteristics, there is a GaN-based E-mode transistor (10b) with a recessed MIS gate structure in which AlGaN under the gate is etched, as shown in FIG. 1b, or a GaN-based E-mode transistor (10c) with a p-GaN gate structure in which a p-GaN layer (5) is used under the gate metal, as shown in FIG. 1c.

FIG. 2 is a cross-sectional view illustrating a metal layer formed on a source electrode in a GaN-based E-mode transistor according to the prior art, FIG. 3 is a plan view of FIG. 2, and FIG. 4 is a plan view illustrating a state in which the source/drain electrodes are removed from FIG. 3.

Referring to FIG. 2, a GaN-based E-mode transistor (10c) of FIG. 1c is illustrated in the lower right square (symbol A) of FIG. 2. In this GaN-based E-mode transistor (10c), a portion of a first metal layer (M1) forms a source electrode (S) and a drain electrode (D), and a plurality of metal layers (M2, M3) are stacked on the source electrode (S) and the drain electrode (D) to form portions of the source electrode (S) and the drain electrode (D), and the uppermost metal layer (M4) forms a source pad (SP) and a drain pad (DP).

The source pad (SP) connects the source electrode (S) to an external circuit or source potential to form a current path. The drain pad (DP) connects the drain electrode (D) to an external circuit or load to allow current to flow from the source to the drain.

In the case of a pGaN/AlGaN/GaN HFET in a conventional GaN-based E-mode transistor as illustrated in FIG. 2, the current flows directly in the vertical direction from the source electrode (S) due to the stacking of M1, M2, M3, and M4, and as illustrated in FIG. 3, the gate electrode (G) (formed on the pGaN layer (5)) is formed over the entire active area (AA).

In Fig. 3, the cross-section viewed from L1 - L1' corresponds to the transistor (10c) in Fig. 2 except for the top metal layer (M4).

In a transistor (10c) of this structure, the gate electrode (G) is arranged thinly and long with a small width (W) as shown in Fig. 4, resulting in a large gate resistance. The large gate resistance is a major cause of switching loss and deteriorates switching characteristics. In other words, there is a problem that it is difficult to implement high-speed switching due to the large gate resistance.

Korean Patent Publication No. 10-2019-0112526

The present invention aims to provide a GaN-based E-mode transistor capable of improving switching characteristics by reducing gate resistance.

A GaN-based E-mode transistor according to an embodiment of the present invention,

A device comprising: a substrate; a buffer layer formed on the substrate; a channel layer formed on the buffer layer and including a two-dimensional electron channel; a source electrode and a drain electrode formed spaced apart from each other on the channel layer; a barrier layer formed between the source electrode and the drain electrode and inducing the two-dimensional electron channel to be formed at a boundary surface with the channel layer; a p-GaN layer formed on the barrier layer; a gate electrode formed on the p-GaN layer; a metal layer formed on the source electrode; and a gate feed line insulated from the metal layer and partially in contact with the gate electrode.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the metal layer includes first to third metal layers that are sequentially stacked, the gate feed line is formed in the third metal layer, and the gate electrode and the gate feed line can be connected through a bridge formed in the second metal layer.

In a GaN-based E-mode transistor according to an embodiment of the present invention, a plurality of bridges may be provided at preset intervals between the gate electrode and the gate feed line.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the gate feed line may be formed between a pair of third metal layers.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the gate feed line may be formed on an upper portion of the source electrode, and a pair of source electrodes may be formed on each of both sides of the gate feed line.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the second metal layer may be laminated so that the entire upper surface of the first metal layer is in direct contact with the lower surface of the second metal layer.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the gate feed line may be formed on each of both sides of the third metal layer.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the gap between the gate feed line and the drain electrode may be arranged to be smaller than the gap between the gate electrode and the drain electrode.

In a GaN-based E-mode transistor according to an embodiment of the present invention, the gate feed line includes a pair of first lines extending in a vertical direction and a plurality of second lines extending in a horizontal direction while connecting the pair of first lines, and the bridge may be formed to connect the upper surface of the gate electrode and the lower surface of the second line.

In a GaN-based E-mode transistor according to an embodiment of the present invention, a pair of gate electrodes arranged on both sides of the source electrode may be arranged on the inner side of a pair of gate feed lines.

Specific details of implementation examples according to various aspects of the present invention are included in the detailed description below.

According to the present invention, switching characteristics can be improved by reducing gate resistance.

FIG. 1a is a cross-sectional view illustrating a GaN-based D-mode transistor according to the prior art.
FIG. 1b and FIG. 1c are cross-sectional views illustrating a GaN-based E-mode transistor according to the prior art.
FIG. 2 is a cross-sectional view illustrating a metal layer formed on a source electrode in a GaN-based E-mode transistor according to the prior art.
Figure 3 is a plan view of Figure 2.
Fig. 4 is a plan view showing the state in which the source/drain electrodes in Fig. 3 are removed.
FIG. 5 is a cross-sectional view illustrating a GaN-based E-mode transistor according to one embodiment of the present invention.
Figure 6 is a plan view of Figure 5.
Fig. 7 is a plan view showing the state in which the source/drain electrodes in Fig. 6 are removed.
Figure 8 is a cross-sectional view taken along line M2-M2' of Figure 7.
FIG. 9 is a cross-sectional view illustrating a GaN-based E-mode transistor according to another embodiment of the present invention.
Figure 10 is a plan view of Figure 9.
Fig. 11 is a plan view showing the state in which the source/drain electrodes are removed from Fig. 10.
Fig. 12 is a cross-sectional view taken along line M3-M3' of Fig. 11.
FIGS. 13a to 13g are cross-sectional views illustrating a method for manufacturing a GaN-based E-mode transistor according to one embodiment of the present invention.
FIGS. 14a to 14c are cross-sectional views illustrating a method for manufacturing a GaN-based E-mode transistor according to another embodiment of the present invention.

The present invention is susceptible to various modifications and embodiments. Specific embodiments are illustrated and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

The terminology used in the present invention is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In the present invention, it should be understood that the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Please note that, where possible, identical components are represented by identical reference numerals throughout the drawings. Furthermore, detailed descriptions of well-known functions and configurations that may obscure the gist of the present invention will be omitted. For the same reason, some components in the attached drawings are exaggerated, omitted, or schematically depicted.

FIG. 5 is a cross-sectional view illustrating a GaN-based E-mode transistor according to one embodiment of the present invention.

Referring to FIG. 5, a GaN-based E-mode transistor (100_1, hereinafter referred to as “transistor”) according to one embodiment of the present invention includes a substrate (110), a buffer layer (120), a channel layer (130), a barrier layer (140), a p-GaN layer (150), a source electrode (S), a drain electrode (D), a gate electrode (G), metal layers (M1, M2, M3, M4), and a gate feed line (160). FIG. 5 shows two transistors (100_1) arranged mirror-symmetrically with respect to the source electrode (S).

The substrate (110) may be a growth substrate such as a sapphire substrate, an AlN substrate, a GaN substrate, a SiC substrate, or a Si substrate, and is not particularly limited as long as it is a substrate capable of growing a semiconductor.

The buffer layer (120) can serve as a nucleus layer that allows the channel layer (130) to grow, and can serve to alleviate the lattice constant mismatch between the substrate (110) and the channel layer (130). Preferably, the buffer layer (120) can be a GaN buffer layer made of GaN.

The channel layer (130) is formed on the buffer layer (120) and is formed of a first nitride semiconductor having a first energy band gap. The first nitride semiconductor is not particularly limited, and may be, for example, a binary nitride semiconductor such as undoped GaN or InN, a ternary nitride semiconductor such as AlGaN or InGaN, or a quaternary nitride semiconductor such as AlInGaN. In addition, the channel layer (130) may be doped with an n-type impurity (Donor) or a p-type impurity (Acceptor). Preferably, the channel layer (130) may be a GaN channel layer made of GaN.

A source electrode (S) and a drain electrode (D) are formed spaced apart from each other on the channel layer (130).

The barrier layer (140) is formed on the channel layer (130) between the source electrode (S) and the drain electrode (D), and induces the formation of a two-dimensional electron channel (2-DEG) at the interface with the channel layer (130). The barrier layer (140) is formed of a second nitride semiconductor having a second energy band gap. The second energy band gap means an energy band gap that is different from the first energy band gap. The second nitride semiconductor is not particularly limited, and may be, for example, a binary nitride semiconductor such as undoped GaN or InN, a ternary nitride semiconductor such as AlGaN or InGaN, or a quaternary nitride semiconductor such as AlInGaN. In addition, the barrier layer (140) may be doped with an n-type or p-type impurity. In addition, the second nitride semiconductor may be a material having a larger energy band gap than the first nitride semiconductor forming the channel layer (130). Preferably, the barrier layer (140) may be an AlGaN barrier layer made of AlGaN. A two-dimensional electron channel is formed at the interface between the channel layer (130) and the barrier layer (140).

And, a p-GaN layer (150) and a gate electrode (G) are formed on the barrier layer (140).

A portion of the first metal layer (M1) forms a source electrode (S) and a drain electrode (D), and a plurality of metal layers (M2, M3) are stacked on the source electrode (S) and the drain electrode (D) to form a portion of the source electrode (S) and the drain electrode (D), and the uppermost metal layer (M4) forms a source pad (SP) and a drain pad (DP). In Fig. 5, the plurality of metal layers (M2, M3) exemplify two layers, but the number of metal layers is not limited thereto. The number of metal layers can be increased depending on the required voltage or current size.

The first metal layer (M1) and the multiple metal layers (M2, M3) stacked thereon constitute a source electrode (S) as a whole. The first metal layer (M1) may be formed in the form of a field plate to alleviate the concentration of an electric field between the gate electrode (G) and the drain electrode (D) when a high voltage is applied.

A second metal layer (M2) is laminated on the first metal layer (M1). Here, the second metal layer (M2) may be laminated so that the entire upper surface of the first metal layer (M1) is in direct contact with the lower surface of the second metal layer (M2). In other words, a passivation layer may not be interposed between the first metal layer (M1) and the second metal layer (M2). Accordingly, the first metal layer (M1) and the second metal layer (M2) come into contact over a large area, thereby increasing the electron movement area and promoting heat diffusion.

A third metal layer (M3) is laminated on the second metal layer (M2). The third metal layers (M3) may be provided as a pair separated by a passivation layer, and one pair of the third metal layers (M3) is in contact with the second metal layer (M2).

A gate feed line (160) is formed between a pair of third metal layers (M3). The gate feed line (160) is formed to be insulated from the third metal layer (M3). The gate feed line (160) and the second metal layer (M2) and the third metal layer (M3) are insulated by a passivation layer. When viewed from above, the gate feed line (160) is formed on an upper portion of a source electrode (S), and a pair of source electrodes (S) are formed on each of both sides of the gate feed line (160). The gate feed line (160) is positioned on the second passivation layer (IMD2) and is surrounded by a third passivation layer (IMD3).

Meanwhile, when forming a gate feed line in the second metal layer (M2), the thickness of the first passivation layer (IMD1) is thinner than that of the second passivation layer (IMD2), which causes a phenomenon in which the capacitance increases. However, when forming a gate feed line (160) in the third metal layer (M3), since it is formed on the relatively thicker second passivation layer (IMD2), there is an advantage in that a lower capacitance is formed in the former case (forming a gate feed line in the second metal layer (M2)).

The gate feed line (160) can transmit an input signal to the gate electrode (G) to switch the device. The gate feed line (160) can be made of a highly conductive metal (e.g., Al, Cu, Au, etc.) to maintain low resistance.

The gate electrode (G) can be connected to the gate feed line (160) via a bridge (B). This will be described with reference to FIGS. 6 and 7.

Fig. 6 is a plan view of Fig. 5, Fig. 7 is a plan view showing the state in which the source/drain electrodes are removed from Fig. 6, and Fig. 8 is a cross-sectional view taken along M2-M2' of Fig. 7. The cross-section taken along L2-L2' in Fig. 6 corresponds to the transistor of Fig. 5.

In FIGS. 6 and 7, the source pad (SP), the drain pad (DP), and the gate pad (GP) are formed on the fourth metal layer (M4). In addition, the source electrode (S), the drain electrode (D), and the gate feed line (160) are shown to be formed on the third metal layer (M3), and the bridge (B) is shown to be formed on the second metal layer (M2). The gate feed line (160) is arranged on the upper portion of the gate electrode (G), and the gate feed line (160) is in contact with the gate electrode (G) through the bridge (B).

Referring to FIGS. 5 to 8, the gate electrodes (G1, G2) arranged on both sides of the source electrode (S) are arranged on both sides of one gate feed line (160) when viewed from above, and each gate electrode (G1, G2) partially contacts the gate feed line (160) through a bridge (B). The bridge (B) is a member that connects the gate electrode (G: G1, G2) and the gate feed line (160), and may be provided in multiple numbers at a preset interval between the gate electrode and the gate feed line.

According to the GaN-based E-mode transistor according to one embodiment of the present invention as described above, the gate electrode (G) is electrically connected to the gate pad through the bridge (B) and the gate feed line (160), and the bridge (B) is connected to the gate feed line (160) by making contact at regular intervals, so that the gate electrode (G) is electrically connected to the gate pad with a smaller gate resistance, thereby having the effect of implementing high-speed switching. In addition, the first metal layer (M1) and the second metal layer (M2) are in contact with a large area, thereby expanding the movement area of electrons, and the electrons are divided in both directions in the second metal layer (M2) and move to the third metal layer (M3), thereby promoting heat diffusion, thereby having the effect of improving the heat dissipation effect.

Next, a GaN-based E-mode transistor according to another embodiment of the present invention will be described with reference to FIGS. 9 to 12.

FIG. 9 is a cross-sectional view illustrating a GaN-based E-mode transistor according to another embodiment of the present invention.

Referring to FIG. 9, a GaN-based E-mode transistor (100_2, hereinafter referred to as “transistor”) according to another embodiment of the present invention includes a substrate (110), a buffer layer (120), a channel layer (130), a barrier layer (140), a p-GaN layer (150), a source electrode (S), a drain electrode (D), a gate electrode (G), metal layers (M1, M2, M3, M4), and a gate feed line (160). FIG. 9 shows two transistors (100_2) arranged mirror-symmetrically with respect to the source electrode (S).

The substrate (110), buffer layer (120), channel layer (130), barrier layer (140), p-GaN layer (150), source electrode (S), drain electrode (D), gate electrode (G), first metal layer (M1), and second metal layer (M2) are substantially the same as those in the above-described embodiment, so a repeated description thereof is omitted.

In the present embodiment, a third metal layer (M3) is laminated on a second metal layer (M2), and gate feed lines (160) are formed on both sides of the third metal layer (M3). The gate feed lines (160) and the second metal layer (M2) and the third metal layer (M3) are insulated by a passivation layer. When viewed from above, the gate feed lines (160) are formed between the gate electrode (G) and the drain electrode (D).

The gate electrode (G) can be connected to the gate feed line (160) via a bridge (B). This will be described with reference to FIGS. 10 to 12.

Fig. 10 is a plan view of Fig. 9, Fig. 11 is a plan view showing the state in which the source/drain electrodes are removed from Fig. 10, and Fig. 12 is a cross-sectional view taken along M3-M3' of Fig. 11. The cross-section taken along L3-L3' of Fig. 10 corresponds to the transistor of Fig. 9.

In FIGS. 10 to 12, the source pad (SP), the drain pad (DP), and the gate pad (GP) are formed on the fourth metal layer (M4). In addition, the source electrode (S), the drain electrode (D), and the gate feed line (160) are shown to be formed on the third metal layer (M3), and the bridge (B) is formed on the second metal layer (M2).

A gate feed line (160) is arranged on top of the gate electrode (G), and the gate feed line (160) is in contact with the gate electrode (G) through a bridge (B). The gate feed line (160) is arranged outside the source electrode in the third metal layer (M3), so that the gate feed line (160) can be utilized as a field plate depending on the design.

In this embodiment, the gate feed line (160) includes a pair of first lines (161) extending vertically and a plurality of second lines (162) extending horizontally while connecting the pair of first lines (161). In addition, a bridge (B) is formed to connect the upper surface of the gate electrode (G) and the lower surface of the second line (162). That is, in FIG. 11, the lower surface of the second line (162) is formed to be connected to the bridge (B).

Referring to FIGS. 9 to 12, gate electrodes (G1, G2) arranged on both sides of a source electrode (S) are arranged on the inner side of a pair of gate feed lines (160), and each gate electrode (G1, G2) partially contacts a second line (162) of the gate feed line (160) through a bridge (B). The bridge (B) is a member that connects the gate electrodes (G1, G2) and the gate feed line (160), and may be provided in multiple numbers at preset intervals in the vertical direction on the upper surface of the gate electrodes (G1, G2).

According to the GaN-based E-mode transistor according to another embodiment of the present invention as described above, the gate electrode (G) is electrically connected to the gate pad through the bridge (B) and the gate feed line (160), and the bridge (B) is connected to the gate feed line (160) by contact at regular intervals, so that the gate electrode (G) is electrically connected to the gate pad with a smaller gate resistance, thereby enabling high-speed switching. In addition, since the gate feed line (160) is arranged closer to the drain electrode (D) than the gate electrode (G), the gate feed line (160) has the effect of simultaneously implementing a field plate.

FIGS. 13a to 13g are cross-sectional views illustrating a method for manufacturing a GaN-based E-mode transistor according to one embodiment of the present invention.

First, as illustrated in Fig. 13a, a buffer layer (120)/channel layer (130)/barrier layer (140)/P-GaN layer (150) are sequentially stacked on a substrate (110), and then device cleaning is performed. Device cleaning can be performed using Acetone, IPA, SPM, BOE (7:1), etc.

Next, as illustrated in FIG. 13b, the P-GaN layer (150) is selectively etched using an etching mask to form a P-GaN layer pattern (150), and a metal is deposited on the P-GaN layer pattern (150) to form a gate electrode (G). Strictly speaking, the P-GaN layer and the P-GaN layer pattern are distinct, but for convenience of explanation, the P-GaN layer pattern is referred to as the P-GaN layer (150).

Next, as illustrated in FIG. 13c, after forming a first passivation layer (P1) on the front surface, the area where the source electrode (S) and the drain electrode (D) are to be formed is etched to form a first recess (R1), an ohmic metal material is deposited on the front surface, and then etched to form a first metal layer (M1). The ohmic metal material may be a metal including Ti/Al, for example. At this time, the first metal layer (M1) that becomes the source electrode (S) is etched to have a T shape so that a field plate is provided.

Next, as illustrated in FIG. 13d, after forming a second passivation layer (P2) on the front surface, an etching mask is used to etch the second passivation layer (P2) in the area where the second metal layer (M2) is to be formed to form a second recess (R2), an ohmic metal material is deposited on the front surface, and then etched to form the second metal layer (M2). The width (W2) of the second metal layer (M2) is formed to be larger than the width (W1) of the first metal layer (M1).

Next, as illustrated in FIG. 13e, after forming a third passivation layer (P3) on the front surface, an etching mask is used to etch the third passivation layer (P3) in the area where the third metal layer (M3) is to be formed, thereby forming a third recess (R3), and an ohmic metal material is deposited on the front surface. Then, selective etching is performed using the etching mask to form the third metal layer (M3) and the gate feed line (160). At this time, the gate feed line (160) is formed between a pair of third metal layers (M3). (See FIGS. 5 to 8)

Next, as illustrated in FIG. 13f, after forming a fourth passivation layer (P4) on the front surface, an etching mask is used to etch the fourth passivation layer (P4) in the area where the fourth metal layer (M4) is to be formed to form a fourth recess (R4), and an ohmic metal material is deposited on the front surface, followed by etching to form the fourth metal layer (M4).

Next, as shown in FIG. 13g, a final passivation layer (P5) is formed on the front surface.

The first passivation layer (P1) may be an ILD layer, and the second to fifth passivation layers (P2 to P5) may be IMD layers. ILD is an insulating material layer used for insulation between an active layer and a metal layer of a semiconductor device or between metal layers, and IMD is an insulating material layer used for electrical insulation between metal wires.

FIGS. 14a to 14c are cross-sectional views illustrating a method for manufacturing a GaN-based E-mode transistor according to another embodiment of the present invention.

The process for forming the second metal layer (M2) is the same as the process of FIGS. 13a to 13d described above, so a repeated description is omitted.

As illustrated in FIG. 14a, after forming a third passivation layer (P3) on the entire surface of the second metal layer (M2), the third passivation layer (P3) in the area where the third metal layer (M3) is to be formed is etched using an etching mask to form a third recess (R3), and an ohmic metal material is deposited on the entire surface. Then, the third metal layer (M3) and the gate feed line (160) are formed by selective etching using the etching mask. At this time, the gate feed lines (160) are formed as a pair arranged on both sides of the third metal layer (M3), and a pair of gate electrodes (G1, G2) are formed so as to be arranged on the inner side of the pair of gate feed lines (160). (See FIGS. 9 to 12)

Next, as shown in FIG. 14b, after forming a fourth passivation layer (P4) on the front surface, an etching mask is used to etch the fourth passivation layer (P4) in the area where the fourth metal layer (M4) is to be formed to form a fourth recess (R4), and an ohmic metal material is deposited on the front surface, followed by etching to form the fourth metal layer (M4).

Next, as shown in Fig. 14c, a final passivation layer (P5) is formed on the front surface.

Above, the embodiments of the present invention have been described, but those of ordinary skill in the art will be able to modify and change the present invention in various ways by adding, changing, deleting or adding components, etc., within the scope that does not depart from the spirit of the present invention described in the claims, and this will also be considered to be included within the scope of the rights of the present invention.

100_1, 100_2: GaN-based E-mode transistors
110: substrate 120: buffer layer
130: Channel layer 140: Barrier layer
150: p-GaN layer 160: gate feed line
S: source electrode D: drain electrode
G: Gate electrode
M1 ~ M4: Metal layer
P1 ~ P5: Passivation layer

Claims (10)

substrate;
A buffer layer formed on the substrate;
A channel layer formed on the buffer layer and including a two-dimensional electron channel;
A source electrode and a drain electrode formed spaced apart from each other on the channel layer;
A barrier layer formed between the source electrode and the drain electrode and inducing the formation of the two-dimensional electron channel at the interface with the channel layer;
A p-GaN layer formed on the above barrier layer;
A gate electrode formed on the above p-GaN layer;
A metal layer formed on the source electrode;
A gate feed line insulated from the metal layer and partially in contact with the gate electrode;
Includes,
The above metal layer includes first to third metal layers that are sequentially laminated,
The above gate feed lines are formed on both sides of the third metal layer,
The above gate electrode and the above gate feed line are connected through a bridge formed in the second metal layer,
The above gate feed line includes a pair of first lines extending in a vertical direction and a plurality of second lines extending in a horizontal direction, connecting the pair of first lines,
The above bridge is formed to connect the upper surface of the gate electrode and the lower surface of the second line.
GaN-based E-mode transistor.
delete In the first paragraph,
A GaN-based E-mode transistor, wherein the above bridge is provided in multiple numbers at a preset interval between the gate electrode and the gate feed line.
delete delete In the first paragraph,
A GaN-based E-mode transistor, wherein the second metal layer is laminated so that the entire upper surface of the first metal layer is in direct contact with the lower surface of the second metal layer.
delete In the first paragraph,
A GaN-based E-mode transistor, wherein the gap between the gate feed line and the drain electrode is arranged to be smaller than the gap between the gate electrode and the drain electrode.
delete In the first paragraph,
A GaN-based E-mode transistor, wherein a pair of gate electrodes arranged on both sides of the source electrode are arranged on the inner side of a pair of gate feed lines.