KR102903905B1 - Manufacturing Method For Semiconductor Package Having A Stacked Structure Of Multiple Chips Having A TSV Structure, And Semiconductor Package Manufactured Thereby - Google Patents
Manufacturing Method For Semiconductor Package Having A Stacked Structure Of Multiple Chips Having A TSV Structure, And Semiconductor Package Manufactured TherebyInfo
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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Abstract
티에스브이구조를 가지는 다수개의 칩 적층구조를 포함하는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지가 개시된다. 본 발명의 실시예에 따른 티에스브이 반도체 패키지 제조방법은, 인쇄회로기판(PCB)의 상부면에 제1 티에스브이 칩(TSV Chip)을 접합 후 기설정된 두께로 씨닝(thinning) 처리하는 하부칩 실장단계; 상기 하부칩 실장단계 이후 노출된 티에스브이 구리(TSV Cu)에 무전해 주석(Sn) 도금 처리하는 내식층 도금단계; 상기 내식층 도금단계 이후 제1 티에스브이 칩(TSV Chip)의 상부면에 제2 티에스브이 칩(TSV Chip)을 안착하여 티에스브이 주석도금(TSV Sn도금)과 제2 티에스브이 칩(TSV Chip)의 범프(Bump)를 접합하는 상부칩 실장단계; 및 상기 상부칩 실장단계와 동시에 실시되고, 제1 티에스브이 칩과 제2 티에스브이 칩 접합 부분에 접착소재를 적용하여 물리적 접합력과 내식성 특성을 확보하는 접착층 적용단계;를 포함하는 것을 구성의 요지로 한다.
본 발명에 따르면, 반도체 패키지의 크기를 축소시킬 수 있고, 더 많은 수의 칩을 밀집된 상태로 적층하여 구성할 수 있는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지를 제공할 수 있다.A method for manufacturing a TSV semiconductor package including a plurality of chip stacking structures having a TSV structure and a TSV semiconductor package manufactured thereby are disclosed. The TSV semiconductor package manufacturing method according to an embodiment of the present invention comprises: a lower chip mounting step of bonding a first TSV chip (TSV Chip) to an upper surface of a printed circuit board (PCB) and then thinning it to a preset thickness; a corrosion-resistant layer plating step of electrolessly plating TSV copper (TSV Cu) exposed after the lower chip mounting step with tin (Sn); an upper chip mounting step of mounting a second TSV chip on an upper surface of the first TSV chip after the corrosion-resistant layer plating step and bonding a TSV tin plating (TSV Sn plating) and a bump of the second TSV chip; The gist of the configuration includes an adhesive layer application step that is performed simultaneously with the upper chip mounting step and secures physical bonding strength and corrosion resistance characteristics by applying an adhesive material to the joint portion of the first TSV chip and the second TSV chip.
According to the present invention, a method for manufacturing a TSV semiconductor package capable of reducing the size of a semiconductor package and stacking a greater number of chips in a dense state, and a TSV semiconductor package manufactured thereby can be provided.
Description
본 발명은 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지에 관한 것으로서, 더욱 상세하게는 인쇄회로기판에 1차 칩을 실장하고 그 위에 제2, 3차 순으로 N차 칩을 순차적으로 적층하여 티에스브이(TSV)구조를 가지는 다수개의 칩 적층구조를 포함하는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지에 관한 것이다.The present invention relates to a method for manufacturing a TSV semiconductor package and a TSV semiconductor package manufactured thereby, and more particularly, to a method for manufacturing a TSV semiconductor package including a plurality of chip stacking structures having a TSV (Through-Silicon Via) structure by mounting a first chip on a printed circuit board and sequentially stacking Nth chips thereon in a second and third order, and a TSV semiconductor package manufactured thereby.
전자산업의 발전에 따라, 경량화, 소형화, 고속화 및 고성능화된 전자 제품을 저렴한 가격으로 제공할 수 있다.With the advancement of the electronics industry, lightweight, miniaturized, high-speed, and high-performance electronic products can be provided at low prices.
이러한 전자 산업의 추세에 따라, 복수의 반도체 칩들 또는 반도체 패키지들이 하나의 패키지로 구현된 반도체 장치 기술이 부각되고 있다. 이러한 반도체 장치들의 미세화 및 고집적화를 위한 다양한 연구가 요구된다.In line with these trends in the electronics industry, semiconductor device technology, which integrates multiple semiconductor chips or semiconductor packages into a single package, is gaining prominence. Diverse research is required to further miniaturize and integrate these semiconductor devices.
종래 기술에 따른 다양한 연구 결과로서 도 1에 도시된 결과물을 확인할 수 있다.The results shown in Figure 1 can be confirmed as a result of various researches according to prior art.
도 1의 (a)에 따른 반도체 패키지 구조는, Chip solder bump & 이면 Pad 형성 공정, Wafer saw 공정, chip attach 공정, Re-Flow 공정, Under-fill 공정, Cure 공정, Mold & Solder ball attach 공정을 순차적으로 수행함으로써 얻을 수 있는 결과물이다.The semiconductor package structure according to Fig. 1 (a) is a result obtained by sequentially performing the Chip solder bump & backside pad formation process, Wafer saw process, chip attach process, Re-Flow process, Under-fill process, Cure process, and Mold & Solder ball attach process.
도 1의 (a)에 따른 반도체 패키지 구조의 문제점은, 공정 Cost가 증가하는 문제점, Chip attach & Re-Flow 공정에 있어 Warpage로 Chip두께가 증가하는 문제점, Solder bump 접합 공정에 있어 접합 두께 증가 문제점, 방열 저하 문제점 및 Pitch 축소 제한 문제점을 포함하고 있다.The problems of the semiconductor package structure according to (a) of Fig. 1 include problems of increased process cost, problems of increased chip thickness due to warpage in the chip attach & re-flow process, problems of increased bonding thickness in the solder bump bonding process, problems of reduced heat dissipation, and problems of limited pitch reduction.
도 1의 (b)에 따른 반도체 패키지 구조는, Chip solder bump & Pad 형성 공정, Chip Top면 NCF 부착 공정, Wafer saw 공정, Chip attach & 가열/ 가압 접합 공정, Mold & Solder ball attach 공정을 순차적으로 수행함으로써 얻을 수 있는 결과물이다.The semiconductor package structure according to Fig. 1 (b) is a result obtained by sequentially performing the Chip solder bump & Pad formation process, Chip Top surface NCF attachment process, Wafer saw process, Chip attach & heating/pressure bonding process, and Mold & Solder ball attach process.
도 1의 (b)에 따른 반도체 패키지 구조의 문제점은, Chip 이면 Bonding pad 형성 공정에 있어 공정 Cost가 증가하는 문제점, Chip attach & 가열 접합 공정에 있어 Warpage로 chip 두께 증가 문제점, Solder bump 밖으로 도출하는 공정에 있어 Pitch 축소 제한의 문제점, Solder bump 접합 공정에 있어 접합 두께 증가 문제점, 방열 저하 문제점 및 pitch 축소 제한 문제점을 포함하고 있다.The problems of the semiconductor package structure according to (b) of Fig. 1 include the problem of increased process cost in the process of forming a bonding pad on the back of the chip, the problem of increased chip thickness due to warpage in the process of attaching and heating the chip, the problem of limited pitch reduction in the process of drawing out the solder bump, the problem of increased bonding thickness in the process of bonding the solder bump, the problem of reduced heat dissipation, and the problem of limited pitch reduction.
따라서, 상기 언급한 종래 기술에 따른 문제점을 해결할 수 있는 기술이 필요한 실정이다.Therefore, there is a need for a technology that can solve the problems of the above-mentioned conventional technology.
본 발명의 목적은, 통상적으로 반도체 패키지의 인쇄회로기판에 형성되는 배선은 규격화되어 있거나 물질적 특성, 또는 제조 공정을 이유로 하여 조밀화하기 어려운 한계가 있으므로, 상기 인쇄회로기판에 물리적으로 접촉하는 연결 부재들의 크기를 감소하기 어려우며, 결과적으로 반도체 칩들의 크기를 축소하거나 반도체 칩의 연결 부재들의 밀도를 축소하기 어려운 종래기술에 따른 문제점을 해결할 수 있고, 반도체 패키지의 크기를 축소시킬 수 있는 구성을 포함하는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지를 제공하는 것이다.The purpose of the present invention is to provide a method for manufacturing a TSV semiconductor package including a configuration capable of reducing the size of a semiconductor package, and a TSV semiconductor package manufactured thereby, which can solve the problem according to the prior art in that the wiring formed on the printed circuit board of a semiconductor package is standardized or has limitations in densification due to material characteristics or manufacturing processes, and thus it is difficult to reduce the size of connecting members that physically contact the printed circuit board, and consequently it is difficult to reduce the size of semiconductor chips or reduce the density of connecting members of the semiconductor chips.
이러한 목적을 달성하기 위한 본 발명의 일 측면에 따른 티에스브이 반도체 패키지 제조방법은, 인쇄회로기판(PCB)의 상부면에 제1 티에스브이 칩(TSV Chip)을 접합 후 기설정된 두께로 씨닝(thinning) 처리하는 하부칩 실장단계; 상기 하부칩 실장단계 이후 노출된 티에스브이 구리(TSV Cu)에 무전해 주석(Sn) 도금 처리하는 내식층 도금단계; 상기 내식층 도금단계 이후 제1 티에스브이 칩(TSV Chip)의 상부면에 제2 티에스브이 칩(TSV Chip)을 안착하여 티에스브이 주석도금(TSV Sn도금)과 제2 티에스브이 칩(TSV Chip)의 범프(Bump)를 접합하는 상부칩 실장단계; 및 상기 상부칩 실장단계와 동시에 실시되고, 제1 티에스브이 칩과 제2 티에스브이 칩 접합 부분에 접착소재를 적용하여 물리적 접합력과 내식성 특성을 확보하는 접착층 적용단계;을 포함하는 구성일 수 있다.According to one aspect of the present invention for achieving the above object, a method for manufacturing a TSV semiconductor package comprises: a lower chip mounting step of bonding a first TSV chip (TSV Chip) to an upper surface of a printed circuit board (PCB) and then thinning it to a preset thickness; a corrosion-resistant layer plating step of electroless plating tin (Sn) on exposed TSV copper (TSV Cu) after the lower chip mounting step; an upper chip mounting step of mounting a second TSV chip on an upper surface of the first TSV chip after the corrosion-resistant layer plating step and bonding a TSV tin plating (TSV Sn plating) and a bump of the second TSV chip; And it may be a configuration including an adhesive layer application step that is performed simultaneously with the upper chip mounting step and secures physical bonding strength and corrosion resistance characteristics by applying an adhesive material to the joint portion of the first TSV chip and the second TSV chip.
본 발명의 일 실시예에 있어서, 상기 하부칩 실장단계는, 상기 제1 티에스브이 칩을 접합한 후, 제1 티에스브이 칩과 인쇄회로기판 사이의 공간을 에폭시 기반의 소재로 채워 접합부에 인가되는 소성 응력을 흡수하여 접합부의 신뢰성을 확보하는 언더필단계;를 포함하는 구성일 수 있다.In one embodiment of the present invention, the lower chip mounting step may include an underfill step of filling the space between the first TSV chip and the printed circuit board with an epoxy-based material after bonding the first TSV chip to absorb plastic stress applied to the bonding portion and secure reliability of the bonding portion.
본 발명의 일 실시예에 있어서, 상기 상부칩 실장단계에서, 상기 티에스브이 주석도금의 두께는 0.1 내지 2.0 마이크로미터 범위 내의 길이일 수 있다.In one embodiment of the present invention, in the upper chip mounting step, the thickness of the TSV tin plating may be a length within a range of 0.1 to 2.0 micrometers.
본 발명의 일 실시예에 있어서, 상기 접착층 적용단계에서, 상기 접착소재는 내화학적 특성을 가지는 SiO2 접착소재 또는 Organic 접착소재일 수 있다.In one embodiment of the present invention, in the adhesive layer application step, the adhesive material may be a SiO2 adhesive material or an organic adhesive material having chemically resistant properties.
본 발명은 또한 상기 티에스브이 반도체 패키지 제조방법에 의해 제조되는 티에스브이 반도체 패키지를 제공할 수 있는 바, 본 발명의 일 측면에 따른 티에스브이 반도체 패키지는, 인쇄회로기판 형성부; 상기 인쇄회로기판 상부면에 하부칩 실장단계를 통해 접합된 하부칩 실장부; 상기 인쇄회로기판과 하부칩 실장부 사이에 충진된 구조의 언더필 형성부; 상기 하부칩 실장부의 상부면에 상부칩 실장단계를 통해 접합된 상부칩 실장부; 및 상기 인쇄회로기판의 상부면에 형성되고, 하부칩 실장부, 언더필 형성부 및 상부칩 실장부를 감싸는 구조로 형성되고, 에폭시 몰드 컴파운드(EMC, Epoxy mold compound) 소재를 이용하여 열, 수분, 충격으로부터 보호할 수 있는 구조로 몰딩 처리된 인캡슐레이션부;를 포함하는 구성일 수 있다.The present invention can also provide a TSV semiconductor package manufactured by the above TSV semiconductor package manufacturing method, and the TSV semiconductor package according to one aspect of the present invention can be configured to include a printed circuit board forming portion; a lower chip mounting portion joined to an upper surface of the printed circuit board through a lower chip mounting step; an underfill forming portion having a structure filled between the printed circuit board and the lower chip mounting portion; an upper chip mounting portion joined to an upper surface of the lower chip mounting portion through an upper chip mounting step; and an encapsulation portion formed on an upper surface of the printed circuit board and having a structure that surrounds the lower chip mounting portion, the underfill forming portion, and the upper chip mounting portion, and is molded using an epoxy mold compound (EMC) material to have a structure that can protect against heat, moisture, and shock.
이상에서 설명한 바와 같이, 본 발명의 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지에 따르면, 특정 과정을 수행하는 하부칩 실장단계, 내식층 도금단계, 상부칩 실장단계 및 접착층 적용단계를 구비함으로써, 반도체 칩들의 크기를 축소하거나 반도체 칩의 연결 부재들의 밀도를 축소하기 어려운 종래기술에 따른 문제점을 해결할 수 있고, 반도체 패키지의 크기를 축소시킬 수 있고, 더 많은 수의 칩을 밀집된 상태로 적층하여 구성할 수 있으며, 이와 동시에 박판형 구조로 반도체 패키지를 제작할 수 있는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지를 제공할 수 있다.As described above, according to the method for manufacturing a TSV semiconductor package of the present invention and the TSV semiconductor package manufactured thereby, by having a lower chip mounting step, a corrosion-resistant layer plating step, an upper chip mounting step, and an adhesive layer application step that perform specific processes, it is possible to solve the problem according to the prior art that it is difficult to reduce the size of semiconductor chips or reduce the density of connecting members of semiconductor chips, and it is possible to reduce the size of the semiconductor package, configure a larger number of chips by stacking them in a dense state, and at the same time, it is possible to provide a TSV semiconductor package manufacturing method and a TSV semiconductor package manufactured thereby that can manufacture a semiconductor package in a thin plate structure.
도 1은 종래 기술에 다른 솔더 범프 및 언더 필 방식에 의해 제조된 반도체 패키지 및 솔더 범프 및 NCF 접합 방식에 의해 제조된 반도체 패키지의 부분확대도이다.
도 2는 본 발명의 일 실시예에 따른 티에스브이 반도체 패키지를 나타내는 종단면도이다.
도 3은 본 발명의 일 실시예에 따른 티에스브이 반도체 패키지의 티에스브이 칩 적층구조를 나타내는 종단면도이다.
도 4는 본 발명의 일 실시예에 다른 티에스브이 반도체 패키지 제조방법을 나타내는 흐름도이다.
도 5는 도 4에 도시된 티에스브이 반도체 패키지 제조방법의 하부칩 실장단계 및 내식층 도금단계에 의해 제조된 티에스브이 반도체 패키지의 모습을 나타내는 종단면도이다.
도 6은 본 발명의 일 실시예에 따른 하부칩 실장단계에서, 인쇄회로기판과 제1 티에스브이 칩을 나타내는 종단면도이다.
도 7은 본 발명의 일 실시예에 따른 하부칩 실장단계에서, 인쇄회로기판의 상부면에 제1 티에스브이 칩을 접합한 상태를 나타내는 종단면도이다.
도 8은 본 발명의 일 실시예에 따른 하부칩 실장단계에서, 인쇄회로기판과 제1 티에스브이 칩 사이의 공간에 언더필한 상태를 나타내는 종단면도이다.
도 9는 본 발명의 일 실시예에 따른 하부칩 실장단계에서, 인쇄회로기판과 제1 티에스브이 칩이 접합된 상태에서 제1 티에스브이 칩의 상부면을 기설정된 두께로 씨닝 처리한 후의 상태를 나타내는 종단면도이다.
도 10은 도 4에 도시된 티에스브이 반도체 패키지 제조방법의 상부칩 실장단계 및 접착층 적용단계에 의해 제조된 티에스브이 반도체 패키지의 모습을 나타내는 종단면도이다.
도 11은 본 발명의 일 실시예에 따른 내식층 도금단계 수행 후의 인쇄회로기판과 제1 티에스브이 칩의 상태를 나타내는 종단면도이다.
도 12는 본 발명의 일 실시예에 따른 상부칩 실장단계 및 접착층 적용단계에서 제2 티에스브이 칩의 접합 전 상태를 나타내는 종단면도이다.
도 13은 본 발명의 일 실시예에 따른 상부칩 실장단계 및 접착층 적용단계에서 제2 티에스브이 칩의 접합 후 상태를 나타내는 종단면도이다.
도 14는 본 발명의 일 실시예에 따른 내식층 도금단계, 상부칩 실장단계 및 접착층 적용단계를 통해 다수의 티에스브이 칩을 적층 및 접합한 상태를 나타내는 종단면도이다.
도 15는 본 발명의 일 실시예에 따른 티에스브이 칩의 다양한 범프 형상을 나타내는 종단면도이다.
도 16은 본 발명의 일 실시예에 따른 하부칩 실장부 및 상부칩 실장부의 도금처리 상태를 나타내는 종단면도이다.
도 17은 본 발명의 또 다른 실시예에 따른 하부칩 실장부 및 상부칩 실장부의 도금처리 상태를 나타내는 종단면도이다.Figure 1 is a partial enlarged view of a semiconductor package manufactured by a solder bump and underfill method different from the prior art and a semiconductor package manufactured by a solder bump and NCF bonding method.
FIG. 2 is a cross-sectional view showing a TSV semiconductor package according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a TSV chip stacking structure of a TSV semiconductor package according to one embodiment of the present invention.
FIG. 4 is a flowchart showing a method for manufacturing a TSV semiconductor package according to another embodiment of the present invention.
FIG. 5 is a cross-sectional view showing the appearance of a TSV semiconductor package manufactured by the lower chip mounting step and the corrosion-resistant layer plating step of the TSV semiconductor package manufacturing method illustrated in FIG. 4.
FIG. 6 is a cross-sectional view showing a printed circuit board and a first TSV chip in a lower chip mounting step according to one embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a state in which a first TSV chip is bonded to an upper surface of a printed circuit board in a lower chip mounting step according to one embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a state in which the space between the printed circuit board and the first TSV chip is underfilled in the lower chip mounting step according to one embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a state after thinning the upper surface of the first TSV chip to a preset thickness while the printed circuit board and the first TSV chip are bonded in a lower chip mounting step according to one embodiment of the present invention.
FIG. 10 is a cross-sectional view showing the appearance of a TSV semiconductor package manufactured by the upper chip mounting step and adhesive layer application step of the TSV semiconductor package manufacturing method illustrated in FIG. 4.
Fig. 11 is a cross-sectional view showing the state of a printed circuit board and a first TSV chip after performing a corrosion-resistant layer plating step according to one embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a state before bonding of a second TSV chip in an upper chip mounting step and an adhesive layer application step according to one embodiment of the present invention.
FIG. 13 is a cross-sectional view showing the state after bonding of the second TSV chip in the upper chip mounting step and adhesive layer application step according to one embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a state in which a plurality of TSV chips are stacked and bonded through a corrosion-resistant layer plating step, an upper chip mounting step, and an adhesive layer application step according to one embodiment of the present invention.
FIG. 15 is a cross-sectional view showing various bump shapes of a TSV chip according to one embodiment of the present invention.
Fig. 16 is a cross-sectional view showing the plating treatment state of the lower chip mounting portion and the upper chip mounting portion according to one embodiment of the present invention.
Fig. 17 is a longitudinal cross-sectional view showing the plating treatment state of the lower chip mounting portion and the upper chip mounting portion according to another embodiment of the present invention.
이하 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정하여 해석되어서는 아니되며, 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Prior to this, it should be noted that the terms and words used in this specification and claims should not be construed as limited to their conventional or dictionary meanings, but rather should be interpreted in terms of meanings and concepts consistent with the technical spirit of the present invention.
본 명세서 전체에서, 어떤 부재가 다른 부재 "상에" 위치하고 있다고 할 때, 이는 어떤 부재가 다른 부재에 접해 있는 경우뿐 아니라 두 부재 사이에 또 다른 부재가 존재하는 경우도 포함한다. 본 명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함" 한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것을 의미한다.Throughout this specification, when it is said that an element is "on" another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. Throughout this specification, when it is said that a part "includes" a component, this does not mean that the other component is excluded, but rather that the other component may be included, unless otherwise stated.
도 2에는 본 발명의 일 실시예에 따른 티에스브이 반도체 패키지를 나타내는 종단면도가 도시되어 있고, 도 3에는 본 발명의 일 실시예에 따른 티에스브이 반도체 패키지의 티에스브이 칩 적층구조를 나타내는 종단면도가 도시되어 있으며, 도 4에는 본 발명의 일 실시예에 다른 티에스브이 반도체 패키지 제조방법을 나타내는 흐름도가 도시되어 있다.FIG. 2 is a cross-sectional view showing a TSV semiconductor package according to an embodiment of the present invention, FIG. 3 is a cross-sectional view showing a TSV chip stacking structure of a TSV semiconductor package according to an embodiment of the present invention, and FIG. 4 is a flowchart showing a method for manufacturing a TSV semiconductor package according to an embodiment of the present invention.
이들 도면을 참조하면, 본 실시예에 따른 티에스브이 반도체 패키지 제조방법(S100)은 특정 과정을 수행하는 하부칩 실장단계(S110), 내식층 도금단계(S120), 상부칩 실장단계(S130) 및 접착층 적용단계(S140)를 구비함으로써, 반도체 칩들의 크기를 축소하거나 반도체 칩의 연결 부재들의 밀도를 축소하기 어려운 종래기술에 따른 문제점을 해결할 수 있고, 반도체 패키지의 크기를 축소시킬 수 있고, 더 많은 수의 칩을 밀집된 상태로 적층하여 구성할 수 있으며, 이와 동시에 박판형 구조로 반도체 패키지를 제작할 수 있는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지를 제공할 수 있다.Referring to these drawings, the TSV semiconductor package manufacturing method (S100) according to the present embodiment comprises a lower chip mounting step (S110), a corrosion-resistant layer plating step (S120), an upper chip mounting step (S130), and an adhesive layer application step (S140) that perform specific processes, thereby solving problems according to the prior art that it is difficult to reduce the size of semiconductor chips or reduce the density of connecting members of semiconductor chips, and providing a TSV semiconductor package manufacturing method that can reduce the size of a semiconductor package, stack a greater number of chips in a dense state, and at the same time manufacture a semiconductor package in a thin plate structure, and a TSV semiconductor package manufactured thereby.
이하에서는 도면을 참조하여 본 실시예에 따른 티에스브이 반도체 패키지 제조방법(S100)을 구성하는 각 단계에 대해 상세히 설명한다.Hereinafter, each step of the TSV semiconductor package manufacturing method (S100) according to the present embodiment will be described in detail with reference to the drawings.
본 실시예에 따른 티에스브이 반도체 패키지 제조방법(S100)의 하부칩 실장단계(S110)는, 인쇄회로기판(PCB)의 상부면에 제1 티에스브이 칩(TSV Chip)을 접합 후 기설정된 두께로 씨닝(thinning) 처리하는 과정을 수행한다.The lower chip mounting step (S110) of the TSV semiconductor package manufacturing method (S100) according to the present embodiment performs a process of thinning a first TSV chip to a preset thickness after bonding it to the upper surface of a printed circuit board (PCB).
구체적으로, 도 4 내지 도 9에 도시된 바와 같이, 하부칩 실장단계(S110)는 특정 과정을 수행하는 언더필단계(S115)를 더 포함하는 구성일 수 있다. 언더필단계(S115)는 제1 티에스브이 칩을 접합한 후, 제1 티에스브이 칩과 인쇄회로기판 사이의 공간을 에폭시 기반의 소재로 채워 접합부에 인가되는 소성 응력을 흡수하여 접합부의 신뢰성을 확보하는 과정을 수행한다.Specifically, as illustrated in FIGS. 4 to 9, the lower chip mounting step (S110) may further include an underfill step (S115) that performs a specific process. The underfill step (S115) performs a process of filling the space between the first TSV chip and the printed circuit board with an epoxy-based material after bonding the first TSV chip to absorb the plastic stress applied to the bonding portion and secure the reliability of the bonding portion.
본 실시예에 따른 내식층 도금단계(S120)는, 도 11에 도시된 바와 같이, 하부칩 실장단계(S110) 이후 노출된 티에스브이 구리(TSV Cu)에 무전해 주석(Sn) 도금 처리하는 과정을 수행한다.The corrosion-resistant layer plating step (S120) according to the present embodiment, as illustrated in FIG. 11, performs a process of electroless tin (Sn) plating on the exposed TSV copper (TSV Cu) after the lower chip mounting step (S110).
도 12에는 본 발명의 일 실시예에 따른 상부칩 실장단계(S130) 및 접착층 적용단계(S140)에서 제2 티에스브이 칩의 접합 전 상태를 나타내는 종단면도가 도시되어 있고, 도 13에는 본 발명의 일 실시예에 따른 상부칩 실장단계(S130) 및 접착층 적용단계(S140)에서 제2 티에스브이 칩의 접합 후 상태를 나타내는 종단면도가 도시되어 있으며, 도 14에는 본 발명의 일 실시예에 따른 내식층 도금단계(S120), 상부칩 실장단계(S130) 및 접착층 적용단계(S140)를 통해 다수의 티에스브이 칩을 적층 및 접합한 상태를 나타내는 종단면도가 도시되어 있다. 또한, 도 15에는 본 발명의 일 실시예에 따른 티에스브이 칩의 다양한 범프 형상을 나타내는 종단면도가 도시되어 있다FIG. 12 is a cross-sectional view showing a state before bonding of a second TSV chip in an upper chip mounting step (S130) and an adhesive layer application step (S140) according to an embodiment of the present invention, FIG. 13 is a cross-sectional view showing a state after bonding of a second TSV chip in an upper chip mounting step (S130) and an adhesive layer application step (S140) according to an embodiment of the present invention, and FIG. 14 is a cross-sectional view showing a state in which a plurality of TSV chips are stacked and bonded through a corrosion-resistant layer plating step (S120), an upper chip mounting step (S130), and an adhesive layer application step (S140) according to an embodiment of the present invention. In addition, FIG. 15 is a cross-sectional view showing various bump shapes of a TSV chip according to an embodiment of the present invention.
또한, 도 16에는 본 발명의 일 실시예에 따른 하부칩 실장부(120) 및 상부칩 실장부(140)의 도금처리 상태를 나타내는 종단면도가 도시되어 있고, 도 17에는 본 발명의 또 다른 실시예에 따른 하부칩 실장부(120) 및 상부칩 실장부(140)의 도금처리 상태를 나타내는 종단면도가 도시되어 있다.In addition, FIG. 16 is a cross-sectional view showing the plating treatment state of the lower chip mounting portion (120) and the upper chip mounting portion (140) according to one embodiment of the present invention, and FIG. 17 is a cross-sectional view showing the plating treatment state of the lower chip mounting portion (120) and the upper chip mounting portion (140) according to another embodiment of the present invention.
이들 도면을 참조하면, 본 실시예에 따른 상부칩 실장단계(S130)는, 내식층 도금단계(S120) 이후 제1 티에스브이 칩(TSV Chip)의 상부면에 제2 티에스브이 칩(TSV Chip)을 안착하여 티에스브이 주석도금(TSV Sn도금)과 제2 티에스브이 칩(TSV Chip)의 범프(Bump)를 접합하는 과정을 수행한다.Referring to these drawings, the upper chip mounting step (S130) according to the present embodiment performs a process of mounting a second TSV chip on the upper surface of a first TSV chip after the corrosion-resistant layer plating step (S120) and bonding the TSV tin plating (TSV Sn plating) and the bump of the second TSV chip.
구체적으로, 상부칩 실장단계(S130)에서, 티에스브이 주석도금의 두께는 0.1 내지 2.0 마이크로미터 범위 내의 길이임이 바람직하다.Specifically, in the upper chip mounting step (S130), the thickness of the TSV tin plating is preferably within the range of 0.1 to 2.0 micrometers.
본 실시예에 따른 접착층 적용단계(S140)는, 도 12 내지 도 14에 도시된 바와 같이, 상부칩 실장단계(S130)와 동시에 실시되는 구성으로서, 제1 티에스브이 칩과 제2 티에스브이 칩 접합 부분에 접착소재를 적용하여 물리적 접합력과 내식성 특성을 확보하는 과정을 수행한다.The adhesive layer application step (S140) according to the present embodiment is a configuration that is performed simultaneously with the upper chip mounting step (S130), as illustrated in FIGS. 12 to 14, and performs a process of applying an adhesive material to the joint portion of the first TSV chip and the second TSV chip to secure physical bonding strength and corrosion resistance characteristics.
구체적으로, 접착층 적용단계(S140)에서, 접착소재는 내화학적 특성을 가지는 SiO2 접착소재 또는 Organic 접착소재임이 바람직하다.Specifically, in the adhesive layer application step (S140), it is preferable that the adhesive material be a SiO2 adhesive material or an organic adhesive material having chemically resistant properties.
또한, 도 15에 도시된 바와 같이, 본 발명의 일 실시예에 따른 티에스브이 칩의 다양한 범프 형상은 다양한 형태를 적용할 수 있다.In addition, as illustrated in FIG. 15, various bump shapes of the TSV chip according to one embodiment of the present invention can be applied in various forms.
한편, 도 16 및 도 17에 도시된 바와 같이 하부칩 실장부(120) 및 상부칩 실장부(140)에는 다양한 소재를 이용하여 도금처리될 수 있다.Meanwhile, as shown in FIGS. 16 and 17, the lower chip mounting portion (120) and the upper chip mounting portion (140) can be plated using various materials.
상기 언급한 본 실시예에 따른 티에스브이 반도체 패키지 제조방법(S100)에 의해 티에스브이 반도체 패키지(100)를 제조할 수 있다.A TSV semiconductor package (100) can be manufactured by the TSV semiconductor package manufacturing method (S100) according to the above-mentioned embodiment.
도 2 및 도 3에 도시된 바와 같이, 본 실시예에 따른 티에스브이 반도체 패키지(100)는, 특정 구조의 인쇄회로기판 형성부(110), 하부칩 실장부(120), 언더필 형성부(130), 상부칩 실장부(140) 및 인캡슐레이션부(150)를 포함하는 구성일 수 있다.As illustrated in FIGS. 2 and 3, the TSV semiconductor package (100) according to the present embodiment may be configured to include a printed circuit board forming portion (110) of a specific structure, a lower chip mounting portion (120), an underfill forming portion (130), an upper chip mounting portion (140), and an encapsulation portion (150).
구체적으로, 하부칩 실장부(120)는 인쇄회로기판 상부면에 하부칩 실장단계(S110)를 통해 접합된 TSV 칩 구조이다. 언더필 형성부(130)는 인쇄회로기판과 하부칩 실장부(120) 사이에 충진된 구조로서, 제1 티에스브이 칩과 인쇄회로기판 사이의 공간을 에폭시 기반의 소재로 채워 접합부에 인가되는 소성 응력을 흡수하여 접합부의 신뢰성을 확보하는 구성이다. 상부칩 실장부(140)는 하부칩 실장부(120)의 상부면에 상부칩 실장단계(S130)를 통해 접합된 TSV 칩 구조이다. 또한, 인캡슐레이션부(150)는 도 2에 도시된 바와 같이, 인쇄회로기판의 상부면에 형성되는 구성으로서, 하부칩 실장부(120), 언더필 형성부(130) 및 상부칩 실장부(140)를 감싸는 구조로 형성되고, 에폭시 몰드 컴파운드(EMC, Epoxy mold compound) 소재를 이용하여 열, 수분, 충격으로부터 보호할 수 있는 구조로 몰딩 처리된 구조이다.Specifically, the lower chip mounting portion (120) is a TSV chip structure bonded to the upper surface of the printed circuit board through a lower chip mounting step (S110). The underfill forming portion (130) is a structure filled between the printed circuit board and the lower chip mounting portion (120), and is a configuration that fills the space between the first TSV chip and the printed circuit board with an epoxy-based material to absorb plastic stress applied to the joint, thereby ensuring the reliability of the joint. The upper chip mounting portion (140) is a TSV chip structure bonded to the upper surface of the lower chip mounting portion (120) through an upper chip mounting step (S130). In addition, the encapsulation portion (150) is formed as a structure formed on the upper surface of the printed circuit board as illustrated in FIG. 2, and is formed to surround the lower chip mounting portion (120), the underfill forming portion (130), and the upper chip mounting portion (140), and is a structure that is molded using an epoxy mold compound (EMC) material to protect against heat, moisture, and impact.
이상에서 설명한 바와 같이, 본 발명의 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지에 따르면, 특정 과정을 수행하는 하부칩 실장단계(S110), 내식층 도금단계(S120), 상부칩 실장단계(S130) 및 접착층 적용단계(S140)를 구비함으로써, 반도체 칩들의 크기를 축소하거나 반도체 칩의 연결 부재들의 밀도를 축소하기 어려운 종래기술에 따른 문제점을 해결할 수 있고, 반도체 패키지의 크기를 축소시킬 수 있고, 더 많은 수의 칩을 밀집된 상태로 적층하여 구성할 수 있으며, 이와 동시에 박판형 구조로 반도체 패키지를 제작할 수 있는 티에스브이 반도체 패키지 제조방법 및 이에 의해 제조된 티에스브이 반도체 패키지를 제공할 수 있다.As described above, according to the method for manufacturing a TSV semiconductor package of the present invention and the TSV semiconductor package manufactured thereby, by having a lower chip mounting step (S110), a corrosion-resistant layer plating step (S120), an upper chip mounting step (S130), and an adhesive layer application step (S140) that perform specific processes, it is possible to solve the problem according to the prior art that it is difficult to reduce the size of semiconductor chips or reduce the density of connecting members of semiconductor chips, and it is possible to reduce the size of the semiconductor package, configure a larger number of chips by stacking them in a dense state, and at the same time, it is possible to provide a TSV semiconductor package manufacturing method and a TSV semiconductor package manufactured thereby that can manufacture a semiconductor package in a thin plate structure.
이상의 본 발명의 상세한 설명에서는 그에 따른 특별한 실시예에 대해서만 기술하였다. 하지만 본 발명은 상세한 설명에서 언급되는 특별한 형태로 한정되는 것이 아닌 것으로 이해되어야 하며, 오히려 첨부된 청구범위에 의해 정의되는 본 발명의 정신과 범위 내에 있는 모든 변형물과 균등물 및 대체물을 포함하는 것으로 이해되어야 한다.The detailed description of the present invention above has described only specific embodiments thereof. However, it should be understood that the present invention is not limited to the specific embodiments described in the detailed description, but rather encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
즉, 본 발명은 상술한 특정의 실시예 및 설명에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형 실시가 가능하며, 그와 같은 변형은 본 발명의 보호 범위 내에 있게 된다.That is, the present invention is not limited to the specific embodiments and descriptions described above, and anyone with ordinary skill in the art to which the present invention pertains can make various modifications without departing from the gist of the present invention claimed in the claims, and such modifications are within the protection scope of the present invention.
S100: 티에스브이 반도체 패키지 제조방법
S110: 하부칩 실장단계
S115: 언더필단계
S120: 내식층 도금단계
S130: 상부칩 실장단계
S140: 접착층 적용단계
100: 티에스브이 반도체 패키지
110: 인쇄회로기판 형성부
120: 하부칩 실장부
130: 언더필 형성부
140: 상부칩 실장부
150: 인캡슐레이션부S100: TSV semiconductor package manufacturing method
S110: Lower chip mounting stage
S115: Underfill stage
S120: Corrosion-resistant layer plating step
S130: Top chip mounting stage
S140: Adhesive layer application step
100: TSV semiconductor package
110: Printed circuit board formation section
120: Lower chip mounting section
130: Underfill formation section
140: Upper chip mounting part
150: Encapsulation section
Claims (5)
상기 제1 티에스브이 칩을 접합한 후, 제1 티에스브이 칩과 인쇄회로기판 사이의 공간을 에폭시 기반의 소재로 채워 접합부에 인가되는 소성 응력을 흡수하여 접합부의 신뢰성을 확보하는 언더필단계(S115);
상기 하부칩 실장단계(S110) 이후 씨닝(thinning) 처리 과정에서 노출된 티에스브이 구리(TSV Cu)에 무전해 주석(Sn) 도금 처리하는 내식층 도금단계(S120);
상기 내식층 도금단계(S120) 이후 제1 티에스브이 칩(TSV Chip)의 상부면에 제2 티에스브이 칩(TSV Chip)을 안착하여 티에스브이 주석도금(TSV Sn도금)과 제2 티에스브이 칩(TSV Chip)의 범프(Bump)를 접합하고, 티에스브이 주석도금의 두께는 0.1 내지 2.0 마이크로미터 범위 내의 길이인 상부칩 실장단계(S130); 및
상기 상부칩 실장단계(S130)와 동시에 실시되고, 제1 티에스브이 칩과 제2 티에스브이 칩 접합 부분에 접착소재를 적용하여 물리적 접합력과 내식성 특성을 확보하고, 접착소재는 내화학적 특성을 가지는 SiO2 접착소재 또는 Organic 접착소재인 접착층 적용단계(S140);
을 포함하고,
상기 상부칩 실장단계(S130)에서,
상기 티에스브이 주석도금의 두께는 0.1 내지 2.0 마이크로미터 범위 내의 길이이고,
상기 접착층 적용단계(S140)에서,
상기 접착소재는 내화학적 특성을 가지는 SiO2 접착소재 또는 Organic 접착소재인 것을 특징으로 하는 티에스브이 반도체 패키지 제조방법.
A lower chip mounting step (S110) in which a first TSV chip is bonded to the upper surface of a printed circuit board (PCB) and then thinned to a preset thickness;
After bonding the first TSV chip, an underfill step (S115) is performed to fill the space between the first TSV chip and the printed circuit board with an epoxy-based material to absorb the plastic stress applied to the bonding portion and secure the reliability of the bonding portion;
A corrosion-resistant layer plating step (S120) in which electroless tin (Sn) plating is performed on the exposed TSV copper (TSV Cu) during the thinning process after the above-mentioned lower chip mounting step (S110);
After the above-mentioned corrosion-resistant layer plating step (S120), a second TSV chip is mounted on the upper surface of the first TSV chip, and the TSV tin plating (TSV Sn plating) and the bump of the second TSV chip are bonded, and the thickness of the TSV tin plating is a length within the range of 0.1 to 2.0 micrometers; and
A step of applying an adhesive layer (S140) that is performed simultaneously with the above upper chip mounting step (S130) and secures physical bonding strength and corrosion resistance by applying an adhesive material to the joint portion of the first TSV chip and the second TSV chip, and the adhesive material is a SiO2 adhesive material or an organic adhesive material having chemical resistance properties;
Including,
In the above upper chip mounting step (S130),
The thickness of the above TSV tin plating is a length within the range of 0.1 to 2.0 micrometers,
In the above adhesive layer application step (S140),
A method for manufacturing a TSV semiconductor package, characterized in that the above adhesive material is a SiO2 adhesive material or an organic adhesive material having chemically resistant properties.
인쇄회로기판 형성부(110);
상기 인쇄회로기판 상부면에 하부칩 실장단계(S110)를 통해 접합된 하부칩 실장부(120);
상기 인쇄회로기판과 하부칩 실장부(120) 사이에 충진된 구조의 언더필 형성부(130);
상기 하부칩 실장부(120)의 상부면에 상부칩 실장단계(S130)를 통해 접합된 상부칩 실장부(140); 및
상기 인쇄회로기판의 상부면에 형성되고, 하부칩 실장부(120), 언더필 형성부(130) 및 상부칩 실장부(140)를 감싸는 구조로 형성되고, 에폭시 몰드 컴파운드(EMC, Epoxy mold compound) 소재를 이용하여 열, 수분, 충격으로부터 보호할 수 있는 구조로 몰딩 처리된 인캡슐레이션부(150);
를 포함하는 것을 특징으로 하는 티에스브이 반도체 패키지.
A TSV semiconductor package manufactured by a semiconductor package manufacturing method according to Article 1,
Printed circuit board forming part (110);
A lower chip mounting portion (120) bonded to the upper surface of the printed circuit board through a lower chip mounting step (S110);
An underfill forming portion (130) having a structure filled between the above printed circuit board and the lower chip mounting portion (120);
An upper chip mounting portion (140) joined to the upper surface of the lower chip mounting portion (120) through an upper chip mounting step (S130); and
An encapsulation portion (150) formed on the upper surface of the printed circuit board and having a structure that surrounds the lower chip mounting portion (120), the underfill forming portion (130), and the upper chip mounting portion (140), and is molded using an epoxy mold compound (EMC) material to provide protection from heat, moisture, and impact;
A TSV semiconductor package characterized by including:
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