KR102903511B1 - Semiconductor package including stacked semiconductor chips - Google Patents

Abstract

A semiconductor package of the present embodiment comprises: a base layer; a first chip stack and a second chip stack sequentially stacked on the base layer, wherein each of the first and second chip stacks includes a plurality of semiconductor chips that are offset-stacked so that chip pads of one edge are exposed, and the chip pads include a stack identification pad for identifying the first chip stack and the second chip stack, and a chip identification pad for identifying the plurality of semiconductor chips in each of the first and second chip stacks; -; a first inter-chip wire connecting those of the chip identification pads of the plurality of semiconductor chips of the first chip stack to which power is applied; a first stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first chip stack to the base layer; a second inter-chip wire connecting those of the chip identification pads of the plurality of semiconductor chips of the second chip stack to which power is applied; And a second stack wire that connects the chip identification pad of the semiconductor chip at the lowest position of the second chip stack to the base layer, wherein the arrangement of the chip identification pads to which the power is applied in the first chip stack is performed so that the first inter-chip wire does not skip any of the plurality of semiconductor chips included in the first chip stack, and the arrangement of the chip identification pads to which the power is applied in the second chip stack is performed so that the second inter-chip wire does not skip any of the plurality of semiconductor chips included in the second chip stack.

Description

Semiconductor package including stacked semiconductor chips {SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS}

This patent document relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips stacked in a vertical direction.

Electronic products are becoming increasingly smaller while requiring high-capacity data processing. Consequently, the need to increase the integration of semiconductor devices used in these products is growing.

However, due to limitations in semiconductor integration technology, it is difficult to satisfy the required functions with just a single semiconductor chip, so semiconductor packages are being manufactured in the form of multiple semiconductor chips embedded in a single semiconductor package.

Multiple semiconductor chips can be stacked vertically and electrically connected to each other by interconnectors such as wires.

The problem that embodiments of the present invention seek to solve is to provide a semiconductor package capable of reducing defects and improving operating characteristics while satisfying high performance/high capacity requirements.

According to an embodiment of the present invention for solving the above problem, a semiconductor package comprises: a base layer; a first chip stack and a second chip stack sequentially stacked on the base layer, wherein each of the first and second chip stacks includes a plurality of semiconductor chips that are offset-stacked so that chip pads of one edge are exposed, and the chip pads include a stack identification pad for identifying the first chip stack and the second chip stack, and a chip identification pad for identifying the plurality of semiconductor chips in each of the first and second chip stacks; -; a first inter-chip wire connecting those of the chip identification pads of the plurality of semiconductor chips of the first chip stack to which power is applied; a first stack wire connecting the chip identification pad of the lowest semiconductor chip of the first chip stack to the base layer; a second inter-chip wire connecting those of the chip identification pads of the plurality of semiconductor chips of the second chip stack to which power is applied; And a second stack wire that connects the chip identification pad of the semiconductor chip at the lowest position of the second chip stack to the base layer, wherein the arrangement of the chip identification pads to which the power is applied in the first chip stack is performed so that the first inter-chip wire does not skip any of the plurality of semiconductor chips included in the first chip stack, and the arrangement of the chip identification pads to which the power is applied in the second chip stack is performed so that the second inter-chip wire does not skip any of the plurality of semiconductor chips included in the second chip stack.

According to embodiments of the present invention, a semiconductor package capable of reducing defects and improving operating characteristics while satisfying high performance/high capacity requirements can be provided.

Figure 1a is a cross-sectional view showing a semiconductor package of a comparative example.
Fig. 1b is a plan view from above of a portion of the semiconductor package of Fig. 1a.
FIG. 1c is a diagram showing the power supply status of chip identification pads of a plurality of semiconductor chips included in the semiconductor package of FIG. 1a and FIG. 1b as logical values.
FIG. 1d is a drawing for explaining a problem that may occur in the semiconductor package of FIG. 1a and FIG. 1b.
FIG. 2a is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention.
Fig. 2b is a plan view from above of a portion of the semiconductor package of Fig. 2a.
FIG. 2c is a diagram showing the power supply status of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in the semiconductor package of FIGS. 2a and 2b as logical values.
FIG. 2D is a diagram showing the power supply status of a stack identification pad and a chip identification pad of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of the present invention as logical values.
FIG. 3a is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention.
Fig. 3b is a plan view from above of a portion of the semiconductor package of Fig. 3a.
FIG. 3c is a diagram showing the power supply status of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in the semiconductor package of FIGS. 3a and 3b as logical values.
FIGS. 3D to 3F are diagrams showing the power supply status of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to other embodiments of the present invention as logical values.

Below, various embodiments are described in detail with reference to the attached drawings.

The drawings are not necessarily drawn to scale, and in some instances, the proportions of at least some of the structures depicted in the drawings may be exaggerated to clearly illustrate features of the embodiments. When a multilayer structure having two or more layers is disclosed in the drawings or detailed description, the relative positional relationship or arrangement order of the layers as depicted reflects only a particular embodiment and the invention is not limited thereto, and the relative positional relationship or arrangement order of the layers may vary. Furthermore, the drawings or detailed description of a multilayer structure may not reflect all of the layers present in a particular multilayer structure (e.g., one or more additional layers may exist between two depicted layers). For example, when a first layer in a multilayer structure in the drawings or detailed description is on a second layer or on a substrate, it may be indicated that the first layer can be formed directly on the second layer or directly on the substrate, as well as that one or more other layers can be present between the first and second layers or between the first layer and the substrate.

Before describing this embodiment, the semiconductor package of the comparative example and its problems will be described.

Fig. 1a is a cross-sectional view showing a semiconductor package of a comparative example, and Fig. 1b is a plan view of a portion of the semiconductor package of Fig. 1a as seen from above. Fig. 1c is a diagram showing the power supply status of chip identification pads of a plurality of semiconductor chips included in the semiconductor packages of Figs. 1a and 1b as logical values. Fig. 1d is a diagram for explaining problems that may occur in the semiconductor packages of Figs. 1a and 1b.

First, referring to FIGS. 1A and 1B, the semiconductor package of the comparative example may include a base layer (100), a chip stack (110), an external connection terminal (130), and a molding layer (140).

The base layer (100) may be a layer having a circuit and/or wiring structure (not shown) for electrically connecting the chip stack (110) to external components of the semiconductor package. For example, the base layer (100) may include a substrate such as a printed circuit board (PCB), an interposer, a redistribution layer, etc. Alternatively, when the chip stack (110) includes a memory chip, the base layer (100) may be a semiconductor chip including a logic circuit that supports operations of the memory chip, such as reading data from the memory chip or writing data to the memory chip.

The base layer (100) may have one surface, for example, the upper surface, on which the chip stack (110) is arranged, and the other surface, for example, the lower surface, on which the external connection terminal (130) is arranged. A pad (102) for electrical connection with the chip stack (110) may be arranged on the upper surface of the base layer (100). The pad (102) may be part of the circuit and/or wiring structure of the base layer (100). Furthermore, although not illustrated, various pads for electrical connection with the base layer (100) and other components, for example, the external connection terminal (130), may be further arranged on the upper surface and/or lower surface of the base layer (100).

The chip stack (110) may include a plurality of semiconductor chips (111 to 118) that are vertically stacked on one surface of the base layer (100). In this comparative example, the chip stack (110) includes eight semiconductor chips (111 to 118), but the number of semiconductor chips included in the chip stack (110) may vary. In particular, the number of semiconductor chips included in the chip stack (110) may be 2 ^N. N may be a natural number greater than or equal to 2. For convenience of explanation, the plurality of semiconductor chips (111 to 118) will be referred to as a first semiconductor chip (111), a second semiconductor chip (112), a third semiconductor chip (113), a fourth semiconductor chip (114), a fifth semiconductor chip (115), a sixth semiconductor chip (116), a seventh semiconductor chip (117), and an eighth semiconductor chip (118) according to the distance from the base layer (100). The first to eighth semiconductor chips (111 to 118) may be identical memory chips, such as DRAM or NAND flash memory chips. However, the present disclosure is not limited thereto, and the first to eighth semiconductor chips (111 to 118) may be semiconductor chips of various types and functions.

The first to eighth semiconductor chips (111 to 118) can be attached to the upper surface of the base layer (100) and the upper surface of the first to seventh semiconductor chips (111 to 117), respectively, by an adhesive layer (not shown) formed on their lower surfaces.

A plurality of chip pads (CP) may be arranged on the upper surface of each of the first to eighth semiconductor chips (111 to 118). The plurality of chip pads (CP) may be arranged on one edge region of each of the first to eighth semiconductor chips (111 to 118) in the first direction. The first to eighth semiconductor chips (111 to 118) may be stacked in a face-up shape, that is, in a shape in which the upper surface on which the chip pads (CP) are arranged faces upward and the lower surface faces the base layer (110). At this time, the first to eighth semiconductor chips (111 to 118) may be offset-stacked in a direction from one side in the first direction adjacent to the chip pads (CP) toward the other side in the first direction located opposite thereto so that all of the chip pads (CP) of each of the first to eighth semiconductor chips (111 to 118) are exposed. In the second direction, one side surface of the first to eighth semiconductor chips (111 to 118) can be substantially aligned with each other, and in the second direction, the other side surface of the first to eighth semiconductor chips (111 to 118) can be substantially aligned with each other.

In each of the first to eighth semiconductor chips (111 to 118), a plurality of chip pads (CP) may be arranged in a row along a second direction intersecting the first direction. The chip pads (CP) corresponding to each other of the first to eighth semiconductor chips (111 to 118), for example, the chip pads (CP) substantially aligned with each other along the first direction, may perform the same function. As an example, in the plan view of FIG. 1B, the chip pads (CP) located at the leftmost side of the first to eighth semiconductor chips (111 to 118) may be connected to the pads (102) of the base layer (100) by being connected to each other by wires (120), and thus may function as terminals for supplying power from the base layer (100) or exchanging signals with the base layer (100). In particular, some of the plurality of chip pads (CP) may function as chip identification pads (CP1, CP2, CP3) for identifying the first to eighth semiconductor chips (111 to 118) included in the chip stack (110), respectively. The arrangement of the chip identification pads (CP1, CP2, CP3), power supply, and connection thereof to the wire (120) will be described later.

The external connection terminal (130) is formed on the lower surface of the base layer (100) and can function to connect to external components of the semiconductor package. The external connection terminal (130) can include various interconnectors such as solder balls.

The molding layer (140) can cover the chip stack (110) on the upper surface of the base layer (100). The molding layer (140) can include various molding materials such as EMC (Epoxy Molding Compound).

In the semiconductor package as above, since the chip stack (110) includes 2 ³ semiconductor chips (111 to 118), each of the first to eighth semiconductor chips (111 to 118) may include three chip identification pads (CP1, CP2, CP3), that is, a first chip identification pad (CP1), a second chip identification pad (CP2), and a third chip identification pad (CP3). This is because 2 ³ state expressions are possible by using three chip identification pads (CP1, CP2, CP3). If the chip stack (110) includes 2 ^N semiconductor chips, each semiconductor chip may include N chip identification pads. By using N chip identification pads, 2 ^N state expressions may be possible.

In the first to eighth semiconductor chips (111 to 118), the first chip identification pads (CP1) may be substantially aligned with each other along a first direction, the second chip identification pads (CP2) may be substantially aligned with each other along the first direction, and the third chip identification pads (CP1) may be substantially aligned with each other along the first direction. In addition, in each of the first to eighth semiconductor chips (111 to 118), the first to third chip identification pads (CP1, CP2, CP3) may be arranged adjacent to each other in the second direction. Depending on the combination of power applied to each of the first to third chip identification pads (CP1, CP2, CP3), the first to eighth semiconductor chips (111 to 118) may be distinguished from each other. This will be described below with further reference to FIG. 1C together with FIG. 1B.

Referring to FIGS. 1B and 1C, each of the first to third chip identification pads (CP1, CP2, CP3) of the first to eighth semiconductor chips (111 to 118) may be in a powered state or a floating state. Here, the applied power may include various levels of voltage. For example, the applied power may be a power supply voltage (VDD). The state in which the first to third chip identification pads (CP1, CP2, CP3) are powered may be indicated by a logic value of '1', and the floating state may be indicated by a logic value of '0'. Each of the first to eighth semiconductor chips (111 to 118) may be expressed by a combination of the logic values of its first to third chip identification pads (CP1, CP2, CP3). At this time, the power supply state of the first to third chip identification pads (CP1, CP2, CP3) of each of the first to eighth semiconductor chips (111 to 118) may be determined so that the combinations of logic values representing the first to eighth semiconductor chips (111 to 118) are different from each other. For example, when the first semiconductor chip (111) is represented by a combination of logic values of '000', the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (111) may all be in a floating state. In addition, when the second semiconductor chip (112) is represented by a combination of logic values of '100', power may be supplied to the first chip identification pad (CP1) of the second semiconductor chip (112) and the second and third chip identification pads (CP2, CP3) may be in a floating state. In a similar manner, the first to third chip identification pads (CP1, CP2, CP3) of each of the third to eighth semiconductor chips (113 to 118) may be powered or in a floating state so that the third to eighth semiconductor chips (113 to 118) are all represented by different combinations of logical values.

Among the first to third chip identification pads (CP1, CP2, CP3) of the first to eighth semiconductor chips (111 to 118), those to which power is applied, that is, those expressed as a logic value '1' in FIG. 1C, can be connected to a wire (120). This is to receive power from the base layer (100) by being connected to the pad (102) of the base layer (100) through the wire (120). On the other hand, among the first to third chip identification pads (CP1, CP2, CP3) of the first to eighth semiconductor chips (111 to 118), those in a floating state, that is, those expressed as a logic value '0' in FIG. 1C, may not be connected to the wire (120). More specifically, among the first chip identification pads (CP1) aligned in the first direction, the first chip identification pads (CP1) of the second, fourth, sixth, and eighth semiconductor chips (112, 114, 116, 118) to which power is applied may be connected to the pad (102) of the base layer (100) while being connected to each other by a wire (120). In addition, among the second chip identification pads (CP2) aligned in the first direction, the second chip identification pads (CP2) of the third, fourth, seventh, and eighth semiconductor chips (113, 114, 117, 118) to which power is applied may be connected to the pad (102) of the base layer (100) while being connected to each other by a wire (120). In addition, the third chip identification pads (CP3) of the fifth to eighth semiconductor chips (115 to 118) to which power is applied among the third chip identification pads (CP3) aligned in the first direction can be connected to the pads (102) of the base layer (100) while being connected to each other by wires (120).

However, in this case, the wire (120) may be a long wire. For reference, a long wire refers to a wire that skips one or more chip pads (CP) among the chip pads (CP) aligned in the first direction, and a short wire may refer to a wire that connects adjacent chip pads (CP) among the chip pads (CP) aligned in the first direction, i.e., a wire that does not skip any chip pads (CP). For example, a wire (120) that connects the first chip identification pad (CP1) of the second semiconductor chip (112) and the first chip identification pad (CP1) of the fourth semiconductor chip (114) may be a long wire because it skips the third semiconductor chip (113). In addition, for example, the wire (120) connecting the second chip identification pad (CP2) of the fourth semiconductor chip (114) and the second chip identification pad (CP2) of the seventh semiconductor chip (117) may be a long wire because it skips the fifth and sixth semiconductor chips (115, 116). The wires (120) corresponding to the long wires may contact each other in the second direction during the molding process, which may cause an electrical short defect. This defect may be further aggravated when the first to eighth semiconductor chips (111 to 118) are not aligned with each other in the second direction due to a process error in the step of stacking the first to eighth semiconductor chips (111 to 118). The electrical short defect pattern is exemplarily shown in FIG. 1D.

Referring to FIG. 1d, among the chip pads (CP) aligned in the first direction, a short wire (SW) connecting adjacent chip pads (CP) in the first direction, i.e., a short wire (SW) that does not skip chips, may not bend or fall sideways, thereby preventing an electrical short defect from occurring.

On the other hand, among the chip pads (CP) aligned in the first direction, long wires (LW) connecting non-adjacent chip pads (CP) in the first direction, i.e., long wires (LW) that skip at least one chip, are more likely to bend or fall sideways. Accordingly, adjacent long wires (LW) in the second direction may come into contact with each other, resulting in an electrical short-circuit defect.

In the embodiments described below, the electrical short-circuit defects occurring in the semiconductor package of the comparative example described above are prevented by using only short wires that do not cross chips as the wires connecting the chip identification pads. Furthermore, by optimizing the arrangement of the chip identification pads and the wire connections to the chip identification pads, the length of the wires is reduced and the signal transmission characteristics are improved accordingly.

FIG. 2A is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and FIG. 2B is a plan view showing a portion of the semiconductor package of FIG. 2A as seen from above. For reference, when the semiconductor package of FIG. 2A is viewed from above, part or all of the first chip stack may be obscured by the second chip stack and thus not visible, but for convenience of explanation, the plan view of FIG. 2B illustrates chip pads of the first and second chip stacks as visible. FIG. 2C is a diagram showing stack identification pads of a plurality of semiconductor chips included in the semiconductor packages of FIGS. 2A and 2B and power supply states of the chip identification pads as logical values.

First, referring to FIGS. 2A and 2B, the semiconductor package of the present embodiment includes a base layer (200), a first chip stack (210) formed on one surface of the base layer (200) and including a plurality of semiconductor chips (211 to 214), a first wire (230) connecting the first chip stack (210) and the base layer (200) while connecting the plurality of semiconductor chips (211 to 214) to each other, a second chip stack (220) formed on the first chip stack (210) and including a plurality of semiconductor chips (221 to 224), a second wire (240) connecting the second chip stack (220) and the base layer (200) while connecting the plurality of semiconductor chips (221 to 224) to each other, an external connection terminal (250) formed on the other surface of the base layer (200), and a first and second chip stacks (210, 220) covering the first and second chip stacks. It may include a molding layer (260).

The base layer (200) may be a layer having a circuit and/or wiring structure (not shown) for electrically connecting the first and second chip stacks (210, 220) to external components of the semiconductor package. For example, the base layer (200) may include a substrate such as a printed circuit board, an interposer, a redistribution layer, etc. Alternatively, the base layer (200) may be a semiconductor chip including a logic circuit that supports an operation of the memory chip, for example, an operation of reading data from the memory chip or writing data to the memory chip, when the first and second chip stacks (210, 220) include a memory chip.

The base layer (200) may have one surface, for example, the upper surface, on which the first and second chip stacks (210, 220) are arranged, and the other surface, for example, the lower surface, on which the external connection terminals (250) are arranged. A pad (202) for electrical connection with the first and second chip stacks (210) may be arranged on the upper surface of the base layer (200). The pad (202) may be part of the circuit and/or wiring structure of the base layer (200). Furthermore, although not illustrated, various pads for electrical connection with the base layer (200) and other components, for example, the external connection terminals (250), may be further arranged on the upper surface and/or lower surface of the base layer (200).

The first chip stack (210) may include a plurality of semiconductor chips (211 to 214) that are vertically stacked on one surface of the base layer (200). In the present embodiment, the first chip stack (210) includes four semiconductor chips (211 to 214), but the number of semiconductor chips included in the first chip stack (210) may vary. In particular, the number of semiconductor chips included in the first chip stack (210) may be 2 ^N-1 . Here, N may be a natural number greater than or equal to 2. For convenience of explanation, the plurality of semiconductor chips (211 to 214) will be referred to as a first semiconductor chip (211), a second semiconductor chip (212), a third semiconductor chip (213), and a fourth semiconductor chip (214) according to the distance from the base layer (200). The first to fourth semiconductor chips (211 to 214) may be identical memory chips, such as DRAM or NAND flash memory chips. However, the present disclosure is not limited thereto, and the first to fourth semiconductor chips (211 to 214) may be semiconductor chips of various types and functions.

An adhesive layer (AL) may be formed on the lower surface of each of the first to fourth semiconductor chips (211 to 214). By the adhesive layer (AL), the first semiconductor chip (211) may be attached to the upper surface of the base layer (200), and the second to fourth semiconductor chips (212 to 214) may be attached to the upper surfaces of the first to third semiconductor chips (211 to 213) positioned directly below them, respectively. The adhesive layer (AL) may include an insulating adhesive material such as a die attach film (DAF).

A plurality of chip pads (CP) may be arranged on the upper surface of each of the first to fourth semiconductor chips (211 to 214). The plurality of chip pads (CP) may be arranged on one edge region of each of the first to fourth semiconductor chips (211 to 214) in the first direction. The first to fourth semiconductor chips (211 to 214) may be stacked in a face-up configuration, i.e., in a configuration in which the upper surface on which the chip pads (CP) are arranged faces upward and the lower surface faces the base layer (200). At this time, the first to fourth semiconductor chips (211 to 214) may be offset-stacked in a direction from one side in the first direction adjacent to the chip pads (CP) toward the other side in the first direction located opposite thereto, so that all of the chip pads (CP) of each of the first to fourth semiconductor chips (211 to 214) are exposed. In the second direction, one side surface of the first to fourth semiconductor chips (211 to 214) can be substantially aligned with each other, and in the second direction, the other side surface of the first to fourth semiconductor chips (211 to 214) can be substantially aligned with each other.

In each of the first to fourth semiconductor chips (211 to 214), a plurality of chip pads (CP) may be arranged in a row along a second direction intersecting the first direction. The corresponding chip pads (CP) of the first to fourth semiconductor chips (211 to 214), for example, the chip pads (CP) substantially aligned with each other along the first direction, may perform the same function. As an example, in the plan view of FIG. 2B, the chip pads (CP) located at the leftmost side of each of the first to fourth semiconductor chips (211 to 214) may be connected to the pads (202) of the base layer (200) while being connected to each other by the first wire (230), and thus may function as terminals for supplying power from the base layer (200) or exchanging signals with the base layer (200). In particular, some of the plurality of chip pads (CP) may function as stack identification pads (CP0) for distinguishing between the first chip stack (210) and the second chip stack (220), and chip identification pads (CP1, CP2) for identifying the first to fourth semiconductor chips (211 to 214) included in the first chip stack (210), respectively. The arrangement of the stack identification pads (CP0) and the chip identification pads (CP1, CP2) in the first chip stack (210), power supply, and connection thereof to the first wire (230) will be described later.

The first wire (230) may provide a connection between the first to fourth semiconductor chips (211 to 214) included in the first chip stack (210) and a connection between the first chip stack (210) and the base layer (200). For convenience of explanation, a wire that connects chip pads (CP) between the first to fourth semiconductor chips (211 to 214) among the first wires (230) is referred to as a first inter-chip wire (232), and a wire that connects the chip pad (CP) of the first semiconductor chip (211) located at the lowest position in the first chip stack (210) and the pad (202) of the base layer (200) is referred to as a first stack wire (234). For convenience, the first inter-chip wire (232) is illustrated as a solid line and the first stack wire (234) is illustrated as a dotted line, but this does not reflect the actual shape of the wires.

The second chip stack (220) may include a plurality of semiconductor chips (221 to 224) that are vertically stacked on the chip stack (210). In the present embodiment, the second chip stack (220) includes four semiconductor chips (221 to 224), but the number of semiconductor chips included in the second chip stack (220) may vary. In particular, the number of semiconductor chips included in the second chip stack (220) may be 2 ^N-1 , which is the same as the number of semiconductor chips included in the first chip stack (210). Accordingly, the semiconductor package of the present embodiment may include a total of 2 ^N semiconductor chips. For convenience of explanation, the plurality of semiconductor chips (221 to 224) of the second chip stack (220) will be referred to as a first semiconductor chip (221), a second semiconductor chip (222), a third semiconductor chip (223), and a fourth semiconductor chip (224) according to their distances from the first chip stack (210). The first to fourth semiconductor chips (221 to 224) may be the same memory chips, for example, DRAM or NAND flash memory chips. However, the present disclosure is not limited thereto, and the first to fourth semiconductor chips (221 to 224) may be semiconductor chips having various types and functions. Furthermore, the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) may be the same as the first to fourth semiconductor chips (211 to 214) of the first chip stack (210).

An adhesive layer (AL) may be formed on the lower surface of each of the first to fourth semiconductor chips (221 to 224). By means of the adhesive layer (AL), the first semiconductor chip (221) may be attached to the upper surface of the fourth semiconductor chip (214) located at the top of the first chip stack (210), and the second to fourth semiconductor chips (222 to 224) may be attached to the upper surfaces of the first to third semiconductor chips (221 to 223) located directly below them, respectively.

A plurality of chip pads (CP) may be arranged on the upper surface of each of the first to fourth semiconductor chips (221 to 224). The plurality of chip pads (CP) may be arranged on one edge region of each of the first to fourth semiconductor chips (221 to 224) in the first direction. The first to fourth semiconductor chips (221 to 224) may be stacked in a face-up configuration, i.e., in a configuration in which the upper surface on which the chip pads (CP) are arranged faces upward and the lower surface faces the base layer (200). At this time, the first to fourth semiconductor chips (221 to 224) may be offset-stacked in a direction from one side in the first direction adjacent to the chip pads (CP) toward the other side in the first direction located opposite thereto, so that all of the chip pads (CP) of each of the first to fourth semiconductor chips (221 to 224) are exposed. That is, the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) can be stacked in the same offset direction as the first to fourth semiconductor chips (211 to 214) of the first chip stack (210), and accordingly, the second chip stack (220) can have a step shape identical/similar to the first chip stack (210). One side surface of the first to fourth semiconductor chips (221 to 224) in the second direction can be substantially aligned with each other, and the other side surface of the first to fourth semiconductor chips (221 to 224) in the second direction can be substantially aligned with each other. Furthermore, in the second direction, one side surface of the first to fourth semiconductor chips (221 to 224) can be substantially aligned with one side surface of the first to fourth semiconductor chips (211 to 214), and in the second direction, the other side surface of the first to fourth semiconductor chips (221 to 224) can be substantially aligned with one side surface of the first to fourth semiconductor chips (211 to 214).

In each of the first to fourth semiconductor chips (221 to 224), a plurality of chip pads (CP) may be arranged in a row along a second direction intersecting the first direction. The corresponding chip pads (CP) of the first to fourth semiconductor chips (221 to 224), for example, the chip pads (CP) substantially aligned with each other along the first direction, may perform the same function. As an example, in the plan view of FIG. 2B, the chip pads (CP) located at the leftmost side of each of the first to fourth semiconductor chips (221 to 224) may be connected to the pads (202) of the base layer (200) while being connected to each other by the second wires (240), and thus may function as terminals for supplying power from the base layer (200) or exchanging signals with the base layer (200). Furthermore, the chip pads (CP) aligned in the first direction of the first to fourth semiconductor chips (211 to 214) and the chip pads (CP) aligned in the first direction of the first to fourth semiconductor chips (221 to 224) corresponding to and/or aligned therewith may perform the same function. Accordingly, the first and second wires (230, 240) connected to these aligned chip pads (CP) may be commonly connected to one pad (202) of the base layer (200). Some of the plurality of chip pads (CP) in the second chip stack (220) may function as stack identification pads (CP0) for distinguishing between the first chip stack (210) and the second chip stack (220), and as chip identification pads (CP1, CP2) for identifying the first to fourth semiconductor chips (221 to 224) included in the second chip stack (220), respectively. The arrangement of the stack identification pad (CP0) and the chip identification pads (CP1, CP2) in the second chip stack (220), power supply, and connection to the second wire (240) will be described later.

The second wire (240) may provide a connection between the first to fourth semiconductor chips (221 to 224) included in the second chip stack (220) and a connection between the second chip stack (220) and the base layer (200). For convenience of explanation, a wire that connects the chip pads (CP) between the first to fourth semiconductor chips (221 to 224) among the second wires (240) is referred to as a second inter-chip wire (242), and a wire that connects the chip pad (CP) of the first semiconductor chip (221) located at the bottom and the pad (202) of the base layer (200) is referred to as a second stack wire (244). For convenience, the second inter-chip wire (242) is illustrated as a solid line and the second stack wire (244) is illustrated as a dotted line, but this does not reflect the actual shape of the wires.

Meanwhile, when the second chip stack (220) is stacked on the first chip stack (210), one side of the first semiconductor chip (221) at the bottom of the second chip stack (220) may protrude more than one side of the fourth semiconductor chip (214) at the top of the first chip stack (210) in the direction opposite to the offset direction. The reason for this is to reduce the area occupied by the first and second chip stacks (210, 220) on a plane, while at the same time preventing the second stack wire (244) from contacting the first wire (230) without increasing the length of the second stack wire (244) as much as possible. For reference, due to the distance between the second chip stack (220) and the base layer (200) in the vertical direction, the second stack wire (244) may have a relatively longer length than the first inter-chip wire (232), the first stack wire (234), and the second inter-chip wire (242). As the length of the wire increases, the electrical path becomes longer, which deteriorates the signal transmission characteristics, and therefore, it may be desirable to reduce the length of the second stack wire (244).

In this case, the thickness (T2) of the adhesive layer (AL) on the lower surface of the first semiconductor chip (221) located at the lowermost portion of the second chip stack (220) may be greater than the thickness (T1) of each of the remaining semiconductor chips (211 to 214, and 222 to 224) of the first and second chip stacks (210, 220). This is because the loop of the first inter-chip wire (232) connected to the chip pad (CP) of the fourth semiconductor chip (214) protrudes above the upper surface of the fourth semiconductor chip (214). The thickness (T2) of the adhesive layer (AL) on the lower surface of the first semiconductor chip (221) may have a sufficiently large value so that the lower surface of the first semiconductor chip (221) is spaced apart from the first semiconductor chip (214) at the uppermost portion of the first chip stack (210) while covering the loop.

The external connection terminal (250) is formed on the lower surface of the base layer (200) and can function to connect to external components of the semiconductor package. The external connection terminal (250) can include various interconnectors such as solder balls.

The molding layer (260) can cover the first and second chip stacks (210, 220) on the upper surface of the base layer (200). The molding layer (260) can include various molding materials such as EMC.

In the semiconductor package as described above, since the first chip stack (210) includes 2 ² semiconductor chips (211 to 214), each of the first to fourth semiconductor chips (211 to 214) may include at least two chip identification pads in order to distinguish/identify them within the first chip stack (210). For example, each of the first to fourth semiconductor chips (211 to 214) may include first and second chip identification pads (CP1, CP2). This is because 2 ² state expressions are possible by using two chip identification pads. Furthermore, in order to distinguish/identify the first chip stack (210) and the second chip stack (220), each of the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) may include one stack identification pad (CP0). Since the second chip stack (220) includes ² semiconductor chips (221 to 224), each of the first to fourth semiconductor chips (221 to 224) may include two, i.e., first and second chip identification pads (CP1, CP2), for distinguishing/identifying them within the second chip stack (220). In addition, each of the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) may include one stack identification pad (CP0) for distinguishing/identifying the second chip stack (220) from the first chip stack (210).

In the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) and the first to fourth semiconductor chips (221 to 224) of the second chip stack (220), the stack identification pads (CP0) may be substantially aligned with each other along a first direction, the first chip identification pads (CP1) may be substantially aligned with each other along the first direction, and the second chip identification pads (CP2) may be substantially aligned with each other along the first direction. In each of the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) and the first to fourth semiconductor chips (221 to 224) of the second chip stack (220), the stack identification pads (CP0), the first chip identification pads (CP1), and the second chip identification pads (CP2) may be arranged adjacent to each other in the second direction. However, the present disclosure is not limited thereto, and in another embodiment, the first and second chip identification pads (CP1, CP2) may be adjacent to each other, and the stack identification pad (CP0) may be spaced apart from the first and second chip identification pads (CP1, CP2). That is, another chip pad (CP) may be placed between the stack identification pad (CP0) and the first and second chip identification pads (CP1, CP2). Depending on the combination of power applied to each of the stack identification pad (CP0), the first chip identification pad (CP1), and the second chip identification pad (CP2), the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) and the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) may be distinguished from each other. This will be described below with further reference to FIG. 2C together with FIG. 2B.

Referring to FIGS. 2B and 2C, each of the stack identification pad (CP0), the first chip identification pad (CP1), and the second chip identification pad (CP2) may be in a powered state or a floating state. Here, the powered power may include various levels of voltage. For example, the powered power may be a power supply voltage (VDD). The powered state of the stack identification pad (CP0), the first chip identification pad (CP1), and the second chip identification pad (CP2) may be indicated by a logic value of '1', and the floating state may be indicated by a logic value of '0'.

Here, in order to distinguish/identify the first chip stack (210) and the second chip stack (220), the power supply states, i.e., the logic values, of the stack identification pads (CP0) of the first chip stack (210) and the stack identification pads (CP0) of the second chip stack (220) may be different from each other. In the present embodiment, the stack identification pads (CP0) of the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) may be in a power supply state, i.e., a state having a logic value of '1', and the stack identification pads (CP0) of the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) may be in a floating state, i.e., a state having a logic value of '0'. Since the stack identification pads (CP0) of the first to fourth semiconductor chips (221 to 224) of the second chip stack (220) are not supplied with power, the bonding wire connection may be omitted as illustrated. In the opposite case to the present embodiment, that is, the stack identification pads (CP0) of the first chip stack (210) may be in a floating state, and the stack identification pads (CP0) of the second chip stack (220) may be supplied with power. However, the present embodiment may be preferable in terms of reducing the length of the wire and improving signal transmission accordingly.

The stack identification pad (CP0) of the first chip stack (210) may be connected to the base layer (200) via the first wire (230). More specifically, the stack identification pads (CP0) of the first to fourth semiconductor chips (211 to 214) of the first chip stack (210) may be connected to each other via the first inter-chip wire (232), and the stack identification pad (CP0) of the first semiconductor chip (211) may be connected to the pad (202) of the base layer (200) via the first stack wire (234). The stack identification pad (CP0) of the second chip stack (220) may not be connected to the wire since it is in a floating state.

In addition, the combinations of four logic values expressed by the power supply states of the first and second chip identification pads (CP1, CP2) may be different from each other so that the first to fourth semiconductor chips (211 to 214) within the first chip stack (210) can be distinguished/identified. In the present embodiment, the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (211) at the bottom may be in a state in which power is supplied, i.e., in a state having a logic value of '1'. The second semiconductor chip (212) may be in a state in which any one of the first and second chip identification pads (CP1, CP2), for example, the first chip identification pad (CP1) is in a state in which power is supplied, i.e., in a state having a logic value of '1', and the second chip identification pad (CP2) is in a floating state, i.e., in a state having a logic value of '0'. The third semiconductor chip (213) may be in a state where one of the first and second chip identification pads (CP1, CP2) is powered, i.e., has a logic value of '1', and the first chip identification pad (CP1) may be in a floating state, i.e., has a logic value of '0'. The fourth semiconductor chip (214) may be in a state where the first and second chip identification pads (CP1, CP2) are in a floating state, i.e., have a logic value of '0'.

The first and second chip identification pads (CP1, CP2) of the first chip stack (210) may be connected to the base layer (200) via the first wire (230). More specifically, the second chip identification pad (CP2) of the third semiconductor chip (213), the first chip identification pad (CP1) of the second semiconductor chip (212), and the first chip identification pad (CP1) of the first semiconductor chip (211) may be connected to each other via the first inter-chip wire (232), and the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (211) may be connected to the pad (202) of the base layer (200) via the first stack wire (234). In particular, the first and second chip identification pads (CP1, CP2) connected to the first inter-chip wire (232) in the second and third semiconductor chips (212, 213) are arranged in a diagonal direction intersecting the first and second directions, and thus can be connected to each other through the first inter-chip wire (232) in the diagonal direction. In this case, since the first inter-chip wire (232) does not include a long wire that skips the semiconductor chips, the occurrence of electrical short defects due to wire interference within the first chip stack (210) can be reduced. Furthermore, since the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (211) that is closest to the base layer (200) are connected to the first wire (230), while the first wire (230) is not connected to the first and second chip identification pads (CP1, CP2) of the fourth semiconductor chip (214) that is farthest from the base layer (200), it is possible to reduce the length of the wire used in the first chip stack (210) and improve the signal transmission characteristics accordingly.

Similarly, in order for the first to fourth semiconductor chips (221 to 224) within the second chip stack (220) to be distinguished/identified, the combinations of four logic values expressed by the power supply states of the first and second chip identification pads (CP1, CP2) may be different from each other. In the present embodiment, the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (221) at the lowermost position may be in a state in which power is supplied, i.e., in a state having a logic value of '1'. The second semiconductor chip (222) may be in a state in which any one of the first and second chip identification pads (CP1, CP2), for example, the first chip identification pad (CP1) is in a state in which power is supplied, i.e., in a state having a logic value of '1', and the second chip identification pad (CP2) is in a floating state, i.e., in a state having a logic value of '0'. The third semiconductor chip (223) may be in a state where one of the first and second chip identification pads (CP1, CP2) is powered, i.e., has a logic value of '1', and the first chip identification pad (CP1) may be in a floating state, i.e., has a logic value of '0'. The fourth semiconductor chip (224) may be in a state where the first and second chip identification pads (CP1, CP2) are in a floating state, i.e., have a logic value of '0'.

The first and second chip identification pads (CP1, CP2) of the second chip stack (220) may be connected to the base layer (200) via a second wire (240). More specifically, the second chip identification pad (CP2) of the third semiconductor chip (223), the first chip identification pad (CP1) of the second semiconductor chip (222), and the first chip identification pad (CP1) of the first semiconductor chip (221) may be connected to each other via a second inter-chip wire (242), and the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (221) may be connected to the pad (202) of the base layer (200) via a second stack wire (244). In particular, the first and second chip identification pads (CP1, CP2) connected to the second inter-chip wire (242) in the second and third semiconductor chips (222, 223) are arranged in a diagonal direction intersecting the first and second directions, and thus can be connected to each other through the second inter-chip wire (242) in the diagonal direction. In this case, since the second inter-chip wire (242) does not include a long wire that skips the semiconductor chips, the occurrence of electrical short defects due to wire interference within the second chip stack (220) can be reduced. Furthermore, since the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (221) that is closest to the base layer (200) are connected to the second wire (240), while the second wire (240) is not connected to the first and second chip identification pads (CP1, CP2) of the fourth semiconductor chip (224) that is farthest from the base layer (200), it is possible to reduce the length of the wire used in the second chip stack (240) and improve the signal transmission characteristics accordingly. Unlike the first inter-chip wire (232), the second inter-chip wire (242), and the first stack wire (234), the second stack wire (244) is a long wire that skips the first chip stack (210), but by having a structure in which the second chip stack (220) is protruded and stacked on the first chip stack (210), interference between the second stack wire (244) and the first wire (230) and electrical short-circuiting defects caused by it can also be prevented.

Meanwhile, the power supply status of the first and second chip identification pads (CP1, CP2) of the first chip stack (210) and the connection form of the first wire (230) accordingly, and the power supply status of the first and second chip identification pads (CP1, CP2) of the second chip stack (220) and the connection form of the second wire (240) accordingly are not limited to those illustrated. Assuming that power is applied to all of the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (211, 221) located at the bottom of the first and second chip stacks (210, 220), respectively, and that all of the first and second chip identification pads (CP1, CP2) of the fourth semiconductor chip (214, 224) located at the top of the first and second chip stacks (210, 220), respectively, are in a floating state, the power application state of the first and second chip identification pads (CP1, CP2) of the second and third semiconductor chips (212, 213, 222, 223) and the connection form of the first and second inter-chip wires (232, 242) accordingly can be modified in various ways. This will be exemplarily described with reference to FIG. 2D.

FIG. 2d is a diagram showing the power supply states of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to another embodiment of the present invention as logical values. In this diagram, wires connected to the stack identification pads and chip identification pads are also depicted in the form of arrows. The following description will focus on differences from the semiconductor package of FIGS. 2a to 2c described above.

Referring to FIG. 2D, unlike the aforementioned embodiment, power may be applied to the first chip identification pad (CP1) of the third semiconductor chip (213, 223) and power may be applied to the second chip identification pad (CP2) of the second semiconductor chip (212, 222). Accordingly, the first chip identification pad (CP1) of the third semiconductor chip (213, 223), the second chip identification pad (CP2) of the second semiconductor chip (212, 222), and the second chip identification pad (CP2) of the first semiconductor chip (211, 221) may be connected to each other by inter-chip wires. Each of the first and second chip identification pads (CP1, CP2) of the first semiconductor chip (211, 221) may be connected to the base layer via stack wires.

Although not illustrated, other embodiments may be possible. For example, the power supply state and wire connection state of the first and second chip identification pads (CP1, CP2) of the first chip stack (210) may be the same as in the embodiments of FIGS. 2b and 2c, and the power supply state and wire connection state of the first and second chip identification pads (CP1, CP2) of the second chip stack (220) may be the same as in the embodiment of FIG. 2d. Or, for example, the power supply state and wire connection state of the first and second chip identification pads (CP1, CP2) of the first chip stack (210) may be the same as in the embodiment of FIG. 2d, and the power supply state and wire connection state of the first and second chip identification pads (CP1, CP2) of the second chip stack (220) may be the same as in the embodiments of FIGS. 2b and 2c.

Meanwhile, in the embodiments of FIGS. 2A to 2D, the two chip stacks each include four semiconductor chips, but the present disclosure is not limited thereto. The two chip stacks may each include eight semiconductor chips, which will be described in more detail with reference to FIGS. 3A to 3E below.

Fig. 3a is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and Fig. 3b is a plan view of a portion of the semiconductor package of Fig. 3a viewed from above. Fig. 3c is a diagram showing the stack identification pads of a plurality of semiconductor chips included in the semiconductor package of Figs. 3a and 3b and the power supply states of the chip identification pads as logical values. The differences from the above-described embodiments will be described mainly.

First, referring to FIGS. 3A and 3B, the semiconductor package of the present embodiment includes a base layer (300), a first chip stack (310) formed on one surface of the base layer (300) and including a plurality of semiconductor chips (311 to 318), a first wire (330) connecting the first chip stack (310) and the base layer (300) while connecting the plurality of semiconductor chips (311 to 318) to each other, a second chip stack (320) formed on the first chip stack (310) and including a plurality of semiconductor chips (321 to 328), a second wire (340) connecting the second chip stack (320) and the base layer (300) while connecting the plurality of semiconductor chips (321 to 328) to each other, an external connection terminal (350) formed on the other surface of the base layer (300), and a first and second chip stacks (310, 320) covering the first and second chip stacks. It may include a molding layer (360).

The first chip stack (310) may include eight semiconductor chips, i.e., first to eighth, (311 to 318), which are vertically stacked on one surface of the base layer (300). The first to eighth semiconductor chips (311 to 318) may be attached to the upper surfaces of the base layer (300) and the first to seventh semiconductor chips (311 to 317) positioned directly below the first to eighth semiconductor chips (311 to 318), respectively, by an adhesive layer (AL) formed on the lower surface thereof.

A plurality of chip pads (CP) may be arranged on the upper surface of each of the first to eighth semiconductor chips (311 to 318). The plurality of chip pads (CP) may be arranged on one edge region of each of the first to eighth semiconductor chips (311 to 318) in a first direction. The first to eighth semiconductor chips (311 to 318) may be offset-stacked so that all of the chip pads (CP) are exposed. One side surface and the other side surface of the first to eighth semiconductor chips (311 to 318) in the second direction may be substantially aligned with each other.

In each of the first to eighth semiconductor chips (311 to 318), a plurality of chip pads (CP) may be arranged in a row along a second direction intersecting the first direction. In particular, some of the plurality of chip pads (CP) may function as stack identification pads (CP0) for distinguishing between the first chip stack (310) and the second chip stack (320), and chip identification pads (CP1, CP2, CP3) for identifying the first to eighth semiconductor chips (311 to 318) included in the first chip stack (310), respectively. The arrangement of the stack identification pad (CP0) and the chip identification pads (CP1, CP2, CP3) in the first chip stack (310), the power supply, and the connection thereof with the first wire (330) will be described later.

The first wire (330) can provide a connection between the first to eighth semiconductor chips (311 to 318) included in the first chip stack (310) and a connection between the first chip stack (310) and the base layer (300). For convenience of explanation, a wire that connects chip pads (CP) between the first to eighth semiconductor chips (311 to 318) among the first wires (330) is referred to as a first inter-chip wire (332), and a wire that connects the chip pad (CP) of the first semiconductor chip (311) located at the lowest position in the first chip stack (310) and the pad (302) of the base layer (300) is referred to as a first stack wire (334).

The second chip stack (320) may include eight semiconductor chips, i.e., first to eighth semiconductor chips (321 to 328), which are vertically stacked on the chip stack (310). The first to eighth semiconductor chips (321 to 328) may be attached to the upper surface of the eighth semiconductor chip (318) of the first chip stack (310) and the upper surfaces of the first to seventh semiconductor chips (321 to 327) positioned directly below the first to eighth semiconductor chips (321 to 328) by an adhesive layer (AL) formed on the lower surface thereof.

A plurality of chip pads (CP) may be arranged on the upper surface of each of the first to eighth semiconductor chips (321 to 328). The plurality of chip pads (CP) may be arranged on one edge region of each of the first to eighth semiconductor chips (321 to 328) in a first direction. The first to eighth semiconductor chips (321 to 328) may be offset-stacked so that all of the chip pads (CP) are exposed. In the second direction, one side surface and the other side surface of the first to eighth semiconductor chips (321 to 328) may be substantially aligned with each other, and further, one side surface and the other side surface of the first to eighth semiconductor chips (311 to 318) may be substantially aligned with each other.

In each of the first to eighth semiconductor chips (321 to 328), a plurality of chip pads (CP) may be arranged in a row along a second direction intersecting the first direction. In particular, some of the plurality of chip pads (CP) may function as stack identification pads (CP0) for distinguishing between the first chip stack (210) and the second chip stack (220), and chip identification pads (CP1, CP2, CP3) for identifying the first to eighth semiconductor chips (321 to 328) included in the second chip stack (320), respectively. The arrangement of the stack identification pad (CP0) and the chip identification pads (CP1, CP2, CP3) in the second chip stack (320), the power supply, and the connection with the second wire (340) accordingly will be described later.

The second wire (340) can provide a connection between the first to eighth semiconductor chips (321 to 328) included in the second chip stack (320) and a connection between the second chip stack (320) and the base layer (300). For convenience of explanation, among the second wires (340), a wire that connects the chip pads (CP) between the first to eighth semiconductor chips (321 to 328) to each other is referred to as a second inter-chip wire (342), and a wire that connects the chip pad (CP) of the first semiconductor chip (321) located at the bottom and the pad (302) of the base layer (300) is referred to as a second stack wire (344).

In the semiconductor package as described above, since the first chip stack (310) includes 2 ^{to 3} semiconductor chips (311 to 318), each of the first to eighth semiconductor chips (311 to 318) may include at least three chip identification pads to distinguish/identify them within the first chip stack (310). For example, each of the first to eighth semiconductor chips (311 to 318) may include first to third chip identification pads (CP1, CP2, CP3). This is because 2 to ³ state expressions are possible by using three chip identification pads. Furthermore, in order to distinguish/identify the first chip stack (310) and the second chip stack (320), each of the first to eighth semiconductor chips (311 to 318) of the first chip stack (310) may include one stack identification pad (CP0). In addition, since the second chip stack (320) includes 2 ^{to 3} semiconductor chips (321 to 328), each of the first to eighth semiconductor chips (321 to 328) may include three, i.e., first to third chip identification pads (CP1, CP2, CP3), for distinguishing/identifying them within the second chip stack (320). Furthermore, in order to distinguish/identify the second chip stack (320) from the first chip stack (310), each of the first to eighth semiconductor chips (321 to 328) of the second chip stack (320) may include one stack identification pad (CP0).

In the first chip stack (310) and the second chip stack (320), the stack identification pad (CP0), the first chip identification pad (CP1), the second chip identification pad (CP2), and the third chip identification pad (CP3) may be substantially aligned with each other along the first direction. In addition, the stack identification pad (CP0), the first chip identification pad (CP1), the second chip identification pad (CP2), and the third chip color-coded pad (CP3) may be arranged adjacent to each other in the second direction. However, the present disclosure is not limited thereto, and in another embodiment, the first to third chip identification pads (CP1, CP2, CP3) may be adjacent to each other, and the stack identification pad (CP0) may be spaced apart from the first to third chip identification pads (CP1, CP2, CP3). That is, another chip pad (CP) may be arranged between the stack identification pad (CP0) and the first to third chip identification pads (CP1, CP2, CP3). Depending on the combination of power applied to each of the stack identification pad (CP0), the first chip identification pad (CP1), the second chip identification pad (CP2), and the third chip identification pad (CP3), the first to eighth semiconductor chips (311 to 318) of the first chip stack (310) and the first to eighth semiconductor chips (321 to 328) of the second chip stack (320) can be distinguished from each other. This will be described below with further reference to FIG. 3C together with FIG. 3B.

Referring to FIGS. 3B and 3C, in order to distinguish/identify the first chip stack (310) and the second chip stack (320), the power supply states, i.e., the logic values, of the stack identification pads (CP0) of the first chip stack (310) and the stack identification pads (CP0) of the second chip stack (320) may be different from each other. In the present embodiment, the stack identification pads (CP0) of the first to eighth semiconductor chips (311 to 318) of the first chip stack (310) may be in a power supply state, i.e., a state having a logic value of '1', and the stack identification pads (CP0) of the first to eighth semiconductor chips (321 to 328) of the second chip stack (320) may be in a floating state, i.e., a state having a logic value of '0'. Since the stack identification pads (CP0) of the first to eighth semiconductor chips (321 to 328) of the second chip stack (320) are not supplied with power, bonding wire connection can be omitted as shown.

The stack identification pad (CP0) of the first chip stack (310) may be connected to the base layer (300) via the first wire (330). More specifically, the stack identification pads (CP0) of the first to eighth semiconductor chips (311 to 318) of the first chip stack (310) may be connected to each other via the first inter-chip wire (332), and the stack identification pad (CP0) of the first semiconductor chip (311) may be connected to the pad (302) of the base layer (300) via the first stack wire (334). The stack identification pad (CP0) of the second chip stack (320) may be in a floating state and thus may not be connected to the wire.

In addition, the combinations of eight logic values expressed by the power supply states of the first to third chip identification pads (CP1, CP2, CP3) may be different from each other so that the first to eighth semiconductor chips (311 to 318) within the first chip stack (310) can be distinguished/identified. In the present embodiment, all of the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311) at the bottom may be in a state in which power is supplied. Each of the second to fourth semiconductor chips (312, 313, 314) may have two selected ones of the first to third chip identification pads (CP1, CP2, CP3) being in a state in which power is supplied, and the other one may be in a floating state. In particular, in order to form a short wire that does not skip chips in a diagonal direction and/or a straight direction, power may be applied to the first to third chip identification pads (CP1, CP2, CP3) of the second to fourth semiconductor chips (312, 313, 314) so that the floating ones are arranged in a diagonal direction. For example, the first and second chip identification pads (CP1, CP2) of the second semiconductor chip (312) may be supplied with power, the first and third chip identification pads (CP1, CP3) of the third semiconductor chip (313) may be supplied with power, and the second and third chip identification pads (CP2, CP3) of the fourth semiconductor chip (314) may be supplied with power. In this case, the third chip identification pad (CP3) of the second semiconductor chip (312), the second chip identification pad (CP2) of the third semiconductor chip (313), and the first chip identification pad (CP1) of the fourth semiconductor chip (314) may be arranged in a diagonal direction in a floating state (see dotted line ①). Each of the fifth to seventh semiconductor chips (315, 316, 317) may be in a state where one selected from the first to third chip identification pads (CP1, CP2, CP3) is supplied with power. In particular, in order to form a short wire that does not skip chips in a diagonal direction and/or a straight direction, those of the first to third chip identification pads (CP1, CP2, CP3) of the fifth to seventh semiconductor chips (315, 316, 317) to which power is supplied may be arranged in a diagonal direction. For example, the third chip identification pad (CP3) of the fifth semiconductor chip (315) may be in a state where power is supplied, the second chip identification pad (CP2) of the sixth semiconductor chip (316) may be in a state where power is supplied, and the first chip identification pad (CP1) of the seventh semiconductor chip (317) may be in a state where power is supplied (see dotted line ②). The first to third chip identification pads (CP1, CP2, CP3) of the eighth semiconductor chip (318) may be in a floating state.

The first to third chip identification pads (CP1, CP2, CP3) of the first chip stack (310) may be connected to the base layer (300) via a first wire (330). More specifically, the first chip identification pad (CP1) of the seventh semiconductor chip (317), the second chip identification pad (CP2) of the sixth semiconductor chip (316), the third chip identification pad (CP3) of the fifth semiconductor chip (315), the second chip identification pad (CP2) of the fourth semiconductor chip (314), the first chip identification pad (CP1) of the third semiconductor chip (313), the first chip identification pad (CP1) of the second semiconductor chip (312), and the first chip identification pad (CP1) of the first semiconductor chip (311) may be connected to each other via a first inter-chip wire (332). Additionally, the third chip identification pad (CP3) of the fourth semiconductor chip (314), the third chip identification pad (CP3) of the third semiconductor chip (313), the second chip identification pad (CP2) of the second semiconductor chip (312), and the second chip identification pad (CP2) of the first semiconductor chip (311) may be connected to each other via the first inter-chip wire (332). The first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311) may be connected to the pad (302) of the base layer (300) via the first stack wire (334).

Similarly, the combinations of eight logic values expressed by the power supply states of the first to third chip identification pads (CP1, CP2, CP3) may be different from each other so that the first to eighth semiconductor chips (321 to 328) within the second chip stack (320) can be distinguished/identified. In the present embodiment, the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (321) at the bottom may be in a power supply state. Each of the second to fourth semiconductor chips (322, 323, 324) may have two selected ones of the first to third chip identification pads (CP1, CP2, CP3) being powered on, and the other one being in a floating state. In particular, in order to form a short wire that does not skip chips in a diagonal direction and/or a straight direction, power may be applied to the first to third chip identification pads (CP1, CP2, CP3) of the second to fourth semiconductor chips (322, 323, 324) so that the floating ones are arranged in a diagonal direction. For example, the first and second chip identification pads (CP1, CP2) of the second semiconductor chip (322) may be supplied with power, the first and third chip identification pads (CP1, CP3) of the third semiconductor chip (323) may be supplied with power, and the second and third chip identification pads (CP2, CP3) of the fourth semiconductor chip (324) may be supplied with power. In this case, the third chip identification pad (CP3) of the second semiconductor chip (322), the second chip identification pad (CP2) of the third semiconductor chip (323), and the first chip identification pad (CP1) of the fourth semiconductor chip (324) may be arranged in a diagonal direction in a floating state (see dotted line ③). Each of the fifth to seventh semiconductor chips (325, 326, 327) may be in a state where one selected from the first to third chip identification pads (CP1, CP2, CP3) is supplied with power. In particular, in order to form a short wire that does not skip chips in a diagonal direction and/or a straight direction, those of the first to third chip identification pads (CP1, CP2, CP3) of the fifth to seventh semiconductor chips (325, 326, 327) to which power is supplied may be arranged in a diagonal direction. For example, the third chip identification pad (CP3) of the fifth semiconductor chip (325) may be in a state where power is supplied, the second chip identification pad (CP2) of the sixth semiconductor chip (326) may be in a state where power is supplied, and the first chip identification pad (CP1) of the seventh semiconductor chip (327) may be in a state where power is supplied (see dotted line ④). The first to third chip identification pads (CP1, CP2, CP3) of the eighth semiconductor chip (328) may be in a floating state.

The first to third chip identification pads (CP1, CP2, CP3) of the second chip stack (320) may be connected to the base layer (300) via a second wire (340). More specifically, the first chip identification pad (CP1) of the seventh semiconductor chip (327), the second chip identification pad (CP2) of the sixth semiconductor chip (326), the third chip identification pad (CP3) of the fifth semiconductor chip (325), the second chip identification pad (CP2) of the fourth semiconductor chip (324), the first chip identification pad (CP1) of the third semiconductor chip (323), the first chip identification pad (CP1) of the second semiconductor chip (322), and the first chip identification pad (CP1) of the first semiconductor chip (321) may be connected to each other via a second inter-chip wire (342). Additionally, the third chip identification pad (CP3) of the fourth semiconductor chip (324), the third chip identification pad (CP3) of the third semiconductor chip (323), the second chip identification pad (CP2) of the second semiconductor chip (322), and the second chip identification pad (CP2) of the first semiconductor chip (321) may be connected to each other via a second inter-chip wire (342). The first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (321) may be connected to the pad (302) of the base layer (300) via a second stack wire (344).

Meanwhile, the power supply state of the first to third chip identification pads (CP1, CP2, CP3) of the first chip stack (310) and the connection form of the first wire (330) accordingly, and the power supply state of the first to third chip identification pads (CP1, CP2, CP3) of the second chip stack (320) and the connection form of the second wire (340) accordingly are not limited to those illustrated. Power is applied to all of the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311, 321) located at the lowermost portions of the first and second chip stacks (310, 320), and power is applied to two selected from the first to third chip identification pads (CP1, CP2, CP3) of the second to fourth semiconductor chips (312 to 314, and 322 to 324), assuming that the two selected from each of the second to fourth semiconductor chips (312 to 314, and 322 to 324) are different from each other, and power is applied to one selected from the first to third chip identification pads (CP1, CP2, CP3) of the fifth to seventh semiconductor chips (315 to 317, and 325 to 327), and to one selected from the fifth to seventh semiconductor chips (315 to 317, and 325 to 327), and to one selected from the fifth to seventh semiconductor chips (315 to 317, and 325 to 327). Assuming that the selected ones are different from each other, power is applied, and all of the first to third chip identification pads (CP1, CP2, CP3) of the eighth semiconductor chips (318, 328) located at the top of the first and second chip stacks (310, 320) are in a floating state, the power application state of the first to third chip identification pads (CP1, CP2, CP3) of the second to seventh semiconductor chips (312 to 317, and 322 to 327) and the connection form of the first and second inter-chip wires (332, 342) according to the power application state can be variously modified. This will be exemplarily described with reference to FIGS. 3d to 3f.

FIGS. 3D to 3F are diagrams showing the power supply states of the stack identification pads and chip identification pads of a plurality of semiconductor chips included in a semiconductor package according to other embodiments of the present invention as logical values. In these drawings, wires connected to the stack identification pads and chip identification pads are depicted in the form of arrows. The differences from the semiconductor package of FIGS. 3A to 3C described above will be mainly explained.

Referring to FIG. 3d, the second and third chip identification pads (CP2, CP3) of the second semiconductor chip (312, 322) may be supplied with power, the first and third chip identification pads (CP1, CP3) of the third semiconductor chip (313, 323) may be supplied with power, and the first and second chip identification pads (CP2, CP3) of the fourth semiconductor chip (314, 324) may be supplied with power. In this case, the first chip identification pad (CP1) of the second semiconductor chip (312, 322), the second chip identification pad (CP2) of the third semiconductor chip (313, 323), and the third chip identification pad (CP3) of the fourth semiconductor chip (314, 324) in a floating state may be arranged in a diagonal direction (see dotted lines ① and ③). However, this diagonal direction may be opposite to that illustrated in FIG. 3c.

The third chip identification pad (CP3) of the fifth semiconductor chip (315, 325) may be powered, the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326) may be powered, and the first chip identification pad (CP1) of the seventh semiconductor chip (317, 327) may be powered, and these may be arranged in a diagonal direction (see dotted lines ② and ④). This diagonal direction may be the same as that illustrated in Fig. 3c.

In this case, the first chip identification pad (CP1) of the seventh semiconductor chip (317, 327), the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326), the third chip identification pad (CP3) of the fifth semiconductor chip (315, 325), the second chip identification pad (CP2) of the fourth semiconductor chip (314, 324), the third chip identification pad (CP3) of the third semiconductor chip (313, 323), the third chip identification pad (CP3) of the second semiconductor chip (312, 322), and the third chip identification pad (CP3) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Additionally, the first chip identification pad (CP1) of the fourth semiconductor chip (314, 324), the first chip identification pad (CP1) of the third semiconductor chip (313, 323), the second chip identification pad (CP2) of the second semiconductor chip (312, 322), and the second chip identification pad (CP2) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Each of the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311, 321) may be connected to the base layer via stack wires.

Referring to FIG. 3e, the second and third chip identification pads (CP2, CP3) of the second semiconductor chip (312, 322) may be supplied with power, the first and third chip identification pads (CP1, CP3) of the third semiconductor chip (313, 323) may be supplied with power, and the first and second chip identification pads (CP2, CP3) of the fourth semiconductor chip (314, 324) may be supplied with power. In this case, the first chip identification pad (CP1) of the second semiconductor chip (312, 322) in a floating state, the second chip identification pad (CP2) of the third semiconductor chip (313, 323), and the third chip identification pad (CP3) of the fourth semiconductor chip (314, 324) may be arranged in a diagonal direction (see dotted lines ① and ③). However, this diagonal direction may be opposite to that illustrated in FIG. 3c.

The first chip identification pad (CP1) of the fifth semiconductor chip (315, 325) may be powered, the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326) may be powered, and the third chip identification pad (CP3) of the seventh semiconductor chip (317, 327) may be powered, and these may be arranged in a diagonal direction (see dotted lines ② and ④). This diagonal direction may be opposite to that illustrated in Fig. 3c.

In this case, the third chip identification pad (CP3) of the seventh semiconductor chip (317, 327), the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326), the first chip identification pad (CP1) of the fifth semiconductor chip (315, 325), the second chip identification pad (CP2) of the fourth semiconductor chip (314, 324), the third chip identification pad (CP3) of the third semiconductor chip (313, 323), the third chip identification pad (CP3) of the second semiconductor chip (312, 322), and the third chip identification pad (CP3) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Additionally, the first chip identification pad (CP1) of the fourth semiconductor chip (314, 324), the first chip identification pad (CP1) of the third semiconductor chip (313, 323), the second chip identification pad (CP2) of the second semiconductor chip (312, 322), and the second chip identification pad (CP2) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Each of the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311, 321) may be connected to the base layer via stack wires.

Referring to FIG. 3f, the first and second chip identification pads (CP1, CP2) of the second semiconductor chip (312, 322) may be supplied with power, the first and third chip identification pads (CP1, CP3) of the third semiconductor chip (313, 323) may be supplied with power, and the second and third chip identification pads (CP2, CP3) of the fourth semiconductor chip (314, 324) may be supplied with power. In this case, the third chip identification pad (CP3) of the second semiconductor chip (312, 322) in a floating state, the second chip identification pad (CP2) of the third semiconductor chip (313, 323), and the first chip identification pad (CP1) of the fourth semiconductor chip (314, 324) may be arranged in a diagonal direction (see dotted lines ① and ③). However, this diagonal direction may be the same as that illustrated in FIG. 3c.

The first chip identification pad (CP1) of the fifth semiconductor chip (315, 325) may be powered, the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326) may be powered, and the third chip identification pad (CP3) of the seventh semiconductor chip (317, 327) may be powered, and these may be arranged in a diagonal direction (see dotted lines ② and ④). This diagonal direction may be opposite to that illustrated in Fig. 3c.

In this case, the third chip identification pad (CP3) of the seventh semiconductor chip (317, 327), the second chip identification pad (CP2) of the sixth semiconductor chip (316, 326), the first chip identification pad (CP1) of the fifth semiconductor chip (315, 325), the second chip identification pad (CP2) of the fourth semiconductor chip (314, 324), the first chip identification pad (CP1) of the third semiconductor chip (313, 323), the first chip identification pad (CP1) of the second semiconductor chip (312, 322), and the first chip identification pad (CP3) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Additionally, the third chip identification pad (CP3) of the fourth semiconductor chip (314, 324), the third chip identification pad (CP3) of the third semiconductor chip (313, 323), the second chip identification pad (CP2) of the second semiconductor chip (312, 322), and the second chip identification pad (CP2) of the first semiconductor chip (311, 321) may be connected to each other by inter-chip wires. Each of the first to third chip identification pads (CP1, CP2, CP3) of the first semiconductor chip (311, 321) may be connected to the base layer via stack wires.

Although not illustrated, other embodiments may be possible. For example, the power supply state and wire connection state of the first to third chip identification pads (CP1, CP2, CP3) of the first chip stack (310) may be the same as any one of the embodiments of FIGS. 3b and 3c, 3d, 3e, and 3f, and the power supply state and wire connection state of the first to third chip identification pads (CP1, CP2, CP3) of the second chip stack (320) may be the same as any one of the embodiments of FIGS. 3b and 3c, 3d, 3e, and 3f, while being different from the first chip stack (310).

The above embodiments have described the arrangement of stack identification pads and chip identification pads, power supply, and wire connection in a case where a semiconductor package includes two chip stacks, and each of the two chip stacks includes four or eight chip stacks; however, the present disclosure is not limited thereto. This concept is further expanded as follows.

The semiconductor package of the present embodiment may include a base layer and first and second chip stacks formed on the base layer.

Each of the first and second chip stacks may include a plurality of semiconductor chips having chip pads arranged in a row along a second direction at one edge region in the first direction. The plurality of semiconductor chips may be offset-stacked in a direction away from the one side in the first direction so that the chip pads are exposed. Furthermore, one side in the first direction of the semiconductor chip at the bottom of the second chip stack may protrude in a direction opposite to the offset direction more than one side in the first direction of the semiconductor chip at the top of the first chip stack.

The chip pad may include a stack identification pad for identifying a first chip stack and a second chip stack, and a chip identification pad for identifying a semiconductor chip included in each of the first chip stack and the second chip stack. Each semiconductor chip may include one stack identification pad. The stack identification pads may be aligned substantially in a line along a first direction. When each of the first and second chip stacks includes ^2N-1 semiconductor chips, each semiconductor chip may include N-1 chip identification pads. When the N-1 chip identification pads are sequentially referred to as first to N-1-th chip identification pads from one side of each semiconductor chip in the second direction, n-th chip identification pads (wherein n is a natural number greater than or equal to 1 and less than or equal to N-1) of the plurality of semiconductor chips may be aligned substantially in a line along the first direction. The 2 ^N-1 semiconductor chips included in each of the first and second chip stacks may be referred to as first to K-th semiconductor chips, depending on their distance from the base layer (where K is equal to 2 ^N-1 ).

A stack identification pad of a semiconductor chip included in one of the first and second chip stacks, for example, a stack identification pad of the first chip stack, may be in a powered state, and a stack identification pad of a semiconductor chip included in the other, for example, a stack identification pad of the second chip stack, may be in a floating state. Accordingly, the stack identification pads of the first to Kth semiconductor chips of the first chip stack are connected to each other via an inter-chip wire, and the stack identification pad of the first semiconductor chip of the first chip stack may be connected to a base layer via the stack wire.

In each of the first and second chip stacks, the first to Kth semiconductor chips can be distinguished by a combination of the power-on states and floating states of their N-1 chip identification pads. That is, the combinations of the power-on states and floating states of the chip identification pads of the first to Kth semiconductor chips can be different from each other.

All of the chip identification pads of the first semiconductor chip may be powered, and all of the chip identification pads of the K-th semiconductor chip may be floating. Some of the chip identification pads of the second to K-1th semiconductor chips may be powered, and the remaining may be floating. In each of the first and second chip stacks, the chip identification pads of the first semiconductor chip may be connected to the base layer via stack wires. Furthermore, in each of the first and second chip stacks, the chip identification pads between the first to K-1th semiconductor chips to which power is applied may be connected to each other via inter-chip wires.

Here, the arrangement of the chip identification pads to which power is applied in the second to K-1th semiconductor chips located between the first semiconductor chip and the Kth semiconductor chip can be performed so that a long inter-chip wire that skips the semiconductor chips does not occur. To this end, the chip identification pads to which power is applied and/or the chip identification pads in a floating state in the second to K-1th semiconductor chips can be arranged in a diagonal direction intersecting the first and second directions. In this case, the inter-chip wire that connects to the nth chip identification pad of the kth semiconductor chip (wherein k is a natural number greater than or equal to 1 and less than or equal to K-1) among the first to K-1th semiconductor chips can be connected to any one of the n-1th chip identification pad, the nth identification pad, and the n+1th chip identification pad of a semiconductor chip adjacent to the kth semiconductor chip, for example, the k-1th and/or k+1th semiconductor chip. That is, the inter-chip wire can be formed as a short wire that does not skip semiconductor chips by connecting chip identification pads of adjacent semiconductor chips to each other in a diagonal direction or a first direction.

Furthermore, the second to K-1 semiconductor chips may be grouped into one or more groups, and the number of chip identification pads to which power is applied in each semiconductor chip belonging to a specific group may sequentially decrease according to the distance between the group and the first semiconductor chip. Specific grouping methods have been exemplarily described in the above embodiments. For example, when each of the first and second chip stacks includes the first to fourth semiconductor chips, there is one group including the second and third semiconductor chips, and each of the second and third semiconductor chips in the group may receive power to one chip identification pad. Here, it has been described that one chip identification pad to which power is applied may be arranged in a diagonal direction. Alternatively, for example, if each of the first and second chip stacks includes first to eighth semiconductor chips, there may be a first group including second and fourth semiconductor chips and a second group including fifth to seventh semiconductor chips, and each of the second to fourth semiconductor chips of the first group may be powered by two chip identification pads, and each of the fifth to seventh semiconductor chips of the second group may be powered by one chip identification pad. Here, it has already been described that one chip identification pad of a floating state of the second to fourth semiconductor chips may be arranged in a diagonal direction, and one chip identification pad to which power is supplied of the fifth to seventh semiconductor chips may be arranged in a diagonal direction.

While the technical concept of the present invention has been specifically described in accordance with the above preferred embodiments, it should be noted that the above-described embodiments are intended for illustrative purposes only and are not intended to be limiting. Furthermore, those skilled in the art will readily appreciate that various embodiments are possible within the scope of the technical concept of the present invention.

200: Base layer 210: First chip stack
220: Second chip stack 230: First wire
240: Second wire 250: External connection electrode
260: Molding layer

Claims (23)

base layer;
A chip stack laminated on the base layer;
inter-chip wires; and
comprising first and second stack wires,
The chip stack includes first to fourth semiconductor chips sequentially offset-stacked in a first direction so that chip pads are exposed,
The above chip pads include a first chip identification pad and a second chip identification pad;
The first chip identification pads and the second chip identification pads of the first to fourth semiconductor chips are each aligned in the first direction,
The first stack wire connects the first chip identification pad of the first semiconductor chip to the base layer, and the second stack wire connects the second chip identification pad to the base layer.
The first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip are electrically connected to each other by the inter-chip wires,
The first and second stack wires and the inter-chip wires are connected to one of the chip pads of the adjacent semiconductor chips without skipping the adjacent chip pads in the first direction,
A semiconductor package wherein the second chip identification pad of the second semiconductor chip, the first chip identification pad of the third semiconductor chip, and the first and second chip identification pads of the fourth semiconductor chip are not connected to the inter-chip wires and are electrically floating.
delete delete In the first paragraph,
A semiconductor package in which, within each of the first to fourth semiconductor chips, the chip identification pads are arranged adjacent to each other.
In the first paragraph,
A semiconductor package wherein each of the first to fourth semiconductor chips further includes a stack identification pad adjacent to one of the chip identification pads.
base layer;
A first chip stack and a second chip stack stacked on the base layer, each of the first and second chip stacks including first to eighth semiconductor chips that are offset-stacked so that chip pads are exposed, the chip pads including stack identification pads and chip identification pads;
First inter-chip wires connecting the chip identification pads of one of the first to seventh semiconductor chips of the first chip stack to the chip identification pads of another semiconductor chip adjacent to the one of the first to seventh semiconductor chips;
First stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer;
Second inter-chip wires connecting the chip identification pads of one of the first to seventh semiconductor chips of the second chip stack to the chip identification pads of another semiconductor chip adjacent to the one of the first to seventh semiconductor chips; and
comprising second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer;
The first, second, and third chip identification pads of the first semiconductor chip of the first chip stack are respectively connected to the base layer through the first stack wires,
In the above first chip stack,
The first inter-chip wires connect two selected ones of the first to third chip identification pads of the second to fourth semiconductor chips and one selected one of the first to third chip identification pads of the fifth to seventh semiconductor chips,
The combination of the two selected chip identification pads of the second semiconductor chip, the combination of the two selected chip identification pads of the third semiconductor chip, and the combination of the two selected chip identification pads of the fourth semiconductor chip are different from each other, and
The selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other,
The first, second, and third chip identification pads of the first semiconductor chip of the second chip stack are respectively connected to the base layer through the second stack wires,
In the second chip stack,
The second inter-chip wires connect two selected ones of the first to third chip identification pads of the second to fourth semiconductor chips, and one selected one of the first to third chip identification pads of the fifth to seventh semiconductor chips,
The combination of the two selected chip identification pads of the second semiconductor chip, the combination of the two selected chip identification pads of the third semiconductor chip, and the combination of the selected chip identification pads of the fourth semiconductor chip are different from each other, and
The selected one chip identification pad of the fourth semiconductor chip, the selected one chip identification pad of the fifth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different semiconductor packages.
In paragraph 6,
A third inter-chip wire connecting the stack identification pad of one of the first to eight semiconductor chips within the first chip stack to the stack identification pad of another semiconductor chip adjacent to the one semiconductor chip; and
A semiconductor package further comprising a third stack wire connecting the stack identification pad of the first semiconductor chip of the first chip stack to the base layer.
In paragraph 7,
A semiconductor package wherein the first to eighth stack identification pads of the second chip stack are not connected to the third inter-chip wires.
In paragraph 6,
In the first to eighth semiconductor chips of each of the first and second chip stacks,
The above chip identification pads are adjacent to each other in a semiconductor package.
In paragraph 6,
In the first to eighth semiconductor chips of each of the first and second chip stacks,
A semiconductor package wherein the stack identification pad is adjacent to one of the chip identification pads.
base layer;
A first chip stack and a second chip stack stacked on the base layer, the first and second chip stacks each including first to fourth semiconductor chips that are offset-stacked so that chip pads are exposed, the chip pads including stack identification pads and chip identification pads;
First inter-chip wires connecting the chip identification pads of one of the first to fourth semiconductor chips of the first chip stack to the chip identification pads of another semiconductor chip adjacent to the one semiconductor chip;
First stack wires connecting the chip identification pads of the first semiconductor chip of the first chip stack and the base layer;
Second inter-chip wires connecting the chip identification pads of one of the first to fourth semiconductor chips of the second chip stack to the chip identification pads of another semiconductor chip adjacent to the one semiconductor chip; and
comprising second stack wires connecting the chip identification pads of the first semiconductor chip of the second chip stack to the base layer;
The above chip identification pads include first and second chip identification pads,
The first and second chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer through the first stack wires,
In the first chip stack, the first inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
The first and second chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer through the second stack wires,
In the second chip stack, the second inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip,
In the first chip stack, the first inter-chip wires are:
Supplying power to the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
Supplying power to the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
A semiconductor package that supplies power to the third semiconductor chip through the second chip identification pad of the third semiconductor chip.
In Article 11,
A third inter-chip wire connecting the stack identification pad of one of the first to fourth semiconductor chips of the first chip stack to the stack identification pad of another adjacent semiconductor chip; and
A semiconductor package further comprising a third stack wire connecting the stack identification pad of the first semiconductor chip of the first chip stack and the base layer.
In Article 12,
A semiconductor package in which the stack identification pads of the first to fourth semiconductor chips of the second chip stack are not connected to the third inter-chip wire.
In Article 12,
A semiconductor package in which the stack identification pads of the first to fourth semiconductor chips of the second chip stack are in a floating state.
In Article 12,
A semiconductor package in which the third inter-chip wires supply power to the first to fourth semiconductor chips of the first chip stack through the stack identification pads of the first to fourth semiconductor chips of the first chip stack.
In Article 11,
A semiconductor package in which the chip identification pads are arranged adjacent to each other in the first to fourth semiconductor chips of the first and second chip stacks, respectively.
In Article 11,
A semiconductor package in which the stack identification pads are arranged adjacent to one of the chip identification pads in the first to fourth semiconductor chips of each of the first and second chip stacks.
In Article 11,
In the second chip stack,
The above second inter-chip wires are:
Power is supplied to the first semiconductor chip through the first chip identification pad of the first semiconductor chip,
Power is supplied to the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and
A semiconductor package that provides power to the third semiconductor chip through the second chip identification pad of the third semiconductor chip.
delete delete delete delete delete