KR102903506B1 - Semiconductor memory device and driviing method thereof - Google Patents

Abstract

According to one embodiment of the disclosed invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit connected to the plurality of word lines, a sense amplifier circuit connected to the plurality of bit lines, and a controller for generating signals applied to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of memory cells includes a first transistor having a gate node connected to a word line and one end connected to a bit line to store data in the memory cell, and a second transistor having a gate node connected to the other end of the first transistor and one end connected to the bit line and the other end connected to the word line to read data stored in the memory cell, wherein the first transistor and the second transistor may be configured as a four-terminal element including a back gate node.

Description

Semiconductor memory device and driving method thereof {SEMICONDUCTOR MEMORY DEVICE AND DRIVIING METHOD THEREOF}

The present invention relates to a semiconductor memory device and a driving method thereof, and more specifically, to a technology capable of improving the driving capability of a memory cell by using a back gate line of a transistor.

DRAM stands for "Dynamic Random Access Memory" and is a type of computer memory.

This DRAM is a form of RAM (random access memory) used in computers, primarily as main memory.

Additionally, DRAM is a memory device that temporarily stores data and allows for quick access, storing information needed while the CPU executes a program or processes data.

A conventional 1T 1C structure DRAM includes a memory cell composed of one transistor and one capacitor, and the transistor controls access to each memory cell.

These transistors are configured to control the flow of data between word lines and bit lines that connect to memory cells.

Additionally, the capacitor is configured to store data by accumulating charge, and the accumulated charge can be withdrawn through a device such as a flip-flop or register and provided to a CPU or other device.

DRAMs with this structure can implement relatively simple and miniaturized memory cells, but they have the disadvantage of having the charge of the charged capacitor gradually disappear over time and requiring a periodic refresh process.

In the case of a conventional memory device composed of one transistor and one capacitor, there is a problem that the charged charge leaks out over time as a memory device that depends on the charge state of the capacitor, and there is a problem that leakage current occurs.

In addition, in the case of DRAMs that include memory cells that are conventionally composed of two transistors, there is a problem that one more transistor is added compared to the conventional structure, and the layout area increases due to the increase in the number of wires.

In addition, in the case of memory cells based on back gate control according to the prior art, there is a problem in that a data rewriting operation is required after a read operation to read data, which causes power consumption.

In addition, since the memory cell based on back gate control according to the prior art shares charges between the capacitor of the bit line and the capacitor of the memory cell, there is a problem in that the sense amplifier cannot detect the voltage difference between the bit line and the complementary bit line if the size of the capacitor of the bit line is too large.

Republic of Korea Public Notice No. 10-2012-0022481 (Dynamic latch and data output device including the same) Republic of Korea Publication No. 10-2019-0175250 (Non-volatile memory device and its operating method)

Accordingly, a semiconductor memory device and a driving method thereof according to one embodiment of the disclosed invention are inventions created to solve the problems of the above-described prior art, and more specifically, the purpose is to provide a semiconductor memory device and a driving method thereof in which leakage current is minimized and driving ability is improved by controlling the driving ability of a transistor constituting a memory cell through a back gate line.

In addition, the purpose of the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention is to provide a semiconductor memory device and a driving method thereof having a reduced area by configuring a memory cell using two transistors, each transistor sharing a bit line and a word line.

In addition, the purpose of the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention is to provide a semiconductor memory device and the driving method thereof with increased area efficiency by positioning the back gate line of the transistor in a lower layer of the layer where the word line and the bit line are positioned.

According to one embodiment of the disclosed invention, a semiconductor memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit connected to the plurality of word lines, a sense amplifier circuit connected to the plurality of bit lines, and a controller for generating signals applied to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of memory cells includes a first transistor having a gate node connected to a word line and one end connected to a bit line to store data in the memory cell, and a second transistor having a gate node connected to the other end of the first transistor and one end connected to the bit line and the other end connected to the word line to read data stored in the memory cell, wherein the first transistor and the second transistor may be configured as a four-terminal element including a back gate node.

The threshold voltages of the first transistor and the second transistor can be controlled through their respective back gate nodes.

When the first transistor is turned on, the threshold voltage of the first transistor may be lowered, and when the first transistor is turned off, the threshold voltage of the first transistor may be higher.

A first back gate line connected to the back gate node of the first transistor and a second back gate line connected to the back gate node of the second transistor may be located in a lower layer of the layer where the word line and the bit line are located.

When a write operation of the memory cell is performed, the controller may apply a HIGH signal to the word line and a data signal to the bit line so that data is charged to the gate node of the second transistor, apply a HIGH signal to the back gate node of the first transistor, and apply a LOW signal to the back gate node of the second transistor.

When a write operation of the above memory cell is performed, the threshold voltage of the first transistor may be lowered.

When a read operation of the memory cell is performed, the controller can apply a HIGH signal to the word line and read stored data through the bit line, apply a LOW signal to the back gate node of the first transistor, and apply a HIGH signal to the back gate node of the second transistor.

When a read operation of the above memory cell is performed, the threshold voltage of the first transistor may increase.

The first transistor and the second transistor share the word line and the bit line, and the memory cell may have a 2-WIRE structure.

A semiconductor memory device according to one embodiment of the disclosed invention may include a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cells including a first transistor and a second transistor having a gate node connected to the first transistor, a word line driving circuit connected to the plurality of word lines, a sense amplifier circuit connected to the plurality of bit lines, and a controller configured to apply signals to the plurality of word lines and the plurality of bit lines, and configured to adjust threshold voltages of the first transistor and the second transistor according to a write operation and a read operation of each of the plurality of memory cells.

The first transistor has a gate node connected to a word line and one end connected to a bit line to store data in a memory cell, and the second transistor has one end connected to the bit line and the other end connected to the word line to read data stored in the memory cell.

The first transistor and the second transistor may be configured as four-terminal devices including a back gate node.

A first back gate line connected to the back gate node of the first transistor and a second back gate line connected to the back gate node of the second transistor may be located in a lower layer of the layer where the word line and the bit line are located.

When a write operation of the above memory cell is performed, the controller can apply a HIGH signal to the back gate node of the first transistor and a LOW signal to the back gate node of the second transistor.

The method may include a step of selecting one memory cell among a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines and including a first transistor and a second transistor having a gate node connected to the first transistor, a step of performing a write operation for storing data in the selected memory cell, a step of performing a read operation for reading data stored in the selected memory cell, and a step of adjusting threshold voltages of the first transistor and the second transistor according to the write operation and the read operation of the selected memory cell.

A semiconductor memory device and a driving method thereof according to one embodiment of the disclosed invention have the advantage of minimizing leakage current and improving driving ability by controlling the driving ability of a transistor constituting a memory cell through a back gate line.

In addition, the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention have an advantage in that area efficiency can be increased by positioning the back gate line of the transistor in a lower layer of the layer where the word line and bit line are positioned.

In addition, the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention have the advantage of being able to reduce the area by configuring a memory cell using two transistors, but configuring it in a form in which each transistor shares a bit line and a word line.

Figure 1 is a drawing showing a memory cell of a 2 T structure according to the prior art.
FIG. 2 is a diagram showing the configuration of a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 3 is a drawing showing the configuration of a memory cell in a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 4 is a drawing showing a cross-sectional view of a memory cell in a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 5 is a diagram illustrating the operation of a plurality of memory cells arranged adjacently when a write operation is performed in a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 6 is a diagram illustrating the operation of a plurality of memory cells arranged adjacently when a read operation is performed in a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 7 is a diagram showing a sense amplifier circuit connected to a bit line and a complementary bit line in a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 8 is a flowchart illustrating a method for driving a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 9 is a diagram showing a simulation result when a write operation is performed on a semiconductor memory device according to one embodiment of the disclosed invention.
FIG. 10 is a diagram showing a simulation result when a read operation is performed on a semiconductor memory device according to one embodiment of the disclosed invention.

The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and there may be various modified examples that can replace the embodiments and drawings of this specification at the time of filing of this application.

Additionally, the same reference numbers or symbols presented in each drawing of this specification represent parts or components that perform substantially the same function.

Additionally, the terminology used herein is for the purpose of describing embodiments and is not intended to limit and/or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this specification, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Additionally, terms including ordinal numbers such as “first,” “second,” etc., used herein may be used to describe various components, but the components are not limited by the terms, and the terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component. The term "and/or" includes any combination of a plurality of related listed items or any one of a plurality of related listed items.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

Fig. 1 is a drawing showing a memory cell of a 2 T structure according to the prior art.

Referring to FIG. 1, a memory cell of a 2T structure according to the prior art may include a first transistor (WTR) and a second transistor (RTR).

More specifically, the first transistor (WTR) can be configured to store data by having a gate node connected to a write word line (WWL) and one end connected to a write bit line (WBL).

Additionally, the second transistor (RTR) may have a gate node connected to the other end of the first transistor (WTR), one end connected to a read word line (RWL), and the other end connected to a read bit line (RBL).

A DRAM including a memory cell of a 1T 1C structure according to a prior art can share charges inside the memory cell of the DRAM with a bit line through charge distribution.

At this time, the sense amplifier circuit detects the difference in voltage generated between the bit line and the complementary bit line, thereby allowing the data stored in the memory cell to be read.

However, in the case of a DRAM including a conventional 2T structure memory cell, the presence or absence of data stored in the memory cell can be confirmed through the current flowing through the second transistor (RTR), which is a transistor that reads data.

Therefore, in the case of a conventional 2T structure memory cell, there is no need to perform an operation to rewrite data after performing a read operation, which has advantages in terms of power, memory retention time, and bit line capacitance.

However, in the case of a conventional 2T structure memory cell, compared to a conventional 1T 1C structure memory cell, there is a problem in that the number of transistors is increased by one, the number of wires connected to the transistors increases, and the layout area increases, and parasitic capacitance increases.

This problem can be a fatal drawback in memory devices where integration is important.

In addition, unlike this, in the case of a memory cell utilizing a back gate of a conventional 1T 1C structure, there is an advantage of securing a long data retention time by reducing leakage current, but since the operation is the same as that of the conventional 1T 1C structure except for the operation of controlling the back gate, the charge stored in the capacitor of the memory cell is shared with the bit line capacitor when a data read operation is performed.

Accordingly, in the case of a memory cell utilizing a back gate of a conventional 1T 1C structure, there is a problem of power consumption because a rewrite operation must be performed to recharge the charge reduced by charge sharing.

In addition, in the case of a memory cell utilizing a back gate of a conventional 1T 1C structure, if the capacitance of the bit line is too large during charge sharing, there is a problem in that the sense amplifier circuit cannot detect the voltage difference between the bit line and the complementary bit line, and thus the matrix cannot be formed in a large size.

Accordingly, a semiconductor memory device (100) and a driving method thereof according to one embodiment of the disclosed invention are intended to solve the problems of the above-described prior art, and more specifically, there is a technical effect of implementing a memory cell using two transistors while minimizing the number of wires connected to the transistors, and increasing area efficiency by placing a back gate line for back gate control in a layer different from the layer where a word line and a bit line are placed.

More details on this will be provided later.

FIG. 2 is a diagram showing the configuration of a semiconductor memory device according to one embodiment of the disclosed invention. FIG. 3 is a diagram showing the configuration of a memory cell in a semiconductor memory device according to one embodiment of the disclosed invention. FIG. 4 is a diagram showing a cross-sectional view of a memory cell in a semiconductor memory device according to one embodiment of the disclosed invention.

Referring to FIG. 2, a semiconductor memory device (100) according to one embodiment of the disclosed invention may be a storage device based on a semiconductor element.

These semiconductor memory devices (100) may be random access memory (RAM) devices such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), SRAM (Static RAM), DDR SDRAM (Double Date Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), etc.

A semiconductor memory device (100) can store data received through a data signal (DQ) or output data as a data signal (DQ) in response to an address signal (ADDR) and a control command signal (CMD) received from an external host (e.g., a central processing unit (CPU), an application processor (AP), a system on a chip (SoC)).

Accordingly, a semiconductor memory device (100) according to one embodiment of the disclosed invention includes a memory cell array (10) and a peripheral circuit, and the peripheral circuit may include a word line driving circuit (20), a controller (40), a sense amplifier circuit (30), etc.

A memory cell array (10) includes a plurality of memory cells, and the plurality of memory cells can be connected to a word line driving circuit (20) through a plurality of word lines (WL) and connected to a sense amplifier circuit (30) through a plurality of bit lines (BL).

Additionally, each of the plurality of memory cells may be located at a point where a plurality of word lines (WL) and a plurality of bit lines (BL) intersect.

Additionally, a plurality of memory cells may be arranged in a matrix form in the memory cell array (10), and each of the plurality of memory cells may include at least one memory element for storing data.

For example, each of the plurality of memory cells of the semiconductor memory device (100) according to one embodiment of the disclosed invention may include a transistor as a switching element. Details regarding this will be described later.

The controller (40) can receive address signals and control command signals, etc. from an external host.

The address signal may include a row address indicating a row in the memory cell array (10) and a column address indicating a column in the memory cell array (10).

For example, the word line driving circuit (20) can select at least one of a plurality of word lines (WL) by referring to a row address, and the column decoder can select at least one of a plurality of bit lines (BL) by referring to a column address.

Additionally, the sense amplifier circuit (30) may include a plurality of bit line sense amplifiers connected to the memory cell array (10) through a plurality of bit lines (BL).

Among the plurality of bit line (BL) sense amplifiers, the bit line (BL) sense amplifier connected to the selected bit line (BL) selected by the column decoder can read data of at least one selected memory cell among the memory cells connected to the selected bit line, or store data in the selected memory cell.

A word line (WL) of a memory device of the disclosed invention is a signal used to select a row. In DRAM, data is stored in rows and columns, and a word line (WL) activates a specific row to enable access to data in that row.

When these word lines (WLs) are activated, the data in that row can be read or written.

The bit line (BL) of the memory device of the disclosed invention is a signal line used to read or write data.

In DRAM, data is stored in bit units, and a bit line (BL) selects a specific bit to read or write the data of that bit.

Bit lines (BL) can be used primarily for data transfer related to read and write operations.

Accordingly, while the voltage of the selected word line is maintained at an active level, the sense amplifier circuit (30) connected to the selected memory cell can read data of the selected memory cell or write data to the selected memory cell through the selected bit line (BL).

Referring to FIG. 3, a memory cell array (10) of a semiconductor memory device (100) according to one embodiment of the disclosed invention may include a plurality of memory cells (11) connected to a plurality of word lines (WL) and a plurality of bit lines (BL).

More specifically, each of the plurality of memory cells may include a first transistor (WTR) configured to store data in the memory cell and a second transistor (RTR) configured to read data stored in the memory cell.

For example, the first transistor (WTR) may have a gate node connected to a word line (WL) and one end connected to a bit line (BL).

Additionally, the other terminal of the first transistor (WTR) can be connected to the gate node of the second transistor (RTR).

Additionally, the second transistor (RTR) may have a gate node connected to the other end of the first transistor (WTR), one end connected to a bit line (BL), and the other end connected to a word line (WL).

These first transistor (WTR) and second transistor (RTR) can be configured as four-terminal devices including a back gate node.

Also, referring to FIG. 4, a first back gate line (BG) connected to the back gate node of the first transistor (WTR) and a second back gate line (BG2) connected to the back gate node of the second transistor (RTR) may be located in a lower layer of a layer where a word line and a bit line are located.

Through this, the disclosed invention can provide a semiconductor memory device (100) and a driving method thereof that implement a memory cell using back gate control and has increased area efficiency.

Accordingly, a semiconductor memory device (100) according to one embodiment of the disclosed invention can implement a memory cell of a 2-WIRE structure by having the first transistor and the second transistor share a word line and a bit line.

The back gate of a transistor is a component commonly found in a MOSFET (metal-oxide-semiconductor field-effect transistor).

The back gate of these MOSFETs is located on the opposite side from the gate used to form the channel, which allows controlling the characteristics of the MOSFET in different operating modes.

Additionally, the role of the back gate is to control the characteristics of the MOSFET to improve or manipulate its electrical characteristics.

In particular, the back gate can optimize the operation of the transistor by controlling the high conductivity and current flow of the transistor.

FIG. 5 is a diagram illustrating the operation of a plurality of memory cells arranged adjacently when a write operation is performed in a semiconductor memory device according to an embodiment of the disclosed invention. FIG. 6 is a diagram illustrating the operation of a plurality of memory cells arranged adjacently when a read operation is performed in a semiconductor memory device according to an embodiment of the disclosed invention. FIG. 7 is a diagram illustrating a sense amplifier circuit connected to a bit line and a complementary bit line in a semiconductor memory device according to an embodiment of the disclosed invention.

Referring to FIG. 5, in a semiconductor memory device (100) according to one embodiment of the disclosed invention, when a write operation is performed, the controller (40) can apply a HIGH signal to a word line (WL) of a selected memory cell (11a) so that data is charged to the gate node of the second transistor (RTR), and can apply a data signal to a bit line (BL).

Through this, data can be charged to the gate node of the second transistor (RTR), which is a transistor that reads data.

Additionally, the controller (40) can apply a LOW signal to the word line (WL) of an unselected memory cell (11b).

When such a write operation is performed, the controller (40) can apply a HIGH signal to the back gate node of the first transistor (WTR) and a LOW signal to the back gate node of the second transistor (RTR).

Through this, the disclosed invention can improve the driving capability of the first transistor (WTR) by lowering the threshold voltage Vth of the first transistor (WTR) by adjusting the back gate signal of the first transistor (WTR) high when a write operation is performed, and can prevent data from being lost to other memory cells by raising the threshold voltage Vth of the second transistor (RTR) by adjusting the back gate signal of the second transistor (RTR) low.

Accordingly, the semiconductor memory device (100) according to one embodiment of the disclosed invention has a technical effect of minimizing data loss due to leakage current by increasing the driving capability of the first transistor (WTR) when the first transistor (WTR), which is a transistor that writes data through the first back gate line and the second back gate line, is in an ON state, and increasing the threshold voltage Vth of the first transistor (WTR) when the first transistor (WTR) is in an OFF state.

At this time, since the back gate line is placed on a different layer from the layer where the word line, bit line, and transistor are placed, there is a technical effect that does not affect the area of a single memory cell.

Referring to FIG. 6, in a semiconductor memory device (100) according to one embodiment of the disclosed invention, when a read operation is performed, the controller (40) applies a HIGH signal to the word line (WL) of the selected memory cell (11a) and reads stored data through the bit line (BL).

At this time, the sense amplifier circuit (30) shown in Fig. 7 is connected to the bit line (BL).

Additionally, the controller (40) can apply a LOW signal to the word line (WL) of an unselected memory cell (11b).

When such a read operation is performed, the controller (40) can apply a LOW signal to the back gate node of the first transistor (WTR) and a HIGH signal to the back gate node of the second transistor (RTR).

Through this, the disclosed invention can prevent data loss of the first transistor (WTR) by lowering the back gate signal of the first transistor (WTR) when a read operation is performed, as opposed to when a write operation is performed, thereby increasing the threshold voltage Vth of the first transistor (WTR), and can improve the driving capability of the second transistor (RTR) by lowering the back gate signal of the second transistor (RTR) when a read operation is performed, as opposed to when a write operation is performed.

Accordingly, the semiconductor memory device (100) according to one embodiment of the disclosed invention has a technical effect of minimizing data loss due to leakage current by increasing the driving capability of the first transistor (WTR) when the first transistor (WTR), which is a transistor that writes data through the first back gate line and the second back gate line, is in an ON state, and increasing the threshold voltage Vth of the first transistor (WTR) when the first transistor (WTR) is in an OFF state.

At this time, since the back gate line is placed on a different layer from the layer where the word line, bit line, and transistor are placed, there is a technical effect that does not affect the area of a single memory cell.

Referring to FIG. 7, in a DRAM (Dynamic Random Access Memory) structure, a sense amplifier circuit (30) may include a CSA (Column Sense Amplifier, hereinafter referred to as a sense amplifier circuit).

This sense amplifier circuit (30) can amplify data read from a DRAM cell and transmit it to an external circuit.

Additionally, the sense amplifier circuit (30) can measure data of each column, amplify the value to respond to noise, and transmit the data to the outside.

This sense amplifier circuit (30) is connected to a bit line and a complementary bit line, and may include a plurality of transistors and a set of connection lines.

FIG. 8 is a flowchart illustrating a method for driving a semiconductor memory device according to one embodiment of the disclosed invention.

Referring to FIG. 8, a method for driving a semiconductor memory device (100) according to one embodiment of the disclosed invention may include a step (S110) of determining a selected memory cell among a plurality of memory cells.

More specifically, the step (S110) of determining a selected memory cell among a plurality of memory cells may include a step of applying a HIGH signal to a word line of the selected memory cell.

A method for driving a semiconductor memory device (100) according to one embodiment of the disclosed invention may include a step (S120) of performing a write operation (WRITE OPERATION) for storing data in a selected memory cell (11a).

More specifically, the step (S120) of performing a write operation (WRITE OPERATION) to store data in the selected memory cell (11a) may include a step of applying a HIGH signal to a word line of the selected memory cell (11a) and applying a data signal to a bit line.

A method for driving a semiconductor memory device (100) according to one embodiment of the disclosed invention may include a step (S130) of performing a read operation (READ OPERATION) for reading data stored in a selected memory cell (11a).

More specifically, the step (S130) of performing a read operation (READ OPERATION) to read data stored in the selected memory cell (11a) may include a step of applying a HIGH signal to a word line of the selected memory cell (11a) and reading the stored data through a bit line.

A method for driving a semiconductor memory device (100) according to one embodiment of the disclosed invention may include a step (S140) of adjusting a threshold voltage of a transistor according to a write operation and a read operation of a selected memory cell (11a).

More specifically, the step (S140) of controlling the threshold voltage of the transistor according to the write operation (WRITE OPERATION) and read operation (READ OPERATION) of the selected memory cell (11a) may include a step of applying a back gate signal to each transistor using a first back gate line (BG) connected to the back gate node of the first transistor (WTR) and a second back gate line (BG2) connected to the back gate node of the second transistor (RTR).

For example, the step (S140) of adjusting the threshold voltage of the transistor according to the write operation (WRITE OPERATION) and read operation (READ OPERATION) of the selected memory cell (11a) may include a step of the controller (40) applying a HIGH signal to the back gate node of the first transistor (WTR) and applying a LOW signal to the back gate node of the second transistor (RTR) when the write operation of the memory cell is performed.

In addition, the step (S140) of adjusting the threshold voltage of the transistor according to the write operation and read operation of the selected memory cell (11a) may include a step of the controller (40) applying a LOW signal to the back gate node of the first transistor (WTR) and applying a HIGH signal to the back gate node of the second transistor (RTR) when the read operation of the memory cell is performed.

Accordingly, a method for driving a semiconductor memory device (100) according to one embodiment of the disclosed invention has a technical effect of minimizing data loss due to leakage current by increasing the driving capability of the first transistor (WTR), which is a transistor that writes data through the first back gate line and the second back gate line, when the first transistor (WTR) is in an ON state, and increasing the threshold voltage Vth of the first transistor (WTR) when the first transistor (WTR) is in an OFF state.

At this time, since the back gate line is placed on a different layer from the layer where the word line, bit line, and transistor are placed, there is a technical effect that does not affect the area of a single memory cell.

FIG. 9 is a diagram showing simulation results when a write operation is performed on a semiconductor memory device according to an embodiment of the disclosed invention. FIG. 10 is a diagram showing simulation results when a read operation is performed on a semiconductor memory device according to an embodiment of the disclosed invention.

Referring to FIG. 9, in a semiconductor memory device (100) according to one embodiment of the disclosed invention, it can be confirmed that the source-drain voltage (Vst) of the first transistor (WTR) decreases after a HIGH signal is applied to the word line (WL) and the bit line (BL) when a write operation is performed.

Accordingly, the disclosed invention can increase the driving capability of the first transistor (WTR) by controlling the threshold voltage of the first transistor (WTR) when performing a data write operation of a memory cell.

Referring to FIG. 10, it can be confirmed that in a semiconductor memory device (100) according to one embodiment of the disclosed invention, when a read operation is performed, the current Irtr of the second transistor (RTR) for reading data from a memory cell has increased compared to the prior art.

A semiconductor memory device and a driving method thereof according to one embodiment of the disclosed invention have the advantage of minimizing leakage current and improving driving ability by controlling the driving ability of a transistor constituting a memory cell through a back gate line.

In addition, the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention have the advantage of being able to reduce the area by configuring a memory cell using two transistors, but configuring it in a form in which each transistor shares a bit line and a word line.

In addition, the semiconductor memory device and the driving method thereof according to one embodiment of the disclosed invention have an advantage in that area efficiency can be increased by positioning the back gate line of the transistor in a lower layer of the layer where the word line and bit line are positioned.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used singly; however, those skilled in the art will appreciate that the processing device may include multiple processing elements and/or multiple types of processing elements. For example, the processing device may include multiple processors, or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and/or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program commands, data files, data structures, etc., alone or in combination. The program commands recorded on the medium may be those specially designed and configured for the embodiment or may be those known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

Although the embodiments have been described with limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can be achieved even if the described techniques are performed in a different order than described, and/or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

100; semiconductor memory device
10; memory cell array
11; memory cell
20; Word line driver circuit
30; Sense amplifier circuit
40; controller
WTR; first transistor
RTR; second transistor
WL; word line
BL; bit line
BG; 1st Back Gate Line
BG2; 2nd Back Gate Line

Claims (15)

A memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines;
A word line driving circuit connected to the plurality of word lines;
a sense amplifier circuit connected to the plurality of bit lines; and
a controller that generates signals applied to the plurality of word lines and the plurality of bit lines;
Each of the above plurality of memory cells
A first transistor having a gate node connected to a word line and one end connected to a bit line to store data in a memory cell; and
A second transistor having a gate node connected to the other end of the first transistor to read data stored in the memory cell, one end connected to the bit line, and the other end connected to the word line;
The first transistor and the second transistor are characterized in that they are composed of four-terminal elements including a back gate node.
Semiconductor memory devices. In the first paragraph,
The first transistor and the second transistor are characterized in that their threshold voltages are controlled through their respective back gate nodes.
Semiconductor memory devices. In the second paragraph,
Characterized in that when the first transistor is turned on, the threshold voltage of the first transistor is lowered, and when the first transistor is turned off, the threshold voltage of the first transistor is higher.
Semiconductor memory devices. In the first paragraph,
The first back gate line connected to the back gate node of the first transistor and the second back gate line connected to the back gate node of the second transistor are characterized in that they are located in a lower layer of the layer where the word line and the bit line are located.
Semiconductor memory devices. In the first paragraph,
When a write operation of the memory cell is performed, the controller applies a HIGH signal to the word line and a data signal to the bit line so that data is charged to the gate node of the second transistor, applies a HIGH signal to the back gate node of the first transistor, and applies a LOW signal to the back gate node of the second transistor.
Semiconductor memory devices. In paragraph 5,
Characterized in that when a write operation of the above memory cell is performed, the threshold voltage of the first transistor is lowered.
Semiconductor memory devices. In the first paragraph,
When a read operation of the memory cell is performed, the controller applies a HIGH signal to the word line and reads stored data through the bit line, applies a LOW signal to the back gate node of the first transistor, and applies a HIGH signal to the back gate node of the second transistor.
Semiconductor memory devices. In paragraph 7,
Characterized in that when a read operation of the memory cell is performed, the threshold voltage of the first transistor increases.
Semiconductor memory devices. In the first paragraph,
The first transistor and the second transistor share the word line and the bit line, and the memory cell is characterized by a 2-WIRE structure.
Semiconductor memory devices. A memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, the memory cells including a first transistor and a second transistor having a gate node connected to the first transistor;
A word line driving circuit connected to the plurality of word lines;
a sense amplifier circuit connected to the plurality of bit lines; and
A controller configured to apply signals to the plurality of word lines and the plurality of bit lines, and configured to adjust threshold voltages of the first transistor and the second transistor according to a write operation and a read operation of each of the plurality of memory cells;
The first transistor has a gate node connected to a word line and one end connected to a bit line to store data in a memory cell,
The second transistor is characterized in that one end is connected to the bit line and the other end is connected to the word line to read data stored in the memory cell.
Semiconductor memory devices. delete In Article 10,
The first transistor and the second transistor are characterized in that they are composed of four-terminal elements including a back gate node.
Semiconductor memory devices. In paragraph 12,
The first back gate line connected to the back gate node of the first transistor and the second back gate line connected to the back gate node of the second transistor are characterized in that they are located in a lower layer of the layer where the word line and the bit line are located.
Semiconductor memory devices. In Article 12,
When a write operation of the memory cell is performed, the controller is characterized in that it applies a HIGH signal to the back gate node of the first transistor and applies a LOW signal to the back gate node of the second transistor.
Semiconductor memory devices. A step of selecting one memory cell from among a plurality of memory cells, the memory cells being connected to a plurality of word lines and a plurality of bit lines, and including a first transistor and a second transistor having a gate node connected to the first transistor;
A step of performing a write operation to store data in the selected memory cell;
A step of performing a read operation to read data stored in the selected memory cell; and
A step of controlling the threshold voltages of the first transistor and the second transistor according to a write operation and a read operation of the selected memory cell;
The first transistor has a gate node connected to a word line and one end connected to a bit line to store data in a memory cell,
The second transistor is characterized in that one end is connected to the bit line and the other end is connected to the word line to read data stored in the memory cell.
A method for driving a semiconductor memory device.