KR102859344B1 - Fpga-based spi communication method and device for performing the same - Google Patents

Abstract

An FPGA-based SPI communication method and a device for performing the same are disclosed. An electronic device for performing SPI (serial peripheral interface) communication according to various embodiments includes: a processor for generating instructions including at least one of data and information related to transmission of the data to a slave device; and an FPGA (field programmable gate array) electrically connected to the processor, wherein the FPGA receives the instructions from the processor, initiates transmission of the data to the slave device based on at least some of the instructions, and transmits the data to the slave device in parallel based on at least some of the instructions.

Description

FPGA-BASED SPI COMMUNICATION METHOD AND DEVICE FOR PERFORMING THE SAME

The following disclosure relates to an FPGA-based SPI communication method and a device performing the same.

SPI (Serial Peripheral Interface) is a short-distance serial communication standard that operates in full duplex mode and refers to communication between a master device and a slave device. For SPI communication, pins such as MOSI (master out slave input), MISO (master input slave out), CS (chip select), and SLCK (serial clock) may be required. MOSI refers to a signal line for data transmitted from a master device to a slave device, MISO refers to a signal line for data transmitted from a slave device to a master device, CS refers to a signal line for selecting a slave device to communicate with a master device among multiple slave devices, and SLCK refers to a clock signal line for synchronization.

As a related prior art, there is Korean Patent Publication No. KR 1447154 B1 (Title of invention: Operating method of general-purpose SPI core using FPGA).

The background technology described above is technology that the inventor possessed or acquired in the process of deriving the disclosure of the present application, and cannot necessarily be said to be publicly known technology disclosed to the general public prior to the present application.

A master device performing SPI communication may include a processor (e.g., an application processor such as an ARM Cortex-A9) and a field programmable gate array (FPGA). The processor may transmit data to the FPGA, and the FPGA may transmit received data to a slave device (e.g., a phased array antenna device including a vector-amplifier integrated circuit (VAIC). The data transfer rate between the processor and the FPGA may be faster than the data transfer rate between the FPGA and the slave device. This difference in data transfer rates may slow down the operating speed of the master device and/or the slave device.

Various embodiments can improve the operating speed of the master device and slave devices by transmitting data in parallel from the FPGA to the slave devices.

Various embodiments can trigger GPIOs at specific times by delaying operations performed in the FPGA based on a synchronous clock.

However, technical challenges are not limited to the technical challenges described above, and other technical challenges may exist.

An electronic device performing SPI communication according to various embodiments includes a processor that generates instructions including at least one of data and information related to transmission of the data to a slave device; and a field programmable gate array (FPGA) electrically connected to the processor, wherein the FPGA receives the instructions from the processor, initiates transmission of the data to the slave device based on at least some of the instructions, and transmits the data to the slave device in parallel based on at least some of the instructions.

The FPGA can delay triggering of a GPIO (general purpose input/output) of the FPGA based on at least some of the instructions.

The FPGA can check the transmission status of the data based on at least some of the instructions among the instructions, and delay triggering of the GPIO until the transmission of the data is completed.

The FPGA can transmit data using one of the CS (chip select) lines of the channels through which the data is transmitted in parallel based on at least some of the instructions among the instructions.

An electronic device performing SPI communication according to various embodiments includes a processor that generates instructions including at least one piece of information related to receiving data from a slave device; and an FPGA electrically connected to the processor, wherein the FPGA receives the instructions from the processor, initiates reception of the data from the slave device based on at least some of the instructions, receives the data in parallel from the slave device based on at least some of the instructions, and transmits the data to the processor.

The FPGA can delay triggering of a GPIO of the FPGA based on at least some of the instructions.

The FPGA can check the reception status of the data based on at least some of the instructions among the instructions, and delay triggering of the GPIO until reception of the data is completed.

The FPGA can receive data using one of the CS (chip select) lines of the channels through which the data is received in parallel based on at least some of the instructions.

An operating method of an FPGA included in an electronic device performing SPI communication according to various embodiments may include: receiving instructions from a processor, the instructions including at least one of data and information related to transmission of the data to a slave device; starting transmission of the data to the slave device based on at least some of the instructions; and transmitting the data to the slave device in parallel based on at least some of the instructions.

The above operating method may further include an operation of delaying triggering of a GPIO of the FPGA based on at least some of the instructions among the instructions.

The above delaying operation may include an operation of checking the transmission status of the data based on at least some of the instructions among the instructions; and an operation of delaying the triggering of the GPIO until the transmission of the data is completed.

The operation of transmitting the above data in parallel may include an operation of transmitting the data using one of the CS lines of the channels through which the data is transmitted in parallel based on at least some of the instructions among the above instructions.

An operating method of an FPGA included in an electronic device performing SPI communication according to various embodiments may include: receiving instructions from a processor, the instructions including at least one piece of information related to receiving data from a slave device; starting to receive data from the slave device based on at least some of the instructions; receiving the data from the slave device in parallel based on at least some of the instructions; and transmitting the data to the processor.

The above operating method may further include an operation of delaying triggering of a GPIO of the FPGA based on at least some of the instructions among the instructions.

The above delaying operation may include an operation of checking the reception status of the data based on at least some of the instructions among the instructions; and an operation of delaying the triggering of the GPIO until the reception of the data is completed.

FIG. 1 is a drawing for explaining an SPI communication system according to various embodiments.
FIG. 2 is a diagram for explaining an FPGA according to various embodiments.
FIG. 3 is a diagram illustrating an instruction dispatcher according to various embodiments.
FIG. 4 is a diagram illustrating an SPI transceiver according to various embodiments.
FIG. 5 is a diagram illustrating a bus interconnection between an instruction dispatcher and an SPI transceiver according to various embodiments.
Figure 6 is a flowchart illustrating an example of the operation of an FPGA according to various embodiments.
Figure 7 is a flowchart illustrating an example of the operation of an FPGA according to various embodiments.

Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Therefore, the actual implementation is not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or alternatives within the technical concepts described in the embodiments.

Although terms such as "first" or "second" may be used to describe various components, these terms should be interpreted solely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When it is said that a component is "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this document, phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can each include any one of the items listed together in that phrase, or all possible combinations thereof. In this specification, it should be understood that the terms "comprises" or "has" and the like are intended to specify the presence of a described feature, number, step, operation, component, part, or combination thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are assigned the same reference numerals regardless of the drawing numbers, and redundant descriptions thereof will be omitted.

FIG. 1 is a drawing for explaining an SPI communication system according to various embodiments.

Referring to FIG. 1, according to various embodiments, a master device (110) (e.g., an electronic device) and a slave device (190) can transmit and receive data (e.g., SPI data) through SPI (serial peripheral interface) communication.

According to various embodiments, the master device (110) may include a processor (130) (e.g., an application processor such as ARM coretex-A9) and a field programmable gate array (FPGA) (170). The processor (130) may generate instructions. For example, the instructions may include at least one of instructions including data, instructions including information necessary to transmit data to a slave device (190), and instructions including information necessary to receive data from the slave device (190). The FPGA (170) may transmit and receive instructions to and from the processor (130) via communication (e.g., an AXI4 bus interface). The transmission speed between the processor (130) and the FPGA (170) may be faster than the transmission speed between the FPGA (170) and the slave device (190). Due to the difference in the transmission speed between the processor (130) and the FPGA (170) and the transmission speed between the FPGA (170) and the slave device (190), the processor (130) may operate inefficiently. That is, the processor (130) may have difficulty operating efficiently because it may perform the next operation after the data transmitted to the FPGA (170) is transmitted to the slave device (190). According to various embodiments, the FPGA (170) may increase the operating efficiency of the processor (130) by reducing the waiting time of the processor (130) by transmitting and receiving data in parallel with the slave device (190). The FPGA (170) will be described in detail with reference to FIGS. 2 to 7.

According to various embodiments, the slave device (190) can transmit data to the master device (110) and receive data from the master device (110) via SPI communication. The slave device (190) may be an electronic device including an integrated circuit (IC). For example, the slave device (190) may be a phased array antenna including a vector-amplifier integrated circuit (VAIC). The VAIC may refer to an amplifier integrated circuit capable of setting the phase of a signal.

FIG. 2 is a diagram for explaining an FPGA according to various embodiments.

Referring to FIG. 2, according to various embodiments, the FPGA (170) may receive instructions from a processor (e.g., processor (130) of FIG. 1) and transmit and receive data to and from a slave device (e.g., slave device (190) of FIG. 1) based on the instructions.

According to various embodiments, the first FIFO (first in first out) (210) (e.g., an AXI stream FIFO) may include a TX_FIFO and an RX_FIFO. The TX_FIFO may store instructions (e.g., tx_data (201)) received from a processor (e.g., processor (130) of FIG. 1). The tx_data (201) may include instructions including data and/or instructions including information related to the transmission and reception of data. The RX_FIFO may store responses (e.g., rx_data (203)) including data received from a slave device (190). The rx_data (203) may include responses including data.

According to various embodiments, a GPIO (general purpose input/output) (220) may refer to a multi-purpose input/output port used by an FPGA (e.g., the FPGA (170) of FIG. 1) to communicate with a peripheral device (e.g., a slave device (190)). The FPGA (170) may control (e.g., turn on/off) the GPIO based on instructions.

According to various embodiments, the instruction dispatcher (230) can read instructions (e.g., tx_data (201)) from the TX_FIFO of the first FIFO (210) and execute the instructions. The instruction dispatcher (230) can write instructions (e.g., rx_data (203)) to the RX_FIFO of the first FIFO (210). The instruction dispatcher (230) will be described in detail with reference to FIG. 3.

According to various embodiments, instructions may be exchanged between an instruction dispatcher (230) and SPI transceivers (290-1 to 290-n) via an SPI bus interconnection (250). The SPI bus interconnection (250) will be described in detail with reference to FIG. 5.

According to various embodiments, each of the second FIFOs (270-1 to 270-n) may include a TX_FIFO and an RX_FIFO. The second FIFOs (270-1 to 270-n) may store instructions. The second FIFOs (270-1 to 270-n) will be described in detail with reference to FIG. 5.

According to various embodiments, the SPI transceivers (290-1 to 290-n) may read spi_cmd (391) (e.g., spi_cmd (391) of FIGS. 3 and 4) from the TX_FIFO of the second FIFOs (270-1 to 270-n) and execute the spi_cmd (391). The spi_cmd (391) may be an instruction (or command) included in the instruction tx_data (201). The spi_cmd (391) may be an instruction including data to be transmitted to the slave device (190). The SPI transceivers (290-1 to 290-n) can write spi_response (395) (e.g., spi_response (395) of FIGS. 4 and 5) to the RX_FIFO of the second FIFOs (270-1 to 270-n). The spi_response (395) may be an instruction including data received from the slave device (190). The spi_response (395) may be included in rx_data (203) and transmitted to the processor (130). The SPI transceivers (290-1 to 290-n) will be described in detail with reference to FIG. 4.

FIG. 3 is a diagram illustrating an instruction dispatcher according to various embodiments.

Referring to FIG. 3, according to various embodiments, the instruction dispatcher (230) can read instructions (e.g., tx_data (201)) from the TX_FIFO of the first FIFO (210) and execute the instructions. The instruction dispatcher (230) can write instructions (e.g., rx_data (203)) to the RX_FIFO of the first FIFO (210).

According to various embodiments, the instruction dispatcher (230) can read rx_data (203) in the FETCH (310) state. The instruction dispatcher (230) can update the GPIO of the FPGA (e.g., GPIO (220) of FIG. 2) through the instruction WRITE_IO (330). The wiring of the GPIO (220) can be determined based on the requirements of the application. The instruction dispatcher (230) can read the GPIO (220) through the instruction READ_IO (350) and push the I/O result to the RX_FIFO of the first FIFO (e.g., the first FIFO (210) of FIG. 2). A processor (e.g., processor (130) of FIG. 1) can monitor the status of an external I/O and an FPGA (e.g., FPGA (170) of FIG. 1) via a GPIO (220). An instruction dispatcher (230) can write spi_cmd (391) to the TX_FIFO of the second FIFOs (e.g., the second FIFOs (270-1 to 270-n) of FIG. 2) via an instruction PUSH_CMD (370). The instruction dispatcher (230) can select one or more second FIFOs among the second FIFOs (270-1 to 270-n) using select_spi (393) included in tx_data (201) and write spi_cmd (391) to the selected second FIFO. select_spi(393) may be a selection for a mux/demux (e.g., mux/demux of FIG. 5) of SPI transceivers (e.g., SPI transceivers (290-1 to 290-n) of FIGS. 2 and 5). The instruction dispatcher (230) may wait until a free space becomes available and then write spi_cmd(391) when the TX_FIFO of the selected second FIFO is full. The instruction dispatcher (230) may pop an spi_response(395) from the RX_FIFO of the second FIFOs (270-1 to 270-n) via the instruction POP_RESPONSE. The instruction dispatcher (230) can select one or more second FIFOs among the second FIFOs (270-1 to 270-n) using select_spi (393) included in tx_data (201) and pop spi_response (395) from the selected second FIFO. The spi_response (395) can be put on some bits of rx_data (203) and pushed to the RX_FIFO of the first FIFO (e.g., the first FIFO (210) of FIG. 2). The main purpose of the instruction POP_RESPONSE may be to read MISO (e.g., MISO (456) of FIG. 4). The instruction dispatcher (230) can wait until the spi_response (395) is stored in the RX_FIFO of the selected second FIFO if the RX_FIFO of the selected second FIFO is empty, and then pop the spi_response (395). Accordingly, the instruction dispatcher (230) can be configured to delay until the TX_FIFO of the second FIFO is empty and ready to trigger a LOAD (e.g., LOAD in FIG. 4) signal. Each of FETCH (310), WRITE_IO (330), READ_IO (350), PUSH_CMD (370), and POP_RESPONSE (390) can use a different number of clocks. For example, FETCH (310), WRITE_IO (330), and READ_IO (350) may use 1 clock, while PUSH_CMD (370) and POP_RESPONSE (390) may use 2 clocks if the selected second FIFO is ready.

FIG. 4 is a drawing for explaining an SPI transceiver according to various embodiments. FIG. 4 may be a drawing for explaining SPI transceivers (290-1 to 290-n) using one SPI transceiver (290-1) among the SPI transceivers (290-1 to 290-n) of FIG. 2 as an example.

Referring to FIG. 4, according to various embodiments, the SPI transceivers (290-1 to 290-n) can read spi_cmd (391) from the TX_FIFOs of the second FIFOs (e.g., the second FIFOs (270-1 to 270-n) of FIG. 2) and execute the spi_cmd (391).

According to various embodiments, the SPI transceiver (290-1) can read spi_cmd (391) in a FETCH state. The instruction SPI_TRANSMIT (462) can include data to be transmitted to a slave device (e.g., slave device (190) of FIG. 1) and a bit count. The bit count can count the length of the data. According to various embodiments, the SPI_TRANSMIT (462) can be executed in TRANSMIT_START, TRANSMIT_LOW, and/or TRANSMIT_HIGH. TRANSMIT_START, TRANSMIT_LOW, and TRANSMIT_HIGH can be states for controlling MOSI (454) or reading MISO (456). Specifically, TRANSMIT_START can be a transmit (or receive) ready state. In TRANSMIT_LOW, SLCK (serial clock) (452) may be maintained low, and in TRANSMIT HIGH, SLCK (452) may be maintained high. SLCK (452) may be a clock signal line for synchronization. SLCK (452) may rise/fall according to the bit count. The duty cycle of SLCK (452) may vary depending on the delay ticks property. The delay ticks property may be changed by the instruction SPI_SET_PROP (434). MOSI (454) may mean a signal line for data transmitted from a master device (e.g., master device (110) of FIG. 1) to a slave device (190). MOSI (454) can be set high/low on the falling edge of SLCK (452).

According to various embodiments, the instruction SPI_RECEIVE (464) may include data and a bit count received from the slave device (190). SPI_RECEIVE (464) may be executed in TRANSMIT_START, TRANSMIT_LOW, and/or TRANSMIT_HIGH. Duplicate descriptions will be omitted. MOSI (454) may change from high to low when data is received from the slave device (190) and at the same time when data is transmitted to the slave device (190). MISO (456) may mean a signal line for data transmitted from the slave device (190) to the master device (110). The data received from the slave device (190) may be included in spi_response (395) and pushed to the RX_FIFO of the second FIFO (e.g., the second FIFO (270-1) of FIG. 2). The SPI transceiver (290-1) can wait until there is free space and then push spi_response (395) when the RX_FIFO of the second FIFO (270-1) is full.

According to various embodiments, the instruction SPI_CONTROL (470) may include an I/O that can be used as multiple high/low. For SPI communication, SPI_CONTROL (470) may be positioned at the beginning and end of the instructions, and SPI_TRANSMIT (462) and/or SPI_RECEIVE (464) may be positioned between SPI_CONTROL (470). For example, the instructions may be executed in the following order: SPI_CONTROL 0x0, SPI_TRANSMIT 0xCAFE, SPI_RECEIVE 16bits, CONTROL 0x1.

According to various embodiments, the instruction SPI_SET_PROP (434) may include a duty cycle of SLCK (452). The duty cycle of SLCK (452) may be calculated as a power of 2. For example, if the value of the bit for the duty cycle of SLCK (452) is 3, SLCK (452) may remain high for 8 clocks and low for 8 clocks. SPI_SET_PROP (434) may be transmitted before SPI_RECEIVE (464) so that the transfer speed can be changed to a high speed and the read speed can be changed to a low speed.

According to various embodiments, RESPONSE_WRITE (490) may be a state of the SPI transceiver (290-1) that is activated when SPI_RECEIVE (464) is executed. When RESPONSE_WRITE (490) is activated, the SPI_transceiver (290-1) may store the spi_response (395) in the RX_FIFO of the second FIFO (270-1).

According to various embodiments, LOAD (430) may be a state of the SPI transceiver (290-1) in which instructions are executed. The SPI transceiver (290-1) may execute SPI_CONST (432) and/or SPI_SET_PROP (434) in LOAD (430).

According to various embodiments, the instruction SPI_CONST (432) may, when executed in an instruction dispatcher (e.g., the instruction dispatcher (230) of FIG. 3), push a specific value into the TX_FIFO of the second FIFO (270-1). The SPI_CONST (432), when executed in the SPI transceiver (290-1), may transfer a specific value to the RX_FIFO of the second FIFO (270-1). The instruction dispatcher (230) may, by executing an instruction (e.g., SPI_POP (not shown)), read a specific value from the RX_FIFO of the second FIFO (270-1) and confirm that transmission (or reception) of data has been completed. That is, the SPI dispatcher (230) can use SPI_CONST (432) to check the execution status of instructions located in front of SPI_CONST (432).

According to various embodiments, FETCH (410), LOAD (430), RESPONSE_WRITE (490), SPI_TRANSMIT (462), and SPI_RECEIVE (464) may each use a different number of clocks. SPI_CONTROL (470) may delay execution based on information contained in the instruction (e.g., delay time) before controlling CS (chip select).

FIG. 5 is a diagram illustrating a bus interconnection between an instruction dispatcher and an SPI transceiver according to various embodiments.

Referring to FIG. 5, according to various embodiments, the bus interconnection (250) may include a mux and a demux.

In various embodiments, SPI transceivers (290-1 through 290-n) may share spi_cmd (391) and/or spi_response (395). TX_FIFOs (510-1 through 510-n) may read wr_en (501) (write enable) and write full (503) (FIFO full). RX_FIFOs (560-1 through 560-n) may read rd_en (505) (read enable) and write empty (507) (FIFO empty). Signals (e.g., signals such as wr_en (501), full (503), rd_en (505), and empty (507)) may pass through a mux/demux and be selected by select_spi (393) from the instruction dispatcher (173). The instruction dispatcher (173) first sets select_spi (393), and can write or read spi_cmd (391) and/or spi_response (395) in the next cycle.

According to various embodiments, the second FIFOs (270-1 to 270-n) may require an option to save 1 clock at the start of a POP RESPONSE (e.g., first data fall through) (e.g., POP_RESPONSE (390) of FIG. 3).

Fig. 6 is a flowchart for explaining an example of the operation of an FPGA according to various embodiments. Fig. 6 may be a diagram for explaining an operation in which an FPGA (e.g., FPGA (170) of Fig. 1) transmits data to a slave device (e.g., slave device (190) of Fig. 1).

Referring to FIG. 6, according to various embodiments, operations 610 to 650 may be sequentially performed by the FPGA (170), but are not limited thereto. For example, the order of operations 630 and 650 may be switched, or two or more operations may be performed in parallel.

In operation 610, the FPGA (170) may receive instructions from a processor (e.g., processor (130) of FIG. 1) via communication (e.g., an AXI4 bus interface). The instructions may include instructions including data, instructions including information related to the transmission of data. For example, the instructions may include information such as information regarding the start timing of data transmission, information regarding the CS line used for the transmission of data, and information regarding I/O.

In operation 630, the FPGA (170) can transmit data to the slave device (190) based on the instructions. That is, after receiving the instructions from the processor (130), the FPGA (170) can transmit the data to the slave device (190) based on the instructions without intervention of the processor (130). For example, the FPGA (170) can start transmitting the data based on at least some of the instructions. For example, the FPGA (170) can transmit the data to the slave device (190) in parallel based on at least some of the instructions. Specifically, the FPGA (170) can transmit data in parallel through one or more SPI transceivers among the SPI transceivers (e.g., the SPI transceivers (290-1 to 290-n) of FIGS. 2 and 5) based on at least some of the instructions. Each channel of the plurality of transceivers (290-1 to 290-n) may be different. The FPGA (170) can transmit data using any one of the CS (chip select) lines of the channels through which data is transmitted based on at least some of the instructions. According to various embodiments, the FPGA (170) can increase the operating efficiency of the processor (130) by transmitting data in parallel through the plurality of channels to the slave device (190). According to various embodiments, the FPGA (170) can operate efficiently by transmitting data to a slave device (190) based on instructions received from the processor (130) without intervention of the processor (130).

In operation 650, the FPGA (170) can control a GPIO (e.g., GPIO (220) of FIG. 2). For example, the FPGA (170) can push a specific value to the TX_FIFOs of the second FIFOs (e.g., TX_FIFOs (510-1 to 510-n) of FIG. 5) using an instruction (e.g., SPI_CONST (432) of FIG. 4) and transmit the specific value to the RX_FIFOs (e.g., RX_FIFOs (560-1 to 560-n) of FIG. 5). The FPGA (170) can check the transmission status of data by reading a specific value from the RX_FIFOs (560-1 to 560-n) and delay the triggering of the GPIO (220) until the transmission of the data is completed. FPGA (170) can control GPIO (e.g. TX_LOAD) when data transmission is completed.

Fig. 7 is a flowchart for explaining an example of the operation of an FPGA according to various embodiments. Fig. 7 may be a diagram for explaining an operation in which an FPGA (e.g., FPGA (170) of Fig. 1) receives data from a slave device (e.g., slave device (190) of Fig. 1).

Referring to FIG. 7, according to various embodiments, operations 710 to 770 may be sequentially performed by the FPGA (170), but are not limited thereto. For example, the order of operations 750 and 770 may be switched, or two or more operations may be performed in parallel.

In operation 710, the FPGA (170) may receive instructions from a processor (e.g., processor (130) of FIG. 1) via communication (e.g., an AXI4 bus interface). The instructions may include instructions including data, instructions including information related to the transmission of data. For example, the instructions may include information such as information regarding a timing for starting data reception, information regarding a CS line used to receive data, and information regarding I/O.

In operation 730, the FPGA (170) may receive data from a slave device (e.g., the slave device (190) of FIG. 1) based on instructions. That is, after receiving instructions from the processor (130), the FPGA (170) may receive data from the slave device (190) based on the instructions without intervention of the processor (130). For example, the FPGA (170) may start receiving data based on at least some of the instructions. For example, the FPGA (170) may receive data from the slave device (190) in parallel based on at least some of the instructions. Specifically, the FPGA (170) can receive data in parallel through one or more SPI transceivers among the SPI transceivers (e.g., the SPI transceivers (290-1 to 290-n) of FIGS. 2 and 5) based on at least some of the instructions. Each channel of the plurality of transceivers (290-1 to 290-n) may be different. The FPGA (170) can receive data using any one of the CS (chip select) lines of the channels through which data is received based on at least some of the instructions. According to various embodiments, the FPGA (170) can increase the operating efficiency of the processor (130) by receiving data in parallel from the slave device (190) through the plurality of channels. According to various embodiments, the FPGA (170) can operate efficiently by receiving data from a slave device (190) based on instructions received from the processor (130) without intervention of the processor (130).

At operation 750, the FPGA (170) can transmit data to the processor (130) via communication.

In operation 770, the FPGA (170) can control a GPIO (e.g., GPIO (220) of FIG. 2). For example, the FPGA (170) can push a specific value to the TX_FIFOs of the second FIFOs (e.g., TX_FIFOs (510-1 to 510-n) of FIG. 5) using an instruction (e.g., SPI_CONST (432) of FIG. 4) and transfer the specific value to the RX_ FIFOs (e.g., RX_FIFOs (560-1 to 560-n) of FIG. 5). The FPGA (170) can check the reception status of data by reading a specific value from the RX_FIFOs (560-1 to 560-n) and delay the triggering of the GPIO (220) until the reception of the data is completed. The FPGA (170) can control the GPIO (e.g., TX_LOAD) when the reception of the data is completed.

The embodiments described above may be implemented using hardware components, software components, and/or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented using a general-purpose computer or a special-purpose computer, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and software applications running on the operating system. Furthermore, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and/or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may, independently or collectively, command the processing device. The software and/or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave, for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on a computer-readable recording medium.

The method according to the embodiment may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may store program commands, data files, data structures, etc., alone or in combination, and the program commands recorded on the medium may be those specially designed and configured for the embodiment or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program commands, such as ROMs, RAMs, and flash memories. Examples of program commands include not only machine language codes such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter, etc.

The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments described above have been described with limited drawings, those skilled in the art will appreciate that various technical modifications and variations can be applied based on the described embodiments. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and/or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims (16)

In an electronic device that performs SPI (serial peripheral interface) communication,
A processor generating instructions including at least one of data and information related to the transmission of said data to a slave device; and
FPGA (field programmable gate array) electrically connected to the above processor
Including,
The above FPGA,
Receive the instructions from the processor,
Initiate transmission of said data to said slave device based on at least some of said instructions,
Transmitting the data in parallel to the slave device based on at least some of the instructions among the above instructions,
After receiving the instructions from the processor, the data is transmitted to the slave device based on at least some of the instructions without intervention of the processor,
Check the transmission status of the data by reading a specific value received from the slave device,
An electronic device that delays triggering of a GPIO (general purpose input/output) of the FPGA until transmission of the above data is completed.
delete delete In the first paragraph,
The above FPGA,
An electronic device that transmits data using one of the CS (chip select) lines of channels through which the data is transmitted in parallel based on at least some of the instructions among the above instructions.
In an electronic device performing SPI communication,
A processor that generates instructions including at least one piece of information related to receiving data from a slave device; and
FPGA electrically connected to the above processor
Including,
The above FPGA,
Receive the instructions from the processor,
Initiate reception of said data from said slave device based on at least some of said instructions,
Receiving the data in parallel from the slave device based on at least some of the instructions among the above instructions,
Transmit the above data to the processor,
After receiving the instructions from the processor, the data is received from the slave device based on at least some of the instructions without intervention of the processor,
By reading a specific value received from the slave device, the reception status of the data is confirmed,
An electronic device that delays triggering of a GPIO (general purpose input/output) of the FPGA until reception of the above data is completed.
delete delete In paragraph 5,
The above FPGA,
An electronic device that receives data using one of the CS (chip select) lines of the channels through which the data is received in parallel based on at least some of the instructions among the above instructions.
In a method of operating an FPGA included in an electronic device performing SPI communication,
An operation of receiving instructions from a processor, the instructions including at least one of data and information related to the transmission of said data to a slave device;
An operation of initiating transmission of said data to said slave device based on at least some of said instructions;
An operation of transmitting the data in parallel to the slave device based on at least some of the instructions among the instructions; and
An operation of delaying the triggering of the GPIO of the FPGA based on at least some of the instructions among the above instructions.
Including,
The action to start transmitting the above data is:
After receiving the instructions from the processor, an operation of transmitting the data to the slave device based on at least some of the instructions without intervention of the processor.
Including,
The above delaying action is,
An operation of checking the transmission status of the data by reading a specific value received from the slave device; and
An action to delay the triggering of the GPIO until the transmission of the above data is completed.
A method of operation, comprising:
delete delete In paragraph 9,
The operation of transmitting the above data in parallel is as follows:
An operation of transmitting data using one of the CS lines of the channels through which the data is transmitted in parallel based on at least some of the instructions among the above instructions.
A method of operation, comprising:
In a method of operating an FPGA included in an electronic device performing SPI communication,
An operation of receiving instructions from a processor, the instructions including at least one piece of information relating to receiving data from a slave device;
An operation of initiating reception of data from the slave device based on at least some of the instructions among the above instructions;
An operation of receiving the data in parallel from the slave device based on at least some of the instructions among the instructions;
An operation of transmitting the above data to the processor; and
An operation of delaying the triggering of the GPIO of the FPGA based on at least some of the instructions among the above instructions.
Including,
The action to start receiving the above data is:
An operation of receiving the data from the slave device based on at least some of the instructions without intervention of the processor after receiving the instructions from the processor.
Including,
The above delaying action is,
An operation of confirming the reception status of the data by reading a specific value received from the slave device; and
An action to delay the triggering of the GPIO until the reception of the above data is completed.
A method of operation, comprising:
delete delete In Article 13,
The operation of receiving the above data in parallel is:
An operation of receiving data using one of the CS lines of the channels through which the data is received in parallel based on at least some of the instructions among the above instructions.
A method of operation, comprising: