KR102812313B1 - Vertical field-effect transistor(VFET) devices including latches having cross-couple structure - Google Patents

Abstract

An integrated circuit device is provided. The integrated circuit device comprises a substrate including a first region, a second region, and a boundary region between the first region and the second region, the first region and the second region being spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, a first latch disposed on the first region of the substrate and including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor, a second latch disposed on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor, the first vertical field effect transistor and the seventh vertical field effect transistor being arranged in the first horizontal direction, and a conductive layer including a first portion extending in the first horizontal direction, intersecting the boundary region, and including a gate electrode of the first vertical field effect transistor, and a second portion including a gate electrode of the seventh vertical field effect transistor.

Description

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure

The present invention relates generally to the field of electronic devices, and more particularly to vertical field effect transistor (VFET) devices.

Vertical field-effect transistor (VFET) devices have been studied due to the high scalability of vertical field-effect transistors. In addition, interconnection between vertical field-effect transistors can be simpler than interconnection between planar transistors. With respect to vertical field-effect transistors, Korean Patent Laid-Open No. KR 10-2018-0069465 (published on June 25, 2018) discloses a vertical field-effect transistor in which a source region (or drain region), a channel region, and a drain region (or source region) are sequentially overlapped and stacked, a gate electrode is arranged to surround the channel region at a level between the source region and the drain region, and the channel region is formed to vertically penetrate the gate electrode.

The problem to be solved by the present invention is to provide an integrated circuit device including a vertical field effect transistor with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to some embodiments of the present invention for solving the above problems, an integrated circuit device comprises a substrate including a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, a first latch disposed on the first region of the substrate and including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor, a second latch disposed on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor, wherein the first vertical field effect transistor and the seventh vertical field effect transistor are arranged in the first horizontal direction, and a conductive layer including a first portion extending in the first horizontal direction, intersecting the boundary region, and including a gate electrode of the first vertical field effect transistor, and a second portion including a gate electrode of the seventh vertical field effect transistor.

According to some other embodiments of the present invention for solving the above problem, an integrated circuit device comprises a substrate including a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, a first latch disposed on the first region of the substrate and including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor, and a second latch disposed on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor, wherein the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged along the first horizontal direction, and the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are the second vertical field effect transistor, The gate signal applied to the gate electrode of each of the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor is shared.

According to still another embodiment of the present invention for solving the above problem, an integrated circuit device comprises a substrate including a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, the first region of the substrate includes an NMOS region and a PMOS region spaced apart from the NMOS region in the first horizontal direction, a first latch disposed on the first region of the substrate and including a first vertical field effect transistor and a third vertical field effect transistor on the PMOS region, and a second vertical field effect transistor and a fourth vertical field effect transistor on the NMOS region, wherein the first vertical field effect transistor includes a first channel region and a first upper source/drain sequentially stacked on the substrate, the second vertical field effect transistor includes a second channel region and a second upper source/drain sequentially stacked on the substrate, and the third vertical field effect transistor includes a third channel region and a third upper source/drain sequentially stacked on the substrate, A fourth vertical field effect transistor includes a fourth channel region and a fourth upper source/drain sequentially stacked on a substrate, a second latch disposed on a second region of the substrate, and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor, and an upper source/drain contact in contact with the first upper source/drain, the second upper source/drain, the third upper source/drain, and the fourth upper source/drain.

Figure 1 is a circuit diagram of a device including a master latch and a slave latch.
FIG. 2 is a diagram illustrating a transistor including a master latch and a slave latch illustrated in FIG. 1 according to some embodiments of the present invention.
FIGS. 3A, 3B, 3C, and 3D are layout diagrams of devices according to some embodiments of the present invention.
Figure 4 is a layout diagram showing the cutting lines of the cross-sectional view.
FIGS. 5A, 5B and 5C are cross-sectional views taken along lines AA', BB' and CC' of FIG. 4, respectively, according to some embodiments of the present invention.
FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G and 6H are cross-sectional views taken along lines 1-1', 2-2', 3-3', 4-4', 5-5', 6-6', 7-7' and 8-8' of FIG. 4, respectively, according to some embodiments of the present invention.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. Many other forms and embodiments are possible without departing from the spirit and teachings of the present invention, and therefore, the present invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements.

Exemplary embodiments of the technical idea of the present invention are described below with reference to cross-sectional drawings which are schematic diagrams of intermediate structures of ideal embodiments and exemplary embodiments. As such, variations from the shape of the illustration as a result of, for example, manufacturing techniques and/or tolerances should be expected. Accordingly, exemplary embodiments of the technical idea of the present invention should not be construed as being limited to the specific shapes illustrated herein, and include, for example, shape deviations resulting from manufacturing processes.

FIG. 1 is a circuit diagram of a device including a master latch and a slave latch. Each of the master latch and the slave latches has a cross-couple structure. The device illustrated in FIG. 1 may be a part of a flip-flop circuit. In some embodiments, the circuit illustrated in FIG. 1 may be a part of a scan flip-flop circuit, although the technical idea of the present invention is not limited thereto. The device illustrated in FIG. 1 may be a part of a different type of flip-flop circuit.

Referring to FIG. 1, a first transistor (TR1), a second transistor (TR2), a third transistor (TR3), and a fourth transistor (TR4) of a master latch form a first cross-couple structure, and a fifth transistor (TR5), a sixth transistor (TR6), a seventh transistor (TR7), and an eighth transistor (TR8) of a slave latch form a second cross-couple structure. The type and number of transistors between any one of the first transistor (TR1), the third transistor (TR3), the fifth transistor (TR5), and the seventh transistor (TR7) and VDD, and the type and number of transistors between any one of the second transistor (TR2), the fourth transistor (TR4), the sixth transistor (TR6), and the eighth transistor (TR8) and VSS may vary depending on the type of a flip-flop circuit including the master latch and the slave latch. Additionally, the first feedback loop (FL1) and the second feedback loop (FL2) may include various types and numbers of transistors depending on the type of flip-flop circuit.

In some embodiments, each of the first, third, fifth and seventh transistors (TR1, TR3, TR5, TR7) can be a P-type transistor, and the second, fourth, sixth and eighth transistors (TR2, TR4, TR6, TR8) can be an N-type transistor, as illustrated in FIG. 1.

Referring to FIG. 1, a clock signal (CLK) may be applied to a plurality of transistors (e.g., a second transistor (TR2), a third transistor (TR3), a fifth transistor (TR5), and an eighth transistor (TR8)), and an inverted clock signal (/CLK) may be applied to a plurality of transistors (e.g., a first transistor (TR1), a fourth transistor (TR4), a sixth transistor (TR6), and a seventh transistor (TR7)). In some embodiments, the clock signal (CLK) may be applied to the first transistor (TR1), the fourth transistor (TR4), the sixth transistor (TR6), and the seventh transistor (TR7), and the inverted clock signal (/CLK) may be applied to a plurality of transistors (e.g., a second transistor (TR2), a third transistor (TR3), a sixth transistor (TR5), and an eighth transistor (TR8)).

Since each of the clock signal (CLK) and the inverted clock signal (/CLK) is shared by a plurality of transistors, a single conductive line (for example, the conductive layer (220) of FIG. 3B) to which one of the clock signal (CLK) and the inverted clock signal (/CLK) is applied can be shared by a plurality of transistors. By sharing a single conductive line with a plurality of transistors, the total number of conductive lines included in the device can be reduced, and therefore, the shared single conductive line can simplify the layout of the device and reduce the amount of conductive material used to manufacture the device.

FIG. 2 illustrates a transistor including a master latch and a slave latch as illustrated in FIG. 1 according to some embodiments of the present invention. A master latch including first, second, third, and fourth transistors (TR1, TR2, TR3, TR4) may be provided in a first latch region (i.e., a master latch region), and slave latches including fifth, sixth, seventh, and eighth transistors (TR5, TR6, TR7, TR8) may be provided on a second latch region (i.e., a slave latch region). In order to provide a common conductive line to a plurality of transistors, the master latch region and the slave latch regions may be arranged along a first horizontal direction (e.g., the X-direction in FIG. 2), and the master latch and the slave latches may form a double height structure as illustrated in FIG. 2. It will be appreciated that the term "height" in the "double height structure" does not mean that the master latch region and the slave latch regions are stacked in a vertical direction. The master latch region and the slave latch region are arranged spaced apart from each other in the first horizontal direction (X), and a boundary region may be provided between the master latch region and the slave latch region.

"Component A and component B are arranged along the X direction" (or similar language) could mean that component A and component B are spaced apart from each other in the X direction and aligned along the X direction.

The master latch region may include a first NMOS region (NR1) and a first PMOS region (PR1) between the first NMOS region (NR1) and a boundary region. The P-type transistors of the master latch (i.e., the first transistor (TR1) and the third transistor (TR3)) may be provided on the first PMOS region (PR1), and the N-type transistors of the master latch (i.e., the second transistor (TR2) and the fourth transistor (TR4)) may be provided on the first NMOS region (NR1). The first transistor (TR1) and the third transistor (TR3) may be arranged to be spaced apart from each other in a second horizontal direction (e.g., the Y direction in FIG. 2) as illustrated in FIG. 2. The second transistor (TR2) and the fourth transistor (TR4) may be arranged to be spaced apart from each other in the second horizontal direction (Y). In some embodiments, the first horizontal direction (X) is perpendicular to the second horizontal direction (Y).

The slave latch region may include a second NMOS region (NR2) and a second PMOS region (PR2) between the second NMOS region (NR2) and the boundary region. The P-type transistor of the slave latch (i.e., the fifth transistor (TR5) and the seventh transistor (TR7)) may be provided on the second PMOS region (PR2), and the N-type transistor of the slave latch (i.e., the sixth transistor (TR6) and the eighth transistor (TR8)) may be provided on the second NMOS region (NR2).

Referring to FIG. 2, a first transistor (TR1) of a master latch to which an inverted clock signal (/CLK) is applied and a seventh transistor (TR7) of a slave latch to which an inverted clock signal (/CLK) is applied may be arranged on a first virtual line (IL_1) and may be spaced apart from each other in a first horizontal direction (X). The first transistor (TR1) and the seventh transistor (TR7) may be provided at positions where the first virtual line (IL_1) intersects the first PMOS region (PR1) and the second PMOS region (PR2), respectively. Accordingly, a single conductive layer (for example, the conductive layer (220) of FIG. 3b) extending in the first horizontal direction (X) and receiving the inverted clock signal (/CLK) may be shared by the first transistor (TR1) and the seventh transistor (TR7). The first transistor (TR1) and the seventh transistor (TR7) can share a gate signal (e.g., an inverted clock signal (/CLK)).

The second and third transistors (TR2, TR3) of the master latch to which the clock signal (CLK) is applied and the fifth and eighth transistors (TR5, TR8) of the slave latch to which the clock signal (CLK) is applied can be arranged on the second virtual line (IL_2) and can be spaced apart from each other in the first horizontal direction (X). The second, third, fifth and eighth transistors (TR2, TR3, TR5, TR8) can be provided at positions where the second virtual line (IL_2) intersects the first NMOS region (NR1), the first PMOS region (PR1), the second PMOS region (PR2) and the second NMOS region (NR2), respectively. Accordingly, a single conductive layer (e.g., conductive layer (220) of FIG. 3b) extending in the first horizontal direction (X) and receiving the clock signal (CLK) can be shared by the second, third, fifth and eighth transistors (TR2, TR3, TR5, TR8). The second, third, fifth and eighth transistors (TR2, TR3, TR5, TR8) can share a gate signal (e.g., clock signal (CLK)).

Therefore, the dual height structure allows the transistors included in different latches (i.e., the master latch and the slave latch) to share a conductive layer to which either the clock signal (CLK) or the inverted clock signal (/CLK) is applied, thereby sharing the gate signal.

As illustrated in FIG. 2, a fourth transistor (TR4) of a master latch to which an inverted clock signal (/CLK) is applied and a sixth transistor (TR6) of a slave latch to which an inverted clock signal (/CLK) is applied may be arranged on a third virtual line (IL_3) and may be spaced apart from each other in the first horizontal direction (X). The fourth transistor (TR4) and the sixth transistor (TR6) may be provided at positions where the third virtual line (IL_3) intersects the first NMOS region (NR1) and the second NMOS region (NR2), respectively.

In some embodiments, the device may include dummy regions (DR) in which no transistors are provided. As illustrated in FIG. 2, the device may include two dummy regions (DR) at each location where the first virtual line (IL_1) intersects the first NMOS region (NR1) and the second NMOS region (NR2). Additionally, as illustrated in FIG. 2, the device may include two dummy regions (DR) at each location where the third virtual line (IL_3) intersects the first PMOS region (PR1) and the second PMOS region (PR2).

In some embodiments, as illustrated in FIG. 2, each of the first, second and third virtual lines (IL_1, IL_2, IL_3) can extend in a first horizontal direction (X) and can be spaced apart from each other in a second horizontal direction (Y) that is parallel to a top surface of the substrate and perpendicular to the first horizontal direction (X). The second virtual line (IL_2) can be formed between the first virtual line (IL_1) and the third virtual line (IL_3). It will be appreciated that each of the first, second and third virtual lines (IL_1, IL_2, IL_3) can correspond to a first, second and third column.

It will be appreciated that the use of a vertical field-effect transistor (VFET) can further simplify the layout of the device. A vertical field-effect transistor includes a vertical channel protruding vertically from a substrate (e.g., perpendicular to a top or bottom surface of the substrate) and an upper source/drain positioned on the vertical channel. Since the upper source/drain is the uppermost portion of the vertical field-effect transistor, the upper source/drain of the vertical field-effect transistor and the upper source/drain of an adjacent vertical field-effect transistor can be connected via a horizontal conductive pattern on the upper source/drain.

Figures 3a, 3b, 3c, and 3d are layout diagrams of a device according to some embodiments of the present invention. To simplify the drawings, Figures 3a to 3d illustrate groups of some components, but not all components of the device.

Referring to FIG. 3A, a substrate (e.g., the substrate (100) of FIG. 5A) may include a master latch region, a slave latch region spaced apart from the master latch region in a first horizontal direction (X), and a boundary region between the master latch region and the slave latch region. The first horizontal direction (X) may be parallel to a top or bottom surface of the substrate (100). Each of the transistors of the master latch region and the slave latch region may be a vertical field effect transistor and may include a vertical channel. The first to eighth transistors (TR1, TR2, TR3, TR4, TR5, TR6, TR7, and TR8) may include a first vertical channel (VC1), a second vertical channel (VC2), a third vertical channel (VC3), a fourth vertical channel (VC4), a fifth vertical channel (VC5), a sixth vertical channel (VC6), a seventh vertical channel (VC7), and an eighth vertical channel (VC8), respectively.

The lower source/drain (140) may surround each transistor, and an isolation region (120) may be provided between the lower source/drain (140). The lower source/drain contact (160) may extend longitudinally in a second horizontal direction (Y). In some embodiments, the second horizontal direction (Y) may be parallel to a top or bottom surface of the substrate (100) and perpendicular to the first horizontal direction (X).

Referring to FIG. 3B, each of the conductive layers (220) may extend longitudinally in the first horizontal direction (X). One of the conductive layers (220) may be shared by the first and seventh vertical channels (VC1, VC7). The conductive layer (220) shared by the first and seventh vertical channels (VC1, VC7) may include a portion surrounding the first vertical channel (VC1) and may constitute a gate electrode of the first transistor (TR1), and may include a portion surrounding the seventh vertical channel (VC7) and may constitute a gate electrode of the seventh transistor (TR7).

In some embodiments, one of the conductive layers (220) may be shared by the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8). The conductive layer (220) shared by the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8) may include a portion surrounding each of the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8). Each of the portions surrounding the conductive layer (220) may form a gate electrode of one of the second, third, fifth, and eighth transistors (TR2, TR3, TR5, TR8). Two conductive layers (220) may each surround the fourth and sixth vertical channels (VC4, VC6) and form gate electrodes of the fourth transistor (TR4) and the sixth transistor (TR6), respectively.

The conductive layer (220) shared by the first and seventh vertical channels (VC1, VC7) may extend in the first horizontal direction (X) from a portion surrounding the seventh vertical channel (VC7) and may include a pad region (220P) disposed on a slave latch region. The conductive layer (220) shared by the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8) may include a pad region (220P) disposed on a boundary region. The gate contacts (240) may overlap and be connected to the pad region (220P) to electrically connect the conductive layer (220) to each of the conductive wirings (e.g., 340 of FIG. 3c). The gate contact (240) can overlap and be connected to the conductive layer (220) surrounding the fourth and sixth vertical channels (VC4, VC6), as illustrated in FIG. 3b.

Referring to FIG. 3c, in some embodiments, a via contact (320) may be provided on each of the gate contacts (240). Each of the via contacts (320) may connect one of the gate contacts (240) to a corresponding conductive wiring (340).

Referring to FIG. 3d, an upper source/drain contact (260) may be provided that overlaps the first, second, third, and fourth vertical channels (VC1, VC2, VC3, VC4), and an upper source/drain contact (260) may be provided that overlaps the fifth, sixth, seventh, and eighth vertical channels (VC5, VC6, VC7, VC8). On the master latch region, a via contact (320) may be provided on the upper source/drain contact (260) to connect the upper source/drain contact (260) to a conductive wiring (340). On the slave latch region, a single via contact (320) may be provided on the upper source/drain contact (260) to connect the upper source/drain contact (260) to a conductive wiring (340).

FIG. 4 is a layout diagram showing cut lines of a cross-section. FIGS. 5a, 5b, and 5c are cross-section views taken along lines A-A', B-B', and C-C' of FIG. 4, respectively, according to some embodiments of the present invention. FIGS. 6a, 6b, 6c, 6d, 6e, 6f, 6g, and 6h are cross-section views taken along lines 1-1', 2-2', 3-3', 4-4', 5-5', 6-6', 7-7', and 8-8' of FIG. 4, respectively, according to some embodiments of the present invention.

It can be seen that the cross-section cut along the 9-9' line is identical or similar to the cross-section cut along the 1-1' line.

Referring to FIG. 5A, the substrate (100) may include a master latch region, a slave latch region, and a boundary region between the master latch region and the slave latch region. The master latch region may be spaced apart from the slave latch region in a first horizontal direction (X). The master latch may be provided in the master latch region of the substrate (100), and the slave latch may be provided in the slave latch region of the substrate (100). The first transistor (TR1) includes a first vertical channel (VC1) protruding from an upper surface of the substrate (100) and an upper source/drain (150) on the first vertical channel (VC1). A lower source/drain (140) may be disposed on the substrate (100) and may surround a lower portion of the first vertical channel (VC1). In some embodiments, the lower source/drain (140) may be formed by an epitaxial growth process, and the lower source/drain (140) may be referred to as a lower epitaxial layer. The seventh vertical field effect transistor may have a structure similar to the first vertical field effect transistor, as illustrated in FIG. 5A.

An isolation region (120) may be provided between adjacent lower sources/drains (140) to electrically insulate the lower sources/drains (140) from each other. In some embodiments, the isolation region (120) may be formed by a shallow trench isolation process, and the isolation region (120) may be referred to as an STI region.

The conductive layer (220) may surround the vertical channel (VC1) and extend toward the seventh vertical channel (VC7). As illustrated in FIG. 5A, the conductive layer (220) may cross (e.g., extend continuously across) the boundary region of the substrate (100). The spacer (280) may be disposed on the lower surface and/or the upper surface of the conductive layer (220) to electrically insulate the conductive layer (220) from the lower source/drain (140). The spacer (280) may expose the pad region (220P) of the conductive layer (220), as illustrated in FIG. 5A. The spacer (280) may include an insulating material (e.g., silicon oxide).

The upper source/drain contact (260) can be in contact with the upper source/drain (150) of each of the first vertical field-effect transistor and the seventh vertical field-effect transistor, as illustrated in FIG. 5A. Referring again to FIG. 3D, the upper source/drain contact (260) of the master latch can be in contact with the upper source/drain (150) of the first, second, third, and fourth transistors (TR1, TR2, TR3, TR4), and the upper source/drain contact (260) of the slave latch can be in contact with the upper source/drain (150) of the fifth, sixth, seventh, and eighth transistors (TR5, TR6, TR7, TR8) (see FIGS. 6B and 6D). In some embodiments, the upper source/drain contact (260) of the master latch may be electrically connected to the conductive wiring (340) via a via contact (320) disposed between the upper source/drain contact (260) and the conductive wiring (340), as illustrated in FIG. 5A.

The gate contact (240) may be disposed on the insulating layer (420) and may extend in a vertical direction (e.g., in the Z direction) perpendicular to the upper surface of the substrate (100). A signal (e.g., a clock signal and an inverted clock signal) may be applied to the conductive layer (220) through the gate contact (240). The gate contact (240) may be electrically connected to the conductive wiring (340) through a via contact (320) between the gate contact (240) and the conductive wiring (340), as illustrated in FIG. 5A. The lower source/drain contact (160) may be provided on the isolation region (120).

Referring to FIGS. 3B and 5B, the conductive layer (220) may extend longitudinally in the first horizontal direction (X) and may intersect a boundary region of the substrate (100). The conductive layer (220) may include a portion surrounding the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8), as illustrated in FIG. 5B, and each surrounding portion of the conductive layer (220) may constitute a gate (e.g., a gate electrode) of one of the second, third, fifth, and eighth transistors (TR2, TR3, TR5, TR8). The conductive layer (220) may include a pad region (220P) on the boundary region of the substrate (100) to which the gate contact (240) is connected. The gate contact (240) can extend in the vertical direction (Z) and be electrically connected to the conductive wiring (340) through a via contact (320) between the gate contact (240) and the conductive wiring (340).

Referring to FIG. 5B, the upper source/drains (150) of the second, third, fifth, and eighth transistors (TR2, TR3, TR5, and TR8) may be provided on the second, third, fifth, and eighth vertical channels (VC2, VC3, VC5, VC8), respectively. In some embodiments, the upper source/drain contact (260) on the master latch region may be in contact with the upper source/drains (150) of the second and third transistors (TR2, TR3), and the upper source/drain contact (260) on the slave latch region may be in contact with the upper source/drains (150) of the fifth and eighth transistors (TR5, TR8). The upper source/drain contact (260) on the slave latch region can be electrically connected to the conductive wiring (340) through a via contact (320) between the upper source/drain contact (260) and the conductive wiring (340).

Referring to FIG. 5c, the conductive layers (220) may be spaced apart from each other in the first horizontal direction (X) and may surround the fourth vertical channel (VC4) and the sixth vertical channel (VC6), respectively. The conductive layers (220) may be electrically connected to each other through gate contacts (240), via contacts (320), and conductive wiring (340). The spacer (280) may not be provided on a portion of the conductive layer (220) to which the gate contact (240) is connected.

Referring to FIGS. 5a and 5c, the dummy region (DR) is a portion of the substrate (100) in which no vertical channel is formed.

Referring to FIG. 6a, the lower source/drain contact (160) may be provided on the isolation region (120) and may extend longitudinally in the second horizontal direction (Y).

Referring to FIG. 6b, the sixth vertical channel (VC6) and the eighth vertical channel (VC8) may be spaced apart in the second horizontal direction (Y), and the upper source/drain (150) may be provided on each of the sixth vertical channel (VC6) and the eighth vertical channel (VC8). In some embodiments, the upper source/drain contact (260) may be in contact with the upper source/drain (150) of the sixth and eighth transistors (TR6, TR8).

Referring to FIG. 6c, the conductive layers (220) may be provided on a separation region (120) extending between the NMOS region and the PMOS region of the slave latch region. The pad region (220P) of the conductive layer (220) may be electrically connected to the conductive wiring (340) through the gate contact (240) and the via contact (320). The upper source/drain contact (260) may be electrically connected to the conductive wiring (340) through the gate contact (240) and the via contact (320). The conductive layer (220) may be electrically connected to the conductive wiring (340) through the gate contact (240) and the via contact (320).

Referring to FIG. 6d, the fifth vertical channel (VC5) and the seventh vertical channel (VC7) may be spaced apart in the second horizontal direction (Y), and the upper source/drain (150) may be provided on each of the fifth and seventh vertical channels (VC5, VC7). In some embodiments, the upper source/drain contact (260) may be in contact with the upper source/drain (150) of the fifth and seventh transistors (TR5, TR7).

Referring to FIG. 6e, the conductive layers (220) can be provided on the separation region (120) on the boundary region. The pad region (220P) of the conductive layer (220) in the boundary region can be electrically connected to the conductive wiring (340) through the gate contact (240) and the via contact (320).

Referring to FIG. 6f, the first vertical channel (VC1) and the third vertical channel (VC3) may be spaced apart in the second horizontal direction (Y), and the upper source/drain (150) may be provided on each of the first vertical channel (VC1) and the third vertical channel (VC3). In some embodiments, the upper source/drain contact (260) may be in contact with the upper source/drain (150) of the first and third transistors (TR1, TR3). A via contact (320) may be provided on the upper source/drain contact (260) to connect the upper source/drain contact (260) to the conductive wiring (340).

Referring to FIG. 6g, a conductive layer (220) may be provided on a separation region (120) extending between a first NMOS region (NR1) and a first PMOS region (PR1) of a master latch region. The conductive layer (220) extending around and surrounding a fourth vertical channel (VC4) may be electrically connected to a conductive wiring (340) through a gate contact (240) and a via contact (320).

Referring to FIG. 6h, the second vertical channel (VC2) and the fourth vertical channel (VC4) may be spaced apart in the second horizontal direction (Y), and the upper source/drain (150) may be provided on each of the second vertical channel (VC2) and the fourth vertical channel (VC4). In some embodiments, the upper source/drain contact (260) may be in contact with the upper source/drain (150) of the second and fourth transistors (TR2, TR4).

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in the meaning commonly understood by a person of ordinary skill in the art to which the present invention belongs. In addition, it will be understood that terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal meaning, except where explicitly defined.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the technical scope of the present invention. In the context of describing the present invention (especially in the context of the claims that follow), the terms "a," "an," "the," and similar terms are to be construed to include both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" should be construed as not excluding the presence of (i.e., meaning "including but not limited to").

In this specification, "component A vertically overlapping component B" (or similar language) will be understood to mean that there is a vertical line crossing both components A and B.

It will be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. Accordingly, a first component may be referred to as a second component without departing from the technical spirit of the present invention.

The technical idea of the present invention described above should be considered as illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements and other embodiments that fall within the technical idea and scope of the present invention. Accordingly, to the maximum extent permitted by law, the scope should be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited by the foregoing detailed description.

TR1 to TR8: first to eighth transistors
VC1 to VC8: 1st to 8th vertical channels
100: substrate 120: separation area
140: Lower source/drain 150: Upper source/drain
160: Lower source/drain contact 220: Conductive layer
240: Gate contact 260: Top source/drain contact
280: Spacer 320: Via Contact
340: Conductive wire 420: Insulating layer

Claims (20)

A substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate;
A first latch disposed on the first region of the substrate and including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor and a fourth vertical field effect transistor;
A second latch disposed on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor and an eighth vertical field effect transistor, wherein the first vertical field effect transistor and the seventh vertical field effect transistor are arranged in the first horizontal direction; and
An integrated circuit device comprising a conductive layer including a first portion extending in the first horizontal direction, intersecting the boundary region, and including a gate electrode of the first vertical field effect transistor and a second portion including a gate electrode of the seventh vertical field effect transistor. In paragraph 1,
An integrated circuit device comprising the above-described challenging layer receiving a clock signal or an inverted clock signal. In the second paragraph,
The conductive layer includes a pad region protruding from the second portion of the conductive layer and arranged on the second region of the substrate,
An integrated circuit device further comprising a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. In the third paragraph,
Each of the first vertical field-effect transistor and the seventh vertical field-effect transistor is a P-type vertical field-effect transistor,
The above-mentioned challenging layer is an integrated circuit device that receives the inverted clock signal. In the second paragraph,
The above challenging layer includes a pad area on the boundary area,
An integrated circuit device further comprising a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. In paragraph 1,
The first vertical field effect transistor includes a first channel region and a first upper source/drain sequentially stacked on the substrate, the second vertical field effect transistor includes a second channel region and a second upper source/drain sequentially stacked on the substrate, the third vertical field effect transistor includes a third channel region and a third upper source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor includes a fourth channel region and a fourth upper source/drain sequentially stacked on the substrate.
An integrated circuit device further comprising an upper source/drain contact in contact with the first upper source/drain, the second upper source/drain, the third upper source/drain, and the fourth upper source/drain. In paragraph 6,
The first region of the substrate includes an NMOS region and a PMOS region between the NMOS region and the boundary region,
The first vertical field effect transistor and the third vertical field effect transistor are P-type vertical field effect transistors, and the first vertical field effect transistor and the third vertical field effect transistor are arranged in a second horizontal direction that is parallel to the upper surface of the substrate and perpendicular to the first horizontal direction on the PMOS region.
An integrated circuit device wherein each of the second vertical field-effect transistor and the fourth vertical field-effect transistor is an N-type vertical field-effect transistor, and the second vertical field-effect transistor and the fourth vertical field-effect transistor are arranged in the second horizontal direction on the NMOS region. In Article 7,
An integrated circuit device wherein the second vertical field effect transistor and the third vertical field effect transistor are arranged along the first horizontal direction. A substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate;
a first latch disposed on the first region of the substrate and including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor and a fourth vertical field effect transistor; and
A second latch is disposed on the second region of the substrate and includes a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor and an eighth vertical field effect transistor,
The second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor and the eighth vertical field effect transistor are arranged along the first horizontal direction,
An integrated circuit device in which the second vertical field-effect transistor, the third vertical field-effect transistor, the fifth vertical field-effect transistor, and the eighth vertical field-effect transistor share a gate signal applied to each of the gate electrodes of the second vertical field-effect transistor, the third vertical field-effect transistor, the fifth vertical field-effect transistor, and the eighth vertical field-effect transistor. In Article 9,
An integrated circuit device wherein the above gate signal is a clock signal or an inverted clock signal. In Article 9,
Further comprising a conductive layer extending in the first horizontal direction and intersecting the boundary region,
An integrated circuit device, wherein the first portion of the conductive layer includes the gate electrode of the second vertical field effect transistor, the second portion of the conductive layer includes the gate electrode of the third vertical field effect transistor, the third portion of the conductive layer includes the gate electrode of the fifth vertical field effect transistor, and the fourth portion of the conductive layer includes the gate electrode of the eighth vertical field effect transistor. In Article 11,
The above challenging layer includes a pad area on the boundary area,
An integrated circuit device further comprising a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. In Article 11,
The first vertical field effect transistor includes a first channel region and a first upper source/drain sequentially stacked on the substrate, the second vertical field effect transistor includes a second channel region and a second upper source/drain sequentially stacked on the substrate, the third vertical field effect transistor includes a third channel region and a third upper source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor includes a fourth channel region and a fourth upper source/drain sequentially stacked on the substrate.
An integrated circuit device further comprising an upper source/drain contact in contact with the first upper source/drain, the second upper source/drain, the third upper source/drain, and the fourth upper source/drain. In Article 13,
An integrated circuit device wherein the first upper source/drain is disposed between the substrate and the upper source/drain contact. In Article 13,
The first region of the substrate includes an NMOS region and a PMOS region between the NMOS region and the boundary region,
The first vertical field effect transistor and the third vertical field effect transistor are arranged in a second horizontal direction that is parallel to the upper surface of the substrate and perpendicular to the first horizontal direction on the PMOS region,
An integrated circuit device wherein the second vertical field effect transistor and the fourth vertical field effect transistor are arranged in the second horizontal direction on the NMOS region. A substrate including a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are spaced apart from each other in a first horizontal direction parallel to an upper surface of the substrate, and the first region of the substrate includes an NMOS region and a PMOS region spaced apart from the NMOS region in the first horizontal direction;
A first latch disposed on the first region of the substrate, the first vertical field effect transistor and the third vertical field effect transistor on the PMOS region, and the second vertical field effect transistor and the fourth vertical field effect transistor on the NMOS region, the first vertical field effect transistor including a first channel region and a first upper source/drain sequentially stacked on the substrate, the second vertical field effect transistor including a second channel region and a second upper source/drain sequentially stacked on the substrate, the third vertical field effect transistor including a third channel region and a third upper source/drain sequentially stacked on the substrate, and the fourth vertical field effect transistor including a fourth channel region and a fourth upper source/drain sequentially stacked on the substrate;
a second latch disposed on the second region of the substrate and including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor and an eighth vertical field effect transistor; and
An integrated circuit device comprising an upper source/drain contact in contact with the first upper source/drain, the second upper source/drain, the third upper source/drain, and the fourth upper source/drain. In Article 16,
The first vertical field effect transistor is disposed at a first position where a first virtual line intersects the PMOS region, the second vertical field effect transistor is disposed at a second position where a second virtual line intersects the NMOS region, the third vertical field effect transistor is disposed at a third position where the second virtual line intersects the PMOS region, and the fourth vertical field effect transistor is disposed at a fourth position where a third virtual line intersects the NMOS region.
Each of the first to third virtual lines extends in the first horizontal direction, and the first to third virtual lines are spaced apart from each other in a second horizontal direction that is parallel to the upper surface of the substrate and perpendicular to the first horizontal direction.
An integrated circuit device in which the second virtual line is formed between the first virtual line and the third virtual line. In Article 17,
Further comprising a conductive layer extending in the first horizontal direction,
An integrated circuit device wherein the first portion of the conductive layer includes a gate electrode of the second vertical field effect transistor, and the second portion of the conductive layer includes a gate electrode of the third vertical field effect transistor. In Article 18,
An integrated circuit device comprising the above-described challenging layer receiving a clock signal or an inverted clock signal. In Article 16,
The second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor and the eighth vertical field effect transistor are arranged along the first horizontal direction,
Further comprising a conductive layer extending in the first horizontal direction,
An integrated circuit device wherein the first portion of the conductive layer includes a gate electrode of the second vertical field effect transistor, the second portion of the conductive layer includes a gate electrode of the third vertical field effect transistor, the third portion of the conductive layer includes a gate electrode of the fifth vertical field effect transistor, and the fourth portion of the conductive layer includes a gate electrode of the eighth vertical field effect transistor.