KR102817231B1 - An power-saving computer system by controlling the power according to CPU usage rate and controlling method therefor - Google Patents

Abstract

The present invention relates to a power-saving computer system capable of optimally saving power without lowering CPU performance, and a method for controlling the same, by pre-saving 'user work habit data', which is data (CPU frequency and/or core voltage) different from the work habits of a user according to various running apps or files, and immediately operating the CPU according to such data if the 'user work habit data' stored in advance by identifying currently running apps (a set of running apps) or files exists in dB, and otherwise setting the optimal operating method (CPU frequency and/or core voltage) according to the CPU usage rate according to the operating state of the CPU by a linear regression model.

Description

{An power-saving computer system by controlling the power according to CPU usage rate and controlling method therefor}

The present invention relates to a power-saving computer system and a control method thereof, which reduces energy consumed by the entire computer system by determining the current operating state (usage rate) of the CPU of a computer main board and setting an optimal operating method (CPU frequency and/or core voltage) according to the CPU usage rate according to the operating state of the CPU by a linear regression model, thereby optimally saving power without lowering CPU performance.

As shown in Fig. 1, a conventional computer power supply device has a power supply (20) such as SMPS connected to the SIO (12) of the main board (10) with 24 pins, one of which is for applying a +5V standby voltage (+5VSB).

When a user presses the power switch (not shown) of a PC case, a power button (13) mechanically connected thereto is pressed, and the power button (13) sends a first signal (PWRBTN#) to SIO (12), which in turn activates a power-on signal line (PSON#) to the power supply (20) and sends a second signal (PWRBTN#_SB) to the chipset (14). The power supply (20) notifies the CPU (11) and the chipset (14) of this by sending a power good signal (PWROK) signal, and then supplies power to the main board.

The unexplained symbol 15 is the reset button of the chipset, 16 is the battery, 17 is the reset (17), and 18 is the LAN. In addition, AC, FWH, super IO (19), AGP slot, PCI slot, IDE, etc., which are connected to the CPU and chipset, are connected.

Meanwhile, as described above, a standby power of +5 V is applied between the power supply (20) and the main board even when not in operation, and a standby power of about 1 W is required for recognition of the start button and remote start, etc.

And, although this is not a high power consumption individually, it leads to a huge waste of energy for the entire organization and even for the entire country.

To solve these problems, an outlet having a switch that completely cuts off the power to the outlet itself to make standby power zero has been developed (first prior art), while on the other hand, a separate, additional, complex device has been proposed to completely cut off the power by recognizing the on/off status of the power switch, as in Korean Patent Publication No. 2013-0043923 (Power supply device and image forming device including the same) (second prior art).

However, in the case of the first prior art, in reality, there are many cases where users leave their seats without turning off the complete power cut-off switch of the outlet for various reasons, and in the case of the second prior art, it is true that it is difficult to install such a device in a general PC because a separate, very complex and expensive device must be added.

Accordingly, the inventor of the present invention has proposed Korean Patent No. 1328393 (Title: Computer power supply device with reduced standby power) to provide a computer power supply device that is very simple and automatically minimizes standby power, and this is described as the third prior art.

The above third prior art comprises, as shown in FIG. 2, a main board (10) having a CPU (11), SIO (12), a power button (13), a chipset (14), a reset button (15), a first battery (16), a LAN (18), and a super IO (19); an SMPS (20) supplying power to the main board; a microcomputer (30) controlling standby power supply of the SMPS; a power connector (60) mediating signal and standby power connection between the main board and the SMPS; and a switching unit (40) switching the standby power on/off according to the control of the microcomputer; and the microcomputer (30) is characterized in that it controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit (40).

That is, the power supply device of the third prior art, as shown in Fig. 2, comprises a main board (10) having a conventional CPU (11), SIO (12), power button (13), chipset (14), reset button (15), battery (16), reset (17), LAN (18), super IO (19), etc., an SMPS (20) for supplying power to the main board, a microcomputer (30) for controlling the standby power supply of the SMPS, and a switching unit (40) for switching the standby power on/off according to the control of the microcomputer. Unexplained reference numeral '50' is a power switch of the PC case, and '60' is a power connector between the main board and the SMPS.

In the above third prior art, the power connector (60) mediates the signal and standby power connection between the main board (10) and the SMPS (20), and the SMPS (20) and the power connector are connected with 23 pins, and instead, one pin, the +5V standby power line (+5VSB), is connected to the microcomputer (30) and the switching unit (40) instead of the power connector, which is different from the conventional power supply device of Fig. 1. The switching unit (40) may be an IC for a power switch or may be formed of a FET circuit.

In addition, the microcomputer (30) receives either one or both of the SMPS good signal (PS_ON#) or the power good signal (PWR_ON) from the SMPS (20). The power good signal (PWR_ON) is also applied to the CPU (11) and the chipset (14).

Meanwhile, the microcomputer (30) also starts a standby power supply start operation by a switching signal (CASE_PWR_BTN) from an external case power switch (50), and accordingly, the +5 V standby power (+5VSB) is applied to the main board (10) as a 5 V standby signal (P5V_STBY) through the switching unit (40). When the control signal (5VSB_SW) of the microcomputer (30) is 'on', the switching unit (40) applies the +5 V standby power (+5VSB) from the SMPS (20) as a 5 V standby signal (P5V_STBY) to the main board (10).

From the SMPS (20) power connector, the PC normal operation power +12V and -12V lines, +5V standby power line and +3.3V power line, and power good (PWR_ON) signal go to the main board (10) power connector. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) to the main board power connector.

Furthermore, a standby power switch signal (5VSB_SW) goes from the microcomputer (30) to the switching unit (40), and a power button signal (MB_PWR_BTN) goes to the main power button (12).

Conversely, the SMPS good (PS_ON#) signal goes from the main board (10) power connector to the SMPS (20) power connector.

To explain these operations in more detail, first, the microcomputer (30) of the third prior art controls the standby power (5VSB) of the power supply by the switching unit (40), thereby controlling the power supplied to the main board. Usually, when the power is turned off, the microcomputer detects the power good (PWR_ON) and/or SMPS good (PS_ON#) signals going back and forth between the connectors, and when the power is off, the 5V standby power is turned off. That is, in this case, since the standby power is not supplied to the main board, the computer cannot be turned on.

Meanwhile, when a PC user presses the case power switch (50), the third prior art microcomputer (30) is activated by this signal, and the microcomputer detects the power good (PWR_ON) and/or SMPS good (PS_ON#) signals going back and forth between the connectors, and when the power is on, it turns on the control signal (5VSB_SW) to the switching unit (40), so that the 5V standby power (5VSB) is applied to the main board. In addition, when the power button (13) of the main board is turned on, an input/output start command is sent to the SIO (12), and the SIO (12) issues a power supply good (PS_ON#) to the SMPS (20) through the power connector (60). When the situation is normal, the SMPS transmits the power good (PWR_ON) signal to the main board (10) through the connector (60) while activating the main board operating power (+12V).

Therefore, according to the third prior art, there is an advantage in that standby and computer startup are possible with only about 0.1 W of standby power corresponding to the standby power of a microcomputer, without consuming 1 W of standby power corresponding to the standby power of a computer startup system.

However, unlike conventional systems that only have the system power 'on' and 'off' states, recent PCs adopt S1 to S5 modes, adopting various subdivided modes and thus achieving the most efficient system operation with increased speed and resource utilization. For reference, S0 mode is the computer operation mode, S1 mode is the state where the processor is idle and supplies low power, but power must still be supplied to the RAM, S2 mode is the state where the processor is in deep sleep mode, but power is still supplied to the RAM, and in the case of S3 mode (power saving/standby mode), data is stored in memory and minimum power is maintained, so even in this case, +5V SB should not be turned off. At this time, although the output is slightly different depending on the type of DDR memory, the VDD power is continuously maintained at 1.2~1.5V, and power is supplied only to some parts such as the memory and RTC. On the other hand, in S4 mode (maximum power saving mode), data is stored in the hard disk and all power of the system is turned off. In other words, it is almost the same as power OFF. At this time, the VDD power of the memory is output as 0V as when the power is OFF. Therefore, it is possible to check for standby power cut-off with a single VDD signal. To summarize, in the case of the system standby power OFF conditions, such as power OFF and S4 mode, the VDD signal is 0V, and in the case of the standby power ON conditions, such as system operation (power ON state) and S3 (power saving/standby mode), the VDD signal outputs 1.2 to 1.5V.

Accordingly, in the case of a system having such a recent S0~S5 mode, even in the case of the third prior art, in order to block this standby power, it is necessary to check the status of all power supplies. In the conventional method, 1) measuring the current applied inside the SMPS, or 2) checking by checking several more signals such as 'power good', but 1) in the case of checking the current, an expensive ADC (Analog to Digital Converter) and peripheral circuits are required, so there is no cost-effectiveness in reducing 1W of standby power, and 2) in the case of checking through a signal such as 'power good', since all power supplies cannot be checked with a single signal, there is a problem that production efficiency is low due to a complex structure in order to input multiple signals and check the power status.

Meanwhile, the conventional general power-on operation will be described with reference to FIGS. 3 to 7.

FIG. 3 is a drawing explaining the concept of a conventional general power-on operation. Conventionally, as shown in FIG. 3, when the power button is turned 'on', the PS_ON circuit (19a) in the super IO (19) recognizes this, communicates with the south bridge of the chipset (14), and activates the PS_ON# terminal of the 20-pin connector of the SIO (12) of the main board (10) so that power is supplied to the main board (10).

An example of a block diagram of the PS_ON circuit (19a) of the above Fig. 3 is illustrated in detail in Fig. 4. That is, in Fig. 4, when the switch (S1) corresponding to the power button is pressed, the PS_ON circuit (19a) is activated as it drops to a 'low' level, and various voltages are applied from the SMPS to the main board (see the timing chart of Fig. 5).

In addition, FIG. 6 is another example drawing explaining the concept of a conventional general power-on operation. Again, when power 'on' switching (PWR) is performed, the chipset (14) outputs a P.ON signal to SIO (12), and SIO (12) then outputs the P.ON signal to the PS_ON# terminal of the connector of the main board, so that power is supplied from the SMPS to the main board.

Figure 7 is a timing chart of each signal in Figure 6. When VAC is activated (AC power is supplied), the PS_ON# signal drops to a 'low' level and becomes activated, and various voltages are supplied from the SMPS to the main board, responding with a power good signal.

That is, as in Fig. 6, conventionally, the PS_ON# signal (SMPS power On) was also connected to the power 'On' switch of the main board after first turning on the +5V SB signal, and then the PS_ON# signal was generated to the SMPS through the southbridge and the Super I/O chipset, which made cable connection and modification work difficult, and ultimately resulted in low productivity.

On the other hand, in order to solve the above problems, the inventor of the present invention proposed a computer power supply device that reduces standby power as shown in FIGS. 8 to 10 in order to provide a computer power supply device that is very simple and automatically minimizes standby power even in a computer system having various operation modes, and was granted a patent under Patent No. 1623756. This will be described with reference to FIGS. 2 and 8 to 10.

FIG. 8 is a block diagram of a computer power supply device with reduced standby power according to the fourth conventional technology, FIG. 9 is a detailed circuit diagram of a computer power supply device with reduced standby power according to the fourth conventional technology, and FIG. 10 is a flowchart of the operation of a microcomputer of a computer power supply device with reduced standby power according to the fourth conventional technology.

First, if the invention of the fourth prior art is schematically explained with the block diagram of Fig. 8, first, whether the PC power (50) is 'on' is detected, and in conjunction with this, the PS_ON# signal of the ATX power cable going from the SMPS (20) to the main board is activated to a 'low' level, so that all lines except the 5V SB line go to the main board. At this time, the 5V SB line does not go directly to the main board, but provides Vcc to the microcomputer (30) and the first switching unit (40), and activates them, thereby activating the power control signal (PWR_CTRL) and outputting it to the first switching unit (40), and in response, the first switching unit (40) sends a power output signal (PWR_OUT) to the 5V SB terminal of the main board, so that all power is supplied to the main board and the main board is operated.

At this time, the microcomputer (30) may operate the main board by applying the PS_ON# signal to the SMPS (20) to turn on the SMPS and, in response, by applying the signal and the common ground signal linked thereto to the SMPS to apply other signals and power from the SMPS to the main board (10) via the ATX cable. However, as shown in FIG. 8, it is also possible for the microcomputer (30) to apply the PS_ON# signal directly to the main board via the second switching unit (41) without going through the SMPS, such as from the power button (13) of the main board -> PS_ON circuit (19a) -> PS_ON# terminal of the power connector (60).

These circuits, described in more detail with reference to Fig. 9, detect the on/off state of the PC power 'on' switch (50) through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer (30).

Thereafter, the microcomputer (30) activates the common ground terminal (goes from 'high' to 'low') to activate all of the 5V, 3.3V, 12V, and power good (PWR_OK) signal lines to go to the terminals of the main board, thereby allowing various powers to be applied from the SMPS to the main board. In addition, the PS_ON# signal may be output to the SMPS (20) through the PS_ON# terminal (pin 2 of the chip) and connected to the corresponding terminal of the power connector (60) of the main board (10) through the ATX power cable, or, as in Fig. 9, the SW_OUT signal may be output to the second switching unit (41) through terminal 5 of the microcomputer, for example, and the switching signal may activate the PS_ON circuit (19a) of the super IO (19) through the power button # (13) in the main board, thereby ultimately connecting to the corresponding terminal of the power connector (60).

Meanwhile, the power control signal (PWR_CTRL) is output through pin 14 of the microcomputer (30), activates the first and third transistors (Q1, Q3) of the switching unit (40), and outputs the power output (PWR_OUT) signal to the 5V standby signal terminal of the connector of the main board (10). This ultimately means that the main board (computer) including the memory function is operating.

Finally, the voltage supplied to the memory (for example, DDR3) of the main board (10) is detected by the fourth transistor (Q4) of the detection unit (70), and the result is reported to the microcomputer through the power good (GD_PWR) terminal (pin 15 of the microcomputer chip).

The operation of the microcomputer of the fourth prior art will be described again with reference to Fig. 10.

First, in the above fourth prior art, the microcomputer (30) is operated when the system standby power is off (in a state where AC power is not input), first, it determines whether the system standby power is off (S1), and in such a case, it determines whether the PC power switch is 'on' (is the computer power switch on?) (S2), and if not, it continuously checks by feeding back after a certain period of delay, and if 'yes', it proceeds to the next step, activating the power control signal (PWR_CTRL) and outputting it to the switching unit (40), and in response, the switching unit (40) sends a power output signal (PWR_OUT) to the 5V SB terminal of the main board, thereby supplying all power to the main board (S3), and at the same time, it activates the power button # (13) and activates the PS_ON# signal, thereby operating the main board (S4').

That is, the microcomputer (30) receives a signal that the PC power switch is 'on', activates a power control signal (PWR_CTRL) to the first switching unit (40), and sends a power output signal (PWR_OUT) to the 5V SB terminal of the main board through the first switching unit (40), thereby supplying all power to the main board (S3), and at the same time outputs a switching out (SW_OUT) signal to another second switching unit (41), thereby turning on the transistor (Q2) of the second switching unit (41), and applying a PS_ON# signal to the power button (13) of the main board, thereby activating the PS_ON# terminal of the connector (60) through the power button (13) and the PS_ON circuit (19a) of the super I/O (19) of the main board, thereby ultimately operating the main board (S4').

Thereafter, the voltage (V _DD ) supplied to the memory (10a) of the main board is checked (S5), and it is determined whether it is below a certain voltage (for example, 0.7 V) (S6), and if it is above that (since the RAM is operating at this time), the 5 V SB power supply is maintained in the 'on' state to continue supplying power to the main board, and if not, the memory is recognized as having stopped operating, and the power control signal (PWR_CTRL) is deactivated and output to the switching unit (40), and in response, the switching unit (40) disables the power output signal (PWR_OUT) to turn the system standby power 'off' (S7).

That is, as described in the above prior art, in the case of S3 mode (power saving/standby mode), +5V SB should not be turned off, whereas in S4 mode (maximum power saving mode), data is saved to the hard disk and all power of the system is turned off. That is, 0V is output in S4 mode and S5 mode which is power OFF. Therefore, it is possible to check for standby power cut-off with a single VDD signal. To summarize again, in the case of power OFF and S4 mode which are system standby power OFF conditions, the VDD signal is 0V, and in the case of system operation (power ON state) and S3 (power saving/standby mode) which are standby power ON conditions, the VDD signal outputs 1.2 to 1.5V. Therefore, in the above S5 and S6 steps, the voltage (V _DD ) supplied to the memory is checked (S5), and it is determined whether it is less than a certain voltage (Vr: 0.7 V for example) (S6), and if it is more than that, the 5V SB power supply is maintained in the 'on' state, and if it is less than that (V _DD If < Vr), the system standby power is turned ‘off’ (S7).

The above-mentioned fourth prior art provides a method of recognizing the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory, and continuously supplying 5V standby power in the S3 mode where power is still required for the system such as the memory, and cutting off the standby power in the S4 mode where power is not required, thereby saving power in the dash mode. However, it has the advantage of being able to do so without additional cable work.

However, even in S3 (standby/power saving mode), except for certain modes, there is no need to supply 5V of standby power, and supplying only 3V of standby power is sufficient, but the above-mentioned 4th prior art does not provide any preparation for this.

In addition, since the above-mentioned conventional technologies checked the mode recognition of S3 and S4, etc. by the voltage of a secondary device such as a memory, a separate device for checking this was required, and furthermore, wiring or a separate cable was required from the detection device of this sensing voltage to the control microcomputer, and furthermore, although the possibility is very low, there was a problem that accurate sensing was not possible in case of a mismatch between the current mode and a secondary device such as a memory due to a system error, and in particular, although the memory, etc. should be supplied with a minimum amount of power even in sleep mode, there was insufficient countermeasure for this.

On the other hand, the inventor of the present invention, in order to solve the above problems, has proposed an energy-saving computer system that saves power by setting limits according to CPU usage as shown in FIGS. 11 to 13, by setting upper and lower limits of VID/FID as well as limits of temperature and other parameters according to CPU usage according to the current operating status of the CPU, and by operating the computer power supply device within this range, without lowering CPU performance, and has been granted a patent under Patent No. 2516672. This will be described with reference to FIGS. 11 to 13.

The computer system according to the fifth prior art, as shown in FIG. 11, comprises a main board (10) including a CPU (11), a hook driver (12), a chipset (14), a PCI (15, 15', 15"), an SPI-type firmware (17), an analog display (VGA) connector (18), an SIO (19), a system memory (10a), an OS (10c), a task scheduler (10d), a CPU core power supply (10e), a power management (PM) (10f), and a set value dB (10g); an SMPS (20) connected to the main board through an auxiliary connector (21) and a main connector (22); and various peripheral devices.

Meanwhile, a standby power supply unit consisting of a power switch (51) and power stage regulators (52 to 54) is interposed between the main board (10) and the power supply (SMPS) (20), and controls the power supply (Vcore) to the CPU and the power supply to various power stage regulators (52, 53, 54). The SIO (19) detects the current computer system power mode (S3 to S5 mode) and the current CPU operation status (C0 to C7 level) from the terminal of the CPU (11), and the sleep type signal from the chipset (14), and controls the standby power switching element (51) and the PCI (15), thereby controlling the standby power supply and various peripheral device buses such as video cards.

To explain this in more detail, depending on the type of processor core of the CPU (11) mounted on the system, each different core voltage is applied and each different frequency clock is provided to the CPU accordingly, and a table (14a) of optimal core applied voltage (VID) data and clock frequency (FID) for each processor core is stored in the firmware (17) and chipset (14). For example, in the case of a 3.2G processor, there is CPU data on how many V of core operating voltage and what frequency of clock to apply, so that when a specific processor is mounted, the processor ID is received and the CPU voltage according to the CPU type is applied. On the other hand, since even with the same CPU, the CPU usage rate varies depending on the type of program being executed, the voltage is adjusted according to the OS load, and the corresponding clock frequency is lowered accordingly, so that the power consumption of the CPU can be reduced. Moreover, going further here, when multiple apps are running simultaneously, it would be generally thought to provide voltage and clock frequency corresponding to the sum (SUM) of the CPU usage rates of each, but in the fifth prior art, considering the fact that the CPU usage rate actually becomes lower when multiple apps are running simultaneously (for example, when four different apps are each run, assuming that the CPU usage rate of each app is 1%, when the four different apps are running simultaneously, it may not be 4% but may be lower than that, for example, 3.1%), the actually measured lower CPU usage rate is converted to dB in advance, and the voltage (VID) and clock frequency (FID) are adjusted based on this, so that the power consumption of the CPU can be reduced as much as possible.

That is, by adjusting the voltage (VID) according to the CPU usage and OS load when multiple programs (apps) are executed simultaneously, and also lowering the corresponding clock frequency (FID), the CPU power consumption can be ultimately reduced. However, in order to prevent a decline in CPU function while saving power in this way, when multiple apps are running and which app is running in the first window? By setting the upper/lower limits of CPU usage and the maximum processor current (IccMAX), the upper/lower limits of the CPU FID/VID, and the upper limit of the CPU temperature (TEMP_MAX), and saving power accordingly, it is possible to save power as much as possible while maintaining the stability of the processor.

More preferably, the CPU usage for each file and the upper/lower limits of the CPU usage for the subgroup of apps that should be executed when an app is running are also set, and the peripherals that are absolutely necessary depending on the running app are called and the dB for the list of such peripherals is also secured, and the ranges of other parameters (IccMAX, FID/VID, TEMP_MAX) are also set in advance to ensure stable operation during power-saving operation.

And, in this specific procedure, first, the reference operating voltage (VID) data according to the CPU type is transmitted from the firmware (17) through the CPU core power supply (10e), and the frequency (FID) data is transmitted from the FID table (14a) of the chipset through the chipset (14) to the CPU (11), while, on the other hand, the upper/lower limits of various parameters other than the reference VID/FID stored in the set value dB (10g) and their sum (SUM) are loaded and updated by the power management (10f) and the OS (10c), and power management is performed.

Afterwards, when the actual CPU (11) starts operating, the OS (10c) receives the program to be executed next from the task scheduler (10d) and transmits it to the hook driver (12), and the hook driver writes FID data and VID data reflecting the load value of the CPU according to the executed application program (i.e., CPU usage according to the app).

In addition, the CPU core power supply (10e) changes the voltage of 12 V received from SMPS (20) into an operating voltage (Vcore) of 0.5 V to 3.04 V and supplies it to the processor core.

Ultimately, the above 'Vcore' reflects the type of the current CPU and the type of task being executed, as well as the actual CPU usage rate (load) when multiple apps are executed, and in the fifth prior art, maximum power saving can be performed reflecting the current CPU operation status without separate additional wiring.

In addition, the CPU and chipset control the standby power supply consisting of the power stage regulators (52 to 54) by turning the power switch (51) on and off by controlling the SIO (19), and control various peripheral device buses such as the video card by controlling the PCI bus, etc., and enable the VID and FID data to be updated in the case of multiple combinations of apps being newly executed.

For reference, the above standby power supply unit supplies 3VSB to the system by a regulator (53, 54) from voltage 5VSB to 3VSB, and this is done by turning on/off the switching element (51), and the PMOS FET (51) is a type of voltage regulator for stably supplying 5VSB to the system.

The undocumented symbol (10b) is a DDI (Digital Display Interface), (18') is a LAN, (71) and (72) are USB ports, (73) is a TPM, and (74) is a SATA bus.

In particular, in the system of the fifth prior art, the CPU (11) and the chipset (14) attempt to optimize standby power in standby mode in a manner programmed by the OS (10c) according to the execution of multiple apps, and as a type of background program, the power management control program PMA (Power Management Application) identifies CPU usage and CPU temperature, controls core power according to the VID and FID setting values of the CPU core power, and selectively controls the TPL (Turbo Boost Power Limits) value for each core, thereby reducing heat generation without lowering CPU performance and ultimately reducing power consumption, thereby saving energy.

To this end, the CPU temperature limit (Temp. Limit) value and the maximum processor current value (IccMAX) are set to the setting value dB (10g) and stored so that when the setting value is exceeded, the VID and FID are reset, thereby enabling the CPU core to operate stably. That is, the setting value dB (10g) stores not only CPU Usage by app and file, PU Usage for subgroups, peripheral device (Device) usage table, and usage rate sum data, but also the limits of IccMAX and TEMP_MAX and the limits of VID and FID for each situation (MAX & LOW values).

Also, the VID (Voltage Identification) of the computer is the best way to judge how much performance is being used on the CPU, and it is the most perfect factor for controlling the use of the entire computer and saving power, and the VID is composed of a code for controlling the power supplied to the CPU, and it is easy to read and change as a program, and the fact that the more stages the VID has, the more sophisticated energy saving can be achieved, so by utilizing the VID information of the VID register (VID_R), the current operating status of the CPU can be easily identified, and furthermore, by adjusting the VID stages, power saving is possible simply without lowering the CPU performance, and further, peripheral devices also save power accordingly, so that the energy consumed by the entire computer system can be reduced.

In addition, according to the energy-saving computer system that saves power by setting a limit value according to CPU usage rate of the above-mentioned fifth prior art, power is saved by considering not only the CPU usage rate of multiple running apps but also the CPU usage rate of each of multiple running files. Therefore, since the CPU usage rate is higher when running an already-written document by running an existing file than when running only an app (for example, running Hangul) to create a new document, this should be reflected.

Moreover, for specific apps, you should also consider subgroup execution apps (for example, security program execution apps that must be executed additionally in the case of execution apps of financial institutions), and you should also consider the peripheral device call list. If multiple apps are running, the 1st window is likely to have the highest CPU usage, but sometimes background apps such as downloading files from the Internet can show the highest usage, so you should consider this situation and perform power saving. Ultimately, if these processes are stored in a database, you can increase compatibility by setting a CPU usage limit based on changes in the current usage and CPU usage data regarding such changes.

Now, a method for optimizing standby power of a computer system using a switching element according to the optimal embodiment of the fifth prior art will be described mainly with reference to FIGS. 12 and 13.

As shown in Fig. 12, when the user presses the power button (13) to turn the power 'ON' and the computer system starts (S1), the switching element (SW1) (51) is turned on to supply the first standby power (5VSB) to the entire system, and the PS_ON# signal is set to 'L' to supply all operating power (3V, 5V, 12V, etc.) to various elements on the main board through the ATX power connector (22) (S2).

After that, whether the app or file runs or not? If it is determined to be running, the power saving mode after step S11 of Fig. 13 is executed, and if it is determined not to be running, the SIO checks the CPU usage together with the chipset to check whether the CPU usage rate is below a certain level (for example, 15%) (S4), and if it is above a certain first reference value (15%), it returns to step S3 and repeats the execution, and if it is below the first reference value (15%), the power saving step (S5, S6) of the fifth prior art at the highest level is executed. For example, the first operation limit range (Operation limit range_1) is set to set the CPU temperature limit value (TEMP_MAX) to the first temperature reference value (for example, 50℃) and the maximum processor current (IccMAX) limit value to 10A (S5), and then the first CPU FID/VID range (CPU FID/VID RANGE_1) is set to set the CPU FID/VID to the lowest, thereby executing the highest The power saving mode of the step is executed (S6). The first temperature reference value (T1) can be selected from any value between 50 and 80°C, but approximately 50°C is most preferable.

Additionally, in the above S6 step, optionally, additional power saving can also be performed simultaneously, and the first VGA PM (VGA PM_1) mode for peripheral power saving is set. As an example of VGA PM, 'PM_1' can be set to 'Clock down to 5% for example' and 'PLL & Transceiver sleep'.

Afterwards, it is checked whether a new app has been additionally executed (S7), and if an additional app has been executed, it waits for a certain period of time for program loading and then returns to the S3 step to repeat the execution. If not, the SIO (19) opens the first switch (SW1) (51) to prevent the 5V standby power from being supplied to the first and second regulators (52, 53), thereby effectively powering off the computer system.

Meanwhile, if it is determined in the S3 step that at least one app or file is running, the setting value dB (10g in FIG. 11) is first loaded (S11). The setting value loaded in the S11 step may include CPU usage rate, low rank processor, device usage table, and CPU usage sum data.

After the above step S11, a second operation limit range (Operation limit range_2) is set, for example, by setting the CPU temperature limit (TEMP_MAX) to a second temperature limit (e.g. 70℃) higher than the first temperature limit and setting the maximum processor current (IccMAX) limit to 30A (S12), and then setting a second CPU FID/VID range (CPU FID/VID RANGE_2) to set the CPU FID/VID higher according to the loaded CPU usage rate (CPU Usage rate) or the measured CPU usage rate of the currently running app or file, thereby executing a relatively lower level power saving mode (S13). The second temperature limit (T2) can be selected from any value between 50 and 80℃, but a high value of about 70℃ is generally most desirable.

Additionally, in the above S13 step, additional power saving can also be performed at the same time, optionally, by setting a second VGA PM (VGA PM_2) mode for peripheral power saving. As an example of VGA PM, 'PM_2' can be set to 'clock down to 30% for example'.

Continuing, in the judgment result of the above S14 step, if a new app or file is not executed, the process is repeated, and if it is determined that a new app or file is executed, whether the sum (SUM) data for the CPU usage considering the newly executed app or file is stored in the existing set value dB (10g) is determined (S15), and if stored, the CPU FID/VID range is added by reflecting the sum (SUM) data for the CPU usage (S16). As described above, even when it is assumed that four apps being executed each have a usage rate of 1%, if four apps are executed simultaneously, the overall sum usage rate is smaller than the simple sum of 4%, and furthermore, what is the 1st window? Therefore, in the case where these 4 apps are running and in the special case where a specific app is running in the 1st window, only when the above setting value dB(10g) is already stored, the stored value becomes the accurate usage rate, and the addition of CPU FID/VID ranges corresponding to that accurate usage rate becomes effective as the accurate limit value.

Thereafter, it is determined whether the CPU temperature and IccMAX exceed the limit set in step S12 (S17), and if not, it returns to step S14 and repeats the process. If not, it resets the new CPU FID/VID range to reflect the current CPU usage rate (S18), and stores the new CPU usage rate (sum) data in the set value dB (10g) to update the set value dB (10g) (S19).

Meanwhile, even if the existing sum (SUM) data does not exist as a result of the judgment in step S15, the current CPU usage rate (sum) data is stored in the setting value dB(10g) to update the setting value dB(10g) (S19).

Now, the process checks the CPU usage again to check whether the CPU usage is less than the first threshold (15%) (S20). If the CPU usage is less than the first threshold (15%), a third operation limit range (Operation limit range_3) is set, for example, by setting the CPU temperature threshold (TEMP_MAX) to a third threshold (e.g., 60℃) that is between the first temperature threshold (e.g., 50℃) and the second temperature threshold (e.g., 70℃) while also setting the maximum processor current (IccMAX) threshold to an intermediate value of 20A (S21). Then, by setting the third CPU FID/VID range (CPU FID/VID RANGE_3) that sets the CPU FID/VID relatively low, a relatively high-level power saving mode is executed, and in this case, all unused peripherals are set to sleep mode (S22). On the other hand, if the CPU usage is determined to be greater than or equal to the first criterion (15%) at step S20, the process returns to step S3 and starts again from the beginning.

Additionally, in the above S22 step, optionally, additional power saving can also be performed simultaneously, and a third VGA PM (VGA PM_3) mode for peripheral power saving can be set. As an example of VGA PM, 'PM_3' can be set to 'clock down to 15% for example' and 'PLL sleep'.

After the step S22, the process checks the CPU usage again to check whether the CPU usage is lower than the second threshold (10%) which is lower than the first threshold (15%) (S23). If the CPU usage is higher than the second threshold (10%), the process returns to the step S20 and repeats steps S20 to S22. If the CPU usage is lower than the second threshold (10%), a fourth CPU FID/VID range (CPU FID/VID RANGE_4) is set to further lower the CPU FID/VID, thereby executing a higher level of power saving mode. In this case, all unused peripheral devices are set to deep sleep mode (S24).

Thereafter, the hook driver (12) performs device hooking (S25), and if there is no keyboard or mouse operation for a certain period of time, it proceeds to the S7 step and performs power off (a detailed description of general processes such as the STR (Suspended To RAM) step in the meantime is omitted), and conversely, if there is keyboard or mouse operation for a certain period of time, it is evaluated that a type of wake-up has occurred, and it proceeds to the S3 step and repeats the operation from the beginning.

According to the energy-saving computer system and its control method that save power by setting a limit value according to the CPU usage rate of the above-mentioned fifth prior art, when multiple apps are running simultaneously, the most optimal CPU usage is expressed in dB, and the preset CPU FID/VID limit value is set accordingly, thereby enabling rapid and optimal energy saving.

However, the power saving technology by the fifth prior art also has the limitation that since it only sets the limit value of CPU FID/VID, the most optimal CPU frequency or core voltage according to the usage is not determined, and thus must be determined by another method.

Republic of Korea Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Republic of Korea Patent No. 1328393 (Title: Computer power supply unit with reduced standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power) Republic of Korea Patent No. 1815239 (Title: Device and method for optimizing standby power of a computer system using switching elements) Korean Patent No. 2516672 (Title: Power-saving computer system that sets CPU operating conditions using a linear regression model according to CPU usage rate and its control method)

The present invention relates to a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to a CPU usage rate, and a control method thereof, wherein 'user working habit data', which is different data (CPU frequency and/or core voltage) according to a user's working habits according to various running apps or files, is stored in advance, and if the currently running app (set of running apps) or files and the 'user working habit data' stored in advance exists in dB, the CPU is immediately driven according to such data, and if not, the optimal driving method (CPU frequency and/or core voltage) is set by a linear regression model according to the CPU usage rate according to the operating state of the CPU, thereby enabling optimal power saving without lowering the CPU performance, and further reducing the energy consumed in the entire computer system by also saving power according to the core temperature and peripheral devices.

According to one aspect of the present invention for achieving the above purpose, a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate is a computer system including a main board (10) including a CPU (11), a chipset (14), firmware (17), an SIO (19), and a system memory (10a), an SMPS (20) that supplies power to the main board (10), and various peripheral devices, wherein the main board (10) further includes a hook driver (10b), a task scheduler (10d), a CPU core power supply (10e), a PM (Power Management) control unit (10f), and user work habit data dB (10g), and the user work habit data dB (10g) stores CPU usage rate information according to a stored execution app or a set of execution apps and data on optimal CPU operation conditions corresponding to the usage rate information, and the chipset (14) adjusts the CPU operation conditions to the optimal conditions according to the execution app or the set of execution apps, thereby reducing CPU power consumption, but In cases where CPU usage information according to a running app or a set of running apps and optimal CPU operating condition data corresponding to the usage information are not stored, a linear regression model is utilized to set CPU operating conditions.

Preferably, the CPU operating condition is characterized by being a core voltage, a clock frequency, or both.

More preferably, the CPU operating condition is a CPU clock frequency, and an equation for measuring a CPU frequency (y GHz) value for a CPU usage rate (x %) is as shown in [Mathematical Formula 1] below, and coefficients a and b in [Mathematical Formula 1] below are characterized in that they are obtained as in [Mathematical Formula 2] and [Mathematical Formula 3] below, respectively.

[Mathematical formula 1]

[Mathematical formula 2]

[Mathematical Formula 3]

In addition, more preferably, the CPU operating condition is a CPU core voltage, and an equation for measuring a CPU core voltage (y [V]) value for a CPU usage rate (x %) is as shown in [Mathematical Formula 1'] below, and coefficients a and b in [Mathematical Formula 1'] below are characterized in that they are obtained as in [Mathematical Formula 2] and [Mathematical Formula 3] below, respectively.

[Mathematical formula 1']

[Mathematical formula 2]

[Mathematical Formula 3]

Meanwhile, a control method of a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to a CPU usage rate according to another aspect of the present invention for achieving the above-mentioned purpose is a control method of a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to the CPU usage rate, comprising: (a) a step (S1) of loading 'user work habit data' while a PM control app is executed when the computer system is started and standby power is supplied to the entire system and operating power is supplied to the main board; (b) a step (S2) of checking whether an app or file is executed after the step (a); (c) a step (S3, S4) of determining whether there is 'user work habit data' for the corresponding 'executing app' or 'executing app set' as a result of the determination in the step (b); (d) a step (S5) of omitting linear regression analysis modeling and directly setting the CPU frequency accordingly if there is 'user work habit data' for the corresponding 'executing app' or 'executing app set' as a result of the determination in the step (c); And (e) if there is no 'user work habit data' for the 'executable app' or 'executable app set' as a result of the judgment in the step (c) above, a 'frequency setting process by linear regression analysis modeling' is performed to calculate an optimal frequency for the current 'executable app' or 'executable app set' through linear regression analysis modeling.

Preferably, the step (e) comprises: (e1) a step of detecting CPU usage and frequency in real time (S21), and then checking until the frequency change becomes stable within a certain value (S22); (e2) a step of calculating the CPU usage and frequency average for the sampled values (S23) after the step (e1), if the frequency change becomes stable within a certain value; (e3) a step of calculating the slope (a) and the intercept (b) by the [Mathematical Formula 2] and the [Mathematical Formula 3] (S24) after the step (e2); (e4) a step of calculating the set frequency mathematical formula (y = ax + b) according to the linear regression model of the [Mathematical Formula 1] (S25) after the step (e3); And (e5) after the step (e4), a step (S26) of calculating a set frequency (y) suitable for the current CPU usage rate (x) by referring to the set frequency mathematical formula (y = ax + b) according to the linear regression model and storing the frequency set by the linear regression modeling in dB; is characterized in that it includes;

On the other hand, according to another aspect of the present invention for achieving the above object, a control method of a power-saving computer system for setting CPU operating conditions by utilizing a linear regression model according to a CPU usage rate is a control method of a power-saving computer system for setting CPU operating conditions by utilizing a linear regression model according to the CPU usage rate, comprising: (A) a step (S1) of loading 'user work habit data' while a PM control app is executed when the computer system is started and standby power is supplied to the entire system and operating power is supplied to the main board; (B) a step (S2) of checking whether an app or file is executed after the step (A); (C) a step (S3, S4) of determining whether there is 'user work habit data' for the corresponding 'executing app' or 'executing app set' as a result of the determination in the step (B); (D) a step (S5) of omitting linear regression analysis modeling and directly setting the CPU core voltage accordingly if there is 'user work habit data' for the corresponding 'executing app' or 'executing app set' as a result of the determination in the step (C); And (E) if there is no 'user work habit data' for the 'executable app' or 'executable app set' as a result of the judgment in the step (C) above, a step of performing a 'core voltage setting process by linear regression analysis modeling' that calculates an optimal core voltage for the current 'executable app' or 'executable app set' through linear regression analysis modeling is characterized by including;

Preferably, the step (E) comprises: (E1) a step of detecting CPU usage and core voltage in real time (S21), and then checking until the core voltage change becomes stable within a predetermined value (S22); (E2) a step of calculating the CPU usage and core voltage average for the sampled values when the core voltage change becomes stable within a predetermined value after the step (E1) (S23); (E3) a step of calculating the slope (a) and the intercept (b) by the [Mathematical Formula 2] and [Mathematical Formula 3] after the step (E2) (S24); (E4) a step of calculating the set core voltage mathematical formula (y = ax + b) according to the linear regression model of the [Mathematical Formula 1'] after the step (E3) (S25); And (E5) after the step (E4), a step (S26) of calculating a set core voltage (y) suitable for the current CPU usage rate (x) by referring to the set core voltage mathematical formula (y = ax + b) according to the linear regression model and storing the core voltage set by the linear regression modeling in dB; is characterized in that it includes;

According to the power-saving computer system and its control method which set CPU operating conditions by utilizing a linear regression model according to CPU usage rate according to the present invention, 'user work habit data' which is different data (CPU frequency and/or core voltage) according to user work habits according to various running apps or files are stored in advance, and the currently running apps (set of running apps) or files are identified, and if the pre-stored 'user work habit data' exists in dB, the CPU is immediately driven according to such data, and if not, the optimal driving method (CPU frequency and/or core voltage) is set by the linear regression model according to the CPU usage rate according to the operating state of the CPU, thereby enabling optimal power saving without lowering CPU performance, and further, by saving power according to the core temperature and peripheral devices, it is possible to reduce the energy consumed by the entire computer system.

In addition to the above objects and effects, other objects and advantages of the present invention will become apparent through a detailed description of embodiments with reference to the attached drawings.

Figure 1 is a conceptual diagram of a conventional computer power supply unit.
Figure 2 is a block diagram of a computer power supply device that reduces standby power according to the third prior art.
Figure 3 is a drawing explaining the concept of a conventional general power-on operation.
Figure 4 is a block diagram of the PS_ON circuit (19a) of Figure 3.
Figure 5 is a timing chart of each signal in Figure 3.
Figure 6 is another example drawing illustrating the concept of a conventional general power-on operation.
Figure 7 is a timing chart of each signal in Figure 6.
Figure 8 is a block diagram of a computer power supply device that reduces standby power according to the fourth prior art.
Figure 9 is a detailed circuit diagram of a computer power supply device that reduces standby power according to the fourth prior art.
Figure 10 is a flow chart of the operation of a microcomputer of a computer power supply device that reduces standby power according to the fourth prior art.
Figure 11 is a computer system configuration diagram according to the fifth prior art.
Figures 12 and 13 are flowcharts showing an operation method of a computer system according to the fourth prior art.
Figure 14 is a computer system configuration diagram according to an optimal embodiment of the present invention.
Figures 15 and 16 are flowcharts showing a method of operating a computer system according to an optimal embodiment of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

FIG. 14 is a computer system configuration diagram according to an optimal embodiment of the present invention, and FIGS. 15 and 16 are flowcharts showing an operation method of a computer system according to an optimal embodiment of the present invention.

However, it will be readily apparent to those skilled in the art that the attached drawings are merely provided to more easily disclose the contents of the present invention, and that the scope of the present invention is not limited to the scope of the attached drawings.

(Computer system according to the optimal embodiment of the present invention)

First, a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate according to an optimal embodiment of the present invention is described with reference to FIG. 14.

First, the computer system according to the present invention, as shown in FIG. 14, comprises a main board (10) including a CPU (11), a chipset (14), a peripheral device driver (15, 15', 15"), firmware (17), an analog display (VGA) connector (18), an SIO (19), a system memory (10a), a hook driver (10b), an OS (10c), a task scheduler (10d), a CPU core power supply (10e) of a PWM controller type, a PM (Power Management) control unit (10f), and user work habit data dB (10g); an SMPS (20) connected to the main board to supply power; and various peripheral devices.

Meanwhile, a standby power supply unit consisting of a CPU core power supply (10e) of a PWM controller type and a PMOS power switch (50) is interposed between the main board (10) and the power supply (SMPS) (20), and controls the supply of core power (Vcore) to the CPU and power to various power stage regulators (not shown). The SIO (19) detects the current power mode (S3 to S5 mode) of the computer system and the current CPU operation state (C0 to C7 level) from the terminal of the CPU (11), and a sleep type signal from the chipset (14), and controls the standby power switching element (50) and peripheral device drivers (15, 15', 15") such as PCI (15'), thereby controlling the standby power supply and various peripheral device buses such as video cards.

To explain this in more detail, the CPU core power supply (10e) of the PWM controller type applies different core voltages and provides different frequency clocks to the CPU according to the operating state of the CPU (11) mounted on the system. The optimal core applied voltage (VID) data and clock frequency (FID) data (10h) for the processor core are stored in the firmware (17) and/or the chipset (14). For example, since the CPU usage rate varies depending on the type of program being executed, the voltage is adjusted according to the OS load, and the corresponding clock frequency is lowered, thereby ultimately reducing the power consumption of the CPU. Moreover, going further here, when multiple apps are running simultaneously, it would be generally thought to provide voltage and clock frequency corresponding to the sum (SUM) of the CPU usage of each, but considering that the CPU usage is actually lower when multiple apps are running simultaneously (for example, when four different apps are each running, assuming that each app has a CPU usage of 1%, it may not be 4% when four different apps are running simultaneously, but may be lower than that, for example, 3.1%), the actually measured lower CPU usage is converted to dB in advance, and the voltage (VID) and clock frequency (FID) are adjusted based on this, so that the CPU power consumption can be reduced as much as possible. However, in the case where there is no such pre-stored data (10h), several peaks are specified and the optimal core input voltage (VID) data and/or clock frequency (FID) according to the CPU usage rate (%) are calculated from these, and a first-order equation is generated by a linear regression model method, and the optimal core input voltage (VID) data and/or clock frequency (FID) according to the CPU usage rate (%) is calculated from this.

More preferably, depending on the running app, the peripherals that are absolutely necessary are called and the dB for the list of such peripherals is secured, and the ranges of other parameters are also set in advance to ensure stable operation during power-saving operation.

And, in this specific procedure, first, the reference operating voltage (VID) data according to the CPU type is transmitted from the firmware (17) through the CPU core power supply (10e), and the frequency (FID) data is transmitted from the FID table of the chipset through the chipset (14) to the CPU (11), while on the other hand, the SVID/DFID data (10h) of the 'reference VID/FID' stored in the user work habit data dB (10g) is loaded and updated by the PM control unit (10f) and the OS (10c), and power management is performed.

Thereafter, when the actual CPU (11) starts operating, the OS (10c) receives the program to be executed next from the task scheduler (10d) and transmits it to the hook driver (10b), and the hook driver notifies the CPU load value (i.e., CPU usage according to the app) according to the executed application program, and the PM control unit (10f) writes 'user work habit data' including FID data and VID data reflecting this.

In addition, the CPU core power supply (10e) changes the voltage of 12 V received from the SMPS (20) into an operating voltage (Vcore) of 0.5 V to 3.04 V and supplies it to the processor core. If there is pre-stored 'user work habit data', it calculates a formula for setting the core voltage of the CPU based on its value, otherwise, it calculates a formula for setting the core voltage of the CPU using a linear regression model described later in the chipset, etc., and supplies the final operating voltage (Vcore) based on the SVID data accordingly. Similarly, if there is pre-stored 'user work habit data', it calculates a formula for setting the clock frequency of the CPU based on its value, otherwise, it calculates a formula for setting the clock frequency of the CPU using a linear regression model described later in the chipset, etc., and provides the final clock frequency based on the SFID data accordingly.

Ultimately, the above 'Vcore' reflects not only the type of task (app or file) currently being executed, but also the actual CPU usage (load) when multiple apps are being executed, and in the present invention, maximum power saving can be achieved by the most optimal voltage and/or frequency reflecting the current CPU operating state without any additional wiring.

In addition, the CPU and chipset control the standby power supply consisting of power stage regulators by turning the power switch (51) on/off by controlling the SIO (19), and control various peripheral device buses such as video cards by controlling the PCI bus, etc., and enable updating of VID and FID data in the case of multiple combinations of apps being newly executed.

For reference, the above standby power supply unit supplies 3VSB to the system by a regulator from voltage 5VSB to 3VSB, and this is done by turning on/off the switching element, and the PMOS (50) stably supplies 5VSB to the system.

The unexplained symbol (15) is LAN, (71) and (72) are USB ports, (73) is TPM, and (74) is SATA bus.

In particular, in the system of the present invention, the CPU (11) and the chipset (14) are programmed by the OS (10c) according to the execution of multiple apps to optimize standby power in standby mode, and as a type of background program, the power management (PM) control program, PMA (Power Management Application), determines CPU usage and CPU temperature, and controls the core power and/or clock frequency according to the VID and FID setting values of the CPU core power, thereby reducing heat generation without lowering the CPU performance and ultimately reducing power consumption, thereby saving energy.

To this end, the user work habit data dB (10g) that stores the CPU temperature limit (Temp. Limit) value and the 'user work habit data' for each app contains CPU usage information for each app, CPU usage linear regression model calculation variable information, frequency setting information for the same usage environment CPU, clock frequency/core voltage for CPU usage, frequency/PM data for each app, etc.

Also, the VID (Voltage Identification) of the computer is the best way to determine how much performance is being used on the CPU, and is the most perfect fact for controlling the use of the entire computer and saving power. Since the VID is composed of a code for controlling the power supplied to the CPU and is easy to read and change as a program, and since the VID has many stages, energy saving can be done more precisely. By utilizing the standard VID (SVID) information, the current operating status of the CPU can be easily identified, and furthermore, by adjusting the SVID, power saving is possible simply without lowering the CPU performance. Furthermore, by having peripheral devices save power accordingly, the energy consumed by the entire computer system can be reduced.

In addition, according to the power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage of the present invention, power is saved by considering not only the CPU usage of multiple running apps but also the CPU usage of multiple running files. Therefore, since the CPU usage is higher in the case of executing an already-written document by executing an existing file than in the case of creating a new document by executing only an app (for example, executing Hangul), this should be reflected.

Moreover, for specific apps, you should also consider subgroup execution apps (for example, security program execution apps that must be executed additionally in the case of execution apps of financial institutions), and you should also consider the peripheral device call list. If multiple apps are running, the 1st window is likely to have the highest CPU usage, but sometimes background apps such as downloading files from the Internet can show the highest usage, so you should consider this situation and perform power saving. Ultimately, if these processes are stored in a database, you can increase compatibility by setting the CPU usage and the corresponding SVID/SFID using data such as changes in the current usage and CPU usage for such changes.

Meanwhile, for power saving, it is desirable to have peripheral devices such as audio devices for each running app. This does not have much effect on CPU usage, but it is necessary for power saving for the entire system by putting the peripheral device to sleep in idle mode or turning off the power of the peripheral device.

Now, after obtaining the optimized above usage rate and the SVID/SFID according to it by loading dB(10g) or, in the case of a new combination not found in the user work habit data dB, by determining the CPU usage rate during actual execution, by linear regression modeling, the corresponding SFID/SVID data is loaded from the firmware (17) or chipset (14), and the SFID/SVID values are calculated and stored.

In order to propose a formula for setting the frequency/core voltage of a CPU using a linear regression model of the present invention, data for determining the relationship between CPU usage and frequency/core voltage is first required. Now, through an example, let's try calculating SFID/SVID data values by linear regression modeling.

(Example 1)

In this Example 1, we will explain the measurement of CPU frequency (y GHz) values for CPU usage (x %) as an example, and the relationship between the two (variables x and y) is as shown in the following [Mathematical Formula 1].

In addition, assuming that there are several pairs of data (for example, 5 pairs) as in [Table 1], the coefficients a and b in [Mathematical Formula 1] are obtained as in the following [Mathematical Formula 2] and [Mathematical Formula 3], respectively.

First, stable frequency values at various CPU usage rates are measured, for example, peak-to-peak values of the waveform are sampled. The assumed data of the sampled values are shown in [Table 1].

)을 [수학식 4]에 의하여 계산한다.Now, in order to obtain the coefficients a and b of [Mathematical Formula 1] according to the linear regression model from the sampling values (xi, yi) of [Table 1], the average values of xi and yi (

) is calculated using [Mathematical Formula 4].

=

및

=

을 구하는바, 이를 [표 2]에 나타내었다.Afterwards, in order to obtain the coefficient a value by [Mathematical Formula 2],

=

and

=

, which is shown in [Table 2].

Next, the coefficients a and b corresponding to the slope and intercept of the linear regression model are obtained as in [Mathematical Formula 5].

With this, the final frequency setting model is completed, and the equation for the linear regression model finally obtained through calculation is as shown in [Mathematical Formula 6].

Now, using the above [Mathematical Formula 6], the CPU frequency for various CPU usage rates can be predicted. For example, the expected optimal frequency (yi) when the CPU usage rate (xi) is 10% is 1.9 [GHz] as in [Mathematical Formula 7].

Ultimately, by adjusting the CPU frequency to suit various CPU usage rates in an actual system through the above linear regression model, the energy efficiency of the system can be increased and the performance of the system can be optimized.

(Example 2)

Meanwhile, in this Example 2, the measurement of CPU core voltage (y V) values for CPU usage rate (x %) is explained as an example. The relationship between the two (variables x, y) is as in the above [Mathematical Formula 1'], and assuming several pairs of data (for example, 5 pairs) as in [Table 3], the coefficients a and b in the above [Mathematical Formula 1'] are obtained as in the above [Mathematical Formula 2] and [Mathematical Formula 3], respectively.

[Mathematical formula 1']

In addition, stable core voltage values at various CPU usage rates are measured, and the assumed data of the sampled values are shown in [Table 3] as an example.

)을 [수학식 8]에 의하여 계산한다.Now, in order to obtain the coefficients a and b of [Mathematical Formula 1] according to the linear regression model from the sampling values (xi yi) of [Table 3], the average values of xi and yi (

) is calculated using [Mathematical Formula 8].

=

및

=

을 구하는바, 이를 [표 4]에 나타내었다.Afterwards, in order to obtain the coefficient a value by the above [Mathematical Formula 2],

=

and

=

, which is shown in [Table 4].

Next, the coefficients a and b corresponding to the slope and intercept of the linear regression model are obtained as in [Mathematical Formula 9].

With this, the final frequency setting model is completed, and the equation for the linear regression model finally obtained through calculation is as shown in [Mathematical Formula 6].

Now, using the above [Mathematical Formula 9], the CPU core voltage for various CPU usage rates can be predicted. For example, the expected optimal core voltage (yi) when the CPU usage rate (xi) is 10% is 1.0667 [V] as in [Mathematical Formula 10].

Ultimately, by adjusting the CPU core voltage according to various CPU usage rates in an actual system through the above linear regression model, the energy efficiency of the system can be increased and the performance of the system can be optimized.

(Control method of a computer system according to an optimal embodiment of the present invention)

Now, a control method of a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate according to an optimal embodiment of the present invention will be described mainly with reference to FIGS. 15 and 16, and supplementarily with reference to FIG. 14.

First, as shown in Fig. 15, when the user presses the power button to turn the power 'ON' and the computer system starts, the switching elements such as PMOS (50) are turned on to supply standby power (5VSB) to the entire system, and all operating power (3V, 5V, 12V, etc.) is supplied to various elements on the main board through the ATX power connector (S0), and the PM control app is executed to load 'user work habit data' (S1).

Afterwards, whether a 'single app or file' is running is checked (S2), and if it is determined that a 'single app or file' is running, whether there is 'user work habit data' for the 'running app' is determined (S3), and if there is, (linear regression analysis modeling is omitted) the CPU frequency is set accordingly (S5).

Meanwhile, if it is determined in the S2 step that a 'single app or file' is not being executed, it is determined that the 'executing app set' of composite apps is being executed, and it is determined whether there is 'user work habit data' for the 'executing app set' (S4). If there is, the CPU frequency is set accordingly (omitting linear regression analysis modeling) (S5). However, since most recent general programs in the Windows environment often execute background programs or other apps simultaneously, the S2 step can be omitted and the S4 step can be proceeded directly.

After the above step S5, it is additionally checked whether a new app is running (S6), and if a new app is running, it waits for a certain period of time for program loading, returns to the S2 step and repeats the process. If not, it is checked whether the core temperature is lower than the first reference value (T1) (S7), and if it is determined not to be so (overheating state), the core clock frequency (f) is increased to a certain value (for example, 10 MHz) (S8), and the check is repeated until it drops to the first reference value (T1).

On the other hand, if the core temperature is lower than the first reference value (T1), it is checked whether it is in an idle state (S9), and if not, it is performed repeatedly, and if it is in an idle state, the power to the PCI devices is turned off (S10), the power including the standby power is turned off (S11), and the process is terminated.

On the other hand, if there is no 'user work habit data' for the corresponding execution app or 'execution app set' as a result of the judgment in the S3 or S4 step, the 'frequency setting process by linear regression analysis modeling' described above is performed.

First, in order to measure a stable frequency value at various CPU usage rates, the CPU usage rate and frequency are detected in real time (S21), and then it is checked whether the frequency change is stable within a certain value (for example, within 3%) (S22).

Accordingly, in the case of instability in the judgment result in the above step S22, the process is repeated from the above step S21, and in the case of stability, the CPU usage rate and frequency average are calculated (S23). The frequency average is performed for sampling 5 'peak-to-peak' values as exemplified in the above [Table 1], as in [Mathematical Formula 4], for example.

Thereafter, as in the above [Table 2] and [Mathematical Formula 5], the slope (a) and the intercept (b) are calculated (S24), and the set frequency mathematical formula (y = ax + b) according to the linear regression model as in [Mathematical Formula 6] is derived (S25), and with reference to this, the set frequency (f) suitable for the current CPU usage rate (x) is calculated as in [Mathematical Formula 7], and the frequency set by the linear regression modeling is stored in dB (S26).

For reference, the frequency set by the linear regression modeling of the present invention is preferably set as low as possible to maximize power saving, and thus the core temperature may become higher than the second reference value (T2), which is an allowable value. Accordingly, as a countermeasure for this, a check is made (S27) to see whether the core temperature is lower than the second reference value (T2), and if not (in case of an overheated state), the core clock frequency (f) is increased to a certain value (for example, 10 MHz) (S28), and the checking is repeated until it drops to the second reference value (T2).

On the other hand, if the core temperature is lower than the second reference value (T2), a check is made to see if there are any non-working PCI devices (S29), and if not, the process is repeated, and if there are any non-working PCI devices, the non-working PCI devices are put to sleep (S30).

Afterwards, it checks whether a new app is running (S31), and if a new app is not running, it continues to check, and if a new app is running, it returns to the beginning (step S2 above).

According to the power-saving computer system and its control method that sets CPU operating conditions by utilizing a linear regression model according to the CPU usage rate of the present invention, the CPU is operated according to 'user work habit data' which is different data (CPU frequency and/or core voltage) depending on the user's work habits according to various running apps or files, and when such data is not present, the optimal operation method (CPU frequency and/or core voltage) according to the CPU usage rate is set by the linear regression model, thereby having the advantage of enabling optimal power saving without lowering the CPU performance.

(variant example)

Finally, in the embodiment of the control method described above, the CPU clock frequency (y GHz) for the CPU usage rate (x %) was explained as an example as in (Example 1) above, but instead of the CPU clock frequency (y GHz) as in (Example 2) above, the CPU core voltage (y [V]) may be set, or both the CPU clock frequency (y GHz) and the CPU core voltage (y [V]) may be set in the same manner.

Although the present invention has been described above according to one embodiment of the present invention, it is obvious that changes and modifications made by a person having ordinary skill in the art to which the present invention pertains within a scope that does not depart from the technical spirit of the present invention also belong to the present invention.

(4th prior art)
10 : Main Board
11: CPU 12: SIO (System IO)
13: Power Button 14: Chipset
15: Reset button 16: 1st battery
17: Reset 18: LAN
19: Super IO 19a: PS_ON Circuit
20: Power supply (SMPS) 30: Microcomputer
40: 1st switching unit 41: 2nd switching unit
50 : Case power switch 60 : Power connector
70 : V _DD detection unit
(5th prior art) (Fig. 11)
10 : Main Board
10a: System Memory 10b: DDI (Digital Display Interface)
10c: OS 10d: Task Manager
10e: Power Management
10f: Setpoint dB
11: CPU 12: Hook Driver
14: Chipset 15: PCI Bus
17: SPI Flash 18: VGA
18': LAN 19: SIO (Super IO)
20: Power supply (SMPS) 21: Auxiliary power supply (5VSB)
22 : Main converter
51: Switching element 52: PMOS FET
53, 54 : Regulator
71, 72: USB port 73: TPM (Trusted Platform Module)
74 : SATA
(Present invention) (Fig. 14)
10 : Main Board
10a: System Memory 10b: Hook Driver
10c: OS 10d: Task Manager
10e: CPU core power supply (PWM controller)
10f: PM(Power Management) Control Unit
10g: User work habits data dB
10h: Linear regression model frequency setting data
11: CPU 14: Chipset
15 : LAN 15' : PCI bus
17: Firmware 18: Analog Display (VGA) Connector
19: SIO (Super IO)
20: Power Supply (SMPS)
50 : PMOS
53, 54 : Regulator
71, 72: USB port 73: TPM (Trusted Platform Module)
74 : SATA

Claims (8)

A computer system including a main board (10) including a CPU (11), a chipset (14), firmware (17), SIO (19) and system memory (10a), an SMPS (20) that supplies power to the main board (10), and various peripheral devices.
The above main board (10) further includes a hook driver (10b), a task scheduler (10d), a CPU core power supply (10e), a PM (Power Management) control unit (10f), and user work habit data dB (10g).
The above user work habit data dB (10g) stores CPU usage information according to the saved running app or set of running apps and data on optimal CPU operation conditions corresponding to the usage information.
The above chipset (14) reduces CPU power consumption by adjusting the CPU operating conditions to the optimal conditions according to the running app or the set of running apps. However, if the CPU usage rate information and the optimal CPU operating condition data corresponding to the usage rate information according to a specific running app or the set of running apps are not stored, the CPU operating conditions are set using a linear regression model.
The above CPU operating conditions include CPU clock frequency.
The formula for measuring the CPU frequency (y GHz) value for the CPU usage rate (x %) is as shown in [Mathematical Formula 1] below, and the coefficients a and b in [Mathematical Formula 1] below are obtained as in [Mathematical Formula 2] and [Mathematical Formula 3] below, respectively.
In the following [Mathematical Formula 2] and [Mathematical Formula 3], the average values (xi,yi) of CPU usage (x %) and CPU frequency (y GHz) ) is a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage, characterized in that the CPU usage and CPU frequency are averages of multiple sampling values that sample the 'peak-to-peak' value of the waveform when the frequency change is stable within a certain value.
[Mathematical Formula 1]

[Mathematical formula 2]

[Mathematical Formula 3]
A computer system including a main board (10) including a CPU (11), a chipset (14), firmware (17), SIO (19) and system memory (10a), an SMPS (20) that supplies power to the main board (10), and various peripheral devices.
The above main board (10) further includes a hook driver (10b), a task scheduler (10d), a CPU core power supply (10e), a PM (Power Management) control unit (10f), and user work habit data dB (10g).
The above user work habit data dB (10g) stores CPU usage information according to the saved running app or set of running apps and data on optimal CPU operation conditions corresponding to the usage information.
The above chipset (14) reduces CPU power consumption by adjusting the CPU operating conditions to the optimal conditions according to the running app or the set of running apps. However, if the CPU usage rate information and the optimal CPU operating condition data corresponding to the usage rate information according to a specific running app or the set of running apps are not stored, the CPU operating conditions are set using a linear regression model.
The above CPU operating conditions include CPU core voltage,
The formula for measuring the CPU core voltage (y [V]) value for the CPU usage rate (x %) is as shown in [Mathematical Formula 1'] below, and the coefficients a and b in [Mathematical Formula 1'] below are obtained as in [Mathematical Formula 2] and [Mathematical Formula 3] below, respectively.
In the following [Mathematical Formula 2] and [Mathematical Formula 3], the average values (xi, yi) of CPU usage rate (x %) and CPU core voltage (y [V]) ) is a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage, characterized in that the CPU usage and CPU core voltage average values for multiple sampling values that sample the 'peak-to-peak' value of the waveform when the frequency change is stable within a certain value.
[Mathematical formula 1']

[Mathematical formula 2]

[Mathematical Formula 3]
In the second paragraph,
A power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage, characterized in that the above CPU operating conditions further include a CPU clock frequency obtained by the following [Mathematical Formula 1].
[Mathematical Formula 1]
In paragraph 1,
A power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage, characterized in that the above CPU operating conditions further include a CPU core voltage obtained by the following [Mathematical Formula 1'].
[Mathematical formula 1']
A control method for a power-saving computer system that sets CPU operating conditions by using a linear regression model according to the CPU usage rate of Article 1,
(a) When the computer system starts and supplies standby power to the entire system and operating power to the main board, the PM control app is executed and loads ‘user work habit data’ (S1);
(b) After step (a), a step (S2) of checking whether the app or file is running;
(c) a step (S3, S4) for determining whether, as a result of the judgment in step (b), there is ‘user work habit data’ for the ‘execution app’ or ‘execution app set’;
(d) If, as a result of the judgment in step (c) above, there is 'user work habit data' for the 'execution app' or 'execution app set', the linear regression analysis modeling is omitted and the CPU frequency is set accordingly (S5); and
(e) If, as a result of the judgment in step (c) above, there is no ‘user work habit data’ for the ‘executable app’ or ‘executable app set’, a ‘frequency setting process by linear regression analysis modeling’ is performed to calculate the optimal frequency for the current ‘executable app’ or ‘executable app set’ through linear regression analysis modeling.
A control method for a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate, characterized in that it includes. In the fifth paragraph, step (e) comprises:
(e1) After detecting CPU usage and frequency in real time (S21), a step of checking until the frequency change stabilizes within a certain value (S22);
(e2) After the step (e1) above, if the frequency change is stable within a certain value, a step (S23) is performed to calculate the CPU usage rate and frequency average value for the sampled values;
(e3) After the step (e2), a step (S24) of calculating the slope (a) and the intercept (b) by the above [Mathematical Formula 2] and [Mathematical Formula 3];
(e4) After the step (e3) above, a step (S25) of calculating a set frequency mathematical formula (y = ax + b) according to the linear regression model of the above [Mathematical Formula 1]; and
(e5) After the step (e4), a step (S26) of calculating a set frequency (y) suitable for the current CPU usage rate (x) by referring to the set frequency mathematical formula (y = ax + b) according to the linear regression model and storing the frequency set by the linear regression analysis modeling in dB;
A control method for a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate, characterized in that it includes. A control method for a power-saving computer system that sets CPU operating conditions by using a linear regression model according to the CPU usage rate of the second clause,
(A) When the computer system starts and supplies standby power to the entire system and operating power to the main board, the PM control app is executed and loads ‘user work habit data’ (S1);
(B) After the step (A) above, a step (S2) of checking whether the app or file is running;
(C) A step (S3, S4) for determining whether there is ‘user work habit data’ for the ‘execution app’ or ‘execution app set’ as a result of the judgment in the above step (B);
(D) If there is 'user work habit data' for the 'execution app' or 'execution app set' as a result of the judgment in the above step (C), a step (S5) in which linear regression analysis modeling is omitted and the CPU core voltage is set accordingly; and
(E) If, as a result of the judgment in step (C) above, there is no ‘user work habit data’ for the ‘executable app’ or ‘executable app set’, a step of performing a ‘core voltage setting process by linear regression analysis modeling’ to calculate the optimal core voltage for the current ‘executable app’ or ‘executable app set’ through linear regression analysis modeling is performed;
A control method for a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate, characterized in that it includes. In the 7th paragraph, the step (E) is,
(E1) Step of detecting CPU usage and core voltage in real time (S21), then checking until core voltage change stabilizes within a certain level (S22);
(E2) After the step (E1) above, if the core voltage change is stable within a certain value, a step (S23) is performed to calculate the CPU usage rate and the core voltage average value for the sampled values;
(E3) After the step (E2), a step (S24) of calculating the slope (a) and intercept (b) by the above [Mathematical Formula 2] and [Mathematical Formula 3];
(E4) After the step (E3) above, a step (S25) of calculating a set core voltage mathematical formula (y = ax + b) according to the linear regression model of the above [Mathematical Formula 1']; and
(E5) After the step (E4), a step (S26) of calculating a set core voltage (y) suitable for the current CPU usage rate (x) by referring to the set core voltage mathematical formula (y = ax + b) according to the linear regression model and storing the core voltage set by the linear regression analysis modeling in dB;
A control method for a power-saving computer system that sets CPU operating conditions by utilizing a linear regression model according to CPU usage rate, characterized in that it includes.