KR102816978B1 - Digital to analog converter - Google Patents

Abstract

A digital-to-analog converter for converting a digital signal of L bits into an analog signal comprises: a multi-phase clock generation unit for receiving a reference clock signal and generating M clock signals having different phases; a pulse width modulation unit for receiving a signal of lower M bits of the L bits and generating a pulse signal having a pulse width corresponding to a value of the signal of the M bits; a signal generation unit for receiving the pulse signal and a signal of upper N bits of the L bits and generating and outputting a digital signal of N bits corresponding to the digital signal of the L bits; a conversion unit for converting an output of the signal generation unit into an analog signal; and an integration filter unit for integrating the output of the conversion unit.

Description

Digital to Analog Converter{DIGITAL TO ANALOG CONVERTER}

Embodiments disclosed herein relate to a digital-to-analog converter.

There are many different types of digital-to-analog converters (DACs), each with different characteristics. The main types of DACs and their characteristics are as follows:

(1) Binary Weighted Resistor DAC: Uses a resistor network with weights corresponding to each bit. It is one of the simplest and most intuitive methods, but requires a large number of resistors when high resolution is required, and the accuracy of each resistor is important.

(2) R-2R ladder DAC: It is constructed using only two resistor values (R and 2R). This method can achieve high resolution with a relatively small number of resistors, and is less sensitive to the accuracy of the resistors.

(3) Sigma-Delta DAC: Uses noise shaping to shift low-frequency noise to high-frequency noise. This method is suitable for audio and high-resolution data conversion, and provides very high resolution and excellent SNR.

(4) Current Steering DAC: Suitable for high-speed operation, mainly used in communication systems and high-speed signal processing. It operates by switching the current source and provides a very fast conversion speed.

(5) PWM (Pulse Width Modulation) DAC: PWM modulates the width of the signal (pulse width) at the digital output pin and converts it into an analog signal.

However, when implementing a digital-to-analog converter of 16 bits or more, resistance and current mismatching may occur, which may require process trim or increase the chip size. In addition, when implementing a high-precision digital-to-analog converter, the problem of a decrease in the data conversion frequency may occur.

The embodiments disclosed in this specification are intended to solve the technical problems described above, and the purpose thereof is to provide a digital-to-analog converter having a high bit rate and a high data conversion frequency.

A digital-to-analog converter for converting a digital signal of L bits into an analog signal according to an embodiment of the present invention may include a pulse width modulation unit for receiving a signal of lower M bits of the L bits and generating a pulse signal having a pulse width corresponding to a value of the signal of the M bits; a signal generation unit for receiving the pulse signal and a signal of upper N bits of the L bits and generating and outputting a digital signal of N bits corresponding to the digital signal of the L bits; a conversion unit for converting an output of the signal generation unit into an analog signal; an integration filter unit for integrating an output of the conversion unit; and a multi-phase clock generation unit for receiving a reference clock signal and generating M clock signals having different phases.

The above pulse width modulation unit further receives the M clock signals and generates the pulse signal.

Specifically, the pulse width modulation unit generates the pulse signal that is activated for a period corresponding to the value of the M bit signal among the periods of one cycle of the first signal, wherein the first signal is a signal generated by dividing one of the M clock signals.

That is, the pulse width modulation unit generates, by using the first signal and the M clock signals, a first pulse signal that is activated during a section corresponding to a value of the M bit signal or less among one ½ period of the first signal. In addition, the pulse width modulation unit generates, by using the inverted signal of the first signal and the M clock signals, a second pulse signal that is activated during a section corresponding to a value of the M bit signal or less among another ½ period of the first signal, excluding a section in which the first pulse signal is activated. In addition, the pulse width modulation unit generates the pulse signal by outputting the first pulse signal during one ½ period of the first signal and outputting the second pulse signal during another ½ period of the first signal.

The above multi-phase clock generation unit is configured to include a reference time measuring unit that receives the reference clock signal and measures a reference time value corresponding to a 1/T period of the reference clock signal; and a multi-phase clock generator that calculates a phase difference value between the M clock signals from the reference time value and generates the M clock signals having different phases using the phase difference value.

In addition, the signal generation unit is configured to include a second multiplexer, wherein the second multiplexer selects one of the signals of the upper N bits of the L bits or a signal greater by 1 than the signal of the upper N bits, using the pulse signal as a selection signal, and outputs a digital signal of the N bits.

According to the digital-to-analog converter, high bit and high data conversion frequency can be implemented.

Figure 1 is a block diagram of a digital-to-analog converter according to one embodiment.
Figure 2 is an example of an output waveform of a converter according to one embodiment.
Figure 3 is a Bode plot of the gain and phase of the integral filter section according to frequency.
Figure 4 is a configuration diagram of a multi-phase clock generation unit according to an embodiment.
Figure 5 is a configuration diagram of each of a plurality of delay cells according to one embodiment.
Figure 6 is an example diagram of the output waveforms of the first delay cell chain circuit and the second delay cell chain circuit.
Figure 7 is an example of the waveforms of M clock signals.
Fig. 8 is a configuration diagram of a pulse width modulation unit according to an embodiment.
Figure 9 is an example of waveforms of major nodes of a pulse width modulation unit according to one embodiment.
Figure 10 is a configuration diagram of a signal generation unit according to an embodiment.

Hereinafter, a digital-to-analog converter according to an embodiment of the present disclosure will be described in detail with reference to the attached drawings. It should be noted that the following embodiments of the present disclosure are intended only to concretize the present disclosure and do not limit or restrict the scope of the rights of the present disclosure. It is interpreted that what a specialist in the technical field to which the present disclosure belongs can easily infer from the detailed description and embodiments of the present disclosure falls within the scope of the rights of the present disclosure.

First, Fig. 1 shows a configuration diagram of a digital-to-analog converter (1000) according to one embodiment.

Each component of the digital-to-analog converter (1000) according to one embodiment may be implemented by one of an analog circuit, a digital circuit, and a combination of an analog circuit and a digital circuit. In addition, in some cases, at least a part of some components of each component of the digital-to-analog converter (1000) according to one embodiment may be implemented using at least some processors.

Additionally, the digital-to-analog converter (1000) according to one embodiment may be implemented as at least a portion of one semiconductor chip, or may be implemented by a combination of at least a portion of one semiconductor chip and an external configuration.

A digital-to-analog converter (1000) according to one embodiment converts a digital signal of L bits into an analog signal.

As can be seen from FIG. 1, a digital-to-analog converter (1000) according to an embodiment includes a multi-phase clock generation unit (100), a pulse width modulation unit (200), a signal generation unit (300), a conversion unit (400), an integral filter unit (500), and an amplifier unit (600).

A multi-phase clock generation unit (100) receives a reference clock signal and generates M clock signals having different phases.

The pulse width modulation unit (200) receives M clock signals and a signal of the lower M bits among L bits, and generates a pulse signal having a pulse width corresponding to the value of the signal of the M bits. The pulse width corresponding to the value of the signal of the M bits can be implemented as active high or active low. That is, the activation section of the pulse corresponding to the value of the signal of the M bits can be a high or low section. M and N are each a natural number greater than or equal to 3. In addition, L has a value that is the sum of M and N.

The signal generation unit (300) receives a pulse signal and a signal of the upper N bits among L bits, generates a digital signal of N bits corresponding to the digital signal of L bits, and outputs the same.

The conversion unit (400) receives the output of the signal generation unit (300), i.e., an N-bit digital signal, and converts it into an analog signal. The conversion unit (400) can be implemented using an R-2R ladder DAC.

The integral filter unit (500) integrates the output of the conversion unit (400) by the integral filter and outputs it.

In addition, the amplifier unit (600) amplifies and outputs the output of the integral filter unit (500).

Fig. 2 shows an example of an output waveform of a converter (400) according to an embodiment. In addition, Fig. 3 shows a Bode plot regarding the gain and phase of an integral filter (500) according to frequency.

In FIGS. 2 and 3, one cycle of the pulse width modulation unit (200) is assumed to be 1 MHz, the reference clock signal is assumed to be 16 MHz, and the data conversion frequency is assumed to be 5 kHz.

Let us assume that L is 18. That is, let us assume that the digital-to-analog converter (1000) according to one embodiment receives an 18-bit digital signal. When the conversion unit (400) outputs 2 Vp-p, the least significant bit of the lower M bits corresponds to the size of the output voltage of the conversion unit (400) of about 7.5 uV.

In addition, the least significant bit of the upper N bits corresponds to the size of the output voltage of the conversion unit (400) of about 2 mV. When the output of the output voltage of the conversion unit (400) of 2 mV is set to 5 kHz with the fc of the integral filter of the integral filter unit (500) having two poles based on the data conversion frequency of 5 kHz, the least significant bit of the lower M bits of 7.5 uV can be implemented by the integral filter of the integral filter unit (500) of -40 dB or higher. For example, the integral filter unit (500) can be implemented at -40 dB at 1 MHz by a resistor of 2 MOhm and a capacitor of 50 pF.

For reference, in Fig. 2, N is 10, the signal value of N bits is 200 in hexadecimal, and the value obtained by adding 1 is 201 in hexadecimal, respectively. In addition, in Fig. 2, M is 10, and the signal values of M bits are 80, 10, and F0 in hexadecimal, respectively. When the signal value of M bits is 80, due to the role of the pulse width modulation unit (200), the signal value of N bits plus 1 is output during 50% of the entire section, and the signal value of N bits is output as it is during the remaining 50% of the section. It can be confirmed from Fig. 2 that a digital signal of N bits corresponding to a digital signal of L bits is generated by receiving a pulse signal and a signal of the upper N bits among L bits.

The operation of the multi-phase clock generation unit (100) according to an embodiment will be specifically described below.

Figure 4 shows a configuration diagram of a multi-phase clock generation unit (100) according to one embodiment.

As can be seen from FIG. 4, a multi-phase clock generation unit (100) according to an embodiment is configured to include a reference time measuring unit (110) and a multi-phase clock generator (120).

The reference time measuring device (110) receives a reference clock signal and measures a reference time value, which is a value corresponding to 1/T cycle of the reference clock signal. T is a natural number greater than or equal to 1. For example, when T is 2, the reference time value corresponds to ½ cycle of the reference clock signal.

Specifically, the operation of the reference time measuring device (110) according to one embodiment will be described in detail.

A reference time measuring device (110) according to an embodiment may be configured to include a first delay cell chain circuit (111), a second delay cell chain circuit (112), a flip-flop (113), and an up-down counter (114).

The first delay cell chain circuit (111) and the second delay cell chain circuit (112) each include a plurality of first delay cells (dc1) and second delay cells (dc2) that are connected in series. However, the first delay cell (dc1), the second delay cell (dc2), and the third delay cell (dc3) to be described later are delay cells (dc) having the same structure, and will be described using the term “delay cell (dc)” interchangeably when necessary. For reference, the first delay cell chain circuit (111) and the second delay cell chain circuit (112) may have the same configuration, but only the selection signals may be different from each other.

Figure 5 shows a configuration diagram of each of a plurality of delay cells (dc) according to one embodiment.

Each of the plurality of delay cells (dc) can output an input signal by delaying the delay time (dt) unique to the delay cell (dc) or output the input signal without delay according to a selection signal, i.e., a control signal (S). For example, if the case where the control signal is high is called an activated state, each delay cell (dc) can delay the input signal by the delay time unique to the delay cell (dc) by a high control signal and output the input signal without delay by a low control signal.

The inherent delay time of each of the plurality of delay cells (dc) can be designed differently from each other. That is, based on the inherent delay time of one of the plurality of delay cells (dc), the remaining delay cells (dc) can be designed to have inherent delay times that are increased by a multiple of 2. For example, in the case where six delay cells (dc) are sequentially connected, such as the first delay cell chain circuit (111) and the second delay cell chain circuit (112) of FIG. 4, if the inherent delay time of the delay cell (dc) at the frontmost stage is designed to be 1 ns, the inherent delay times of the remaining five delay cells (dc) can be designed to be 2 ns, 4 ns, 8 ns, 16 ns, and 32 ns, respectively. Alternatively, if the inherent delay time of the delay cell (dc) at the frontmost stage is designed to be 32 ns, the inherent delay times of the remaining five delay cells (dc) can be designed to be 16 ns, 8 ns, 4 ns, 2 ns, and 1 ns, respectively.

The first delay cell chain circuit (111) can delay or output a reference clock signal without delay by using a plurality of first delay cells (dc1). Each of the plurality of first delay cells (dc1) included in the first delay cell chain circuit (111) uses one bit of the total bits of the reference time value output from the up-down counter (114) as each control signal. That is, depending on the bit value of the corresponding control signal, the input signal is output with a delay time unique to the corresponding first delay cell (dc1) or without delay. The size of the unique delay time of each of the plurality of first delay cells (dc1) is sequentially used as a control signal starting from the least significant bit of the total bits of the reference time value. That is, when six first delay cells (dc1) are sequentially connected as in Fig. 4, and the unique delay time of the first delay cell (dc1) at the very front is designed to be 1 ns, and the unique delay times of the remaining five first delay cells (dc1) are designed to be 2 ns, 4 ns, 8 ns, 16 ns, and 32 ns, respectively, the least significant bit of the 6-bit reference time value is used as the control signal of the first delay cell (dc1) at the very front, and the most significant bit of the 6-bit reference time value is used as the control signal of the first delay cell (dc1) at the very back.

For reference, in the case of the first delay cell chain circuit (111) at the very front, the input signal becomes the reference clock signal, and in the case of the first delay cell (dc1) other than the first delay cell (dc1) at the very front, the input signal becomes the output of the first delay cell (dc1) at the previous front.

The second delay cell chain circuit (112) can delay or output a reference clock signal without delay by using a plurality of second delay cells (dc2). All control signals of the plurality of second delay cells (dc2) included in the second delay cell chain circuit (112) can be set to 0. Accordingly, each of the plurality of second delay cells (dc2) of the second delay cell chain circuit (112) can output an input signal without delay. For reference, in the case of the second delay cell (dc2) at the frontmost stage in the second delay cell chain circuit (112), the input signal becomes the reference clock signal, and in the case of the second delay cells (dc2) other than the second delay cell (dc2) at the frontmost stage, the input signal becomes the output of the second delay cell (dc2) at the previous stage.

The flip-flop (113) may be, for example, a D flip-flop. The flip-flop (113) receives one of the outputs of the first delay cell chain circuit (111) and the second delay cell chain circuit (112) as data, and receives the other of the outputs of the first delay cell chain circuit (111) and the second delay cell chain circuit (112) as a clock.

In addition, the up-down counter (114) uses the reference clock signal as a clock, receives the output of the flip-flop (113), counts it, and outputs the reference time value. For reference, the up-down counter (114) is illustrated as 6 bits in FIG. 4. The up-down counter (114) can be designed to increase the reference time value, which is a counting value, if the output of the flip-flop (113) is 0, and decrease it if it is 1. Finally, in the example of FIG. 4, the reference time value corresponds to ½ the cycle of the reference clock signal.

Figure 6 is an example diagram of the output waveforms of the first delay cell chain circuit (111) and the second delay cell chain circuit (112).

Since the output of the up-down counter (114) is again used as a control signal for the first delay cell chain circuit (111), the output of the first delay cell chain circuit (111) ultimately appears in the form of an inverted reference clock signal.

Finally, the output of the first delay cell chain circuit (111) is locked in the form of an inverted reference clock signal, and accordingly, the reference time value, which is the output of the up-down counter (114), also becomes a value corresponding to ½ the cycle of the reference clock signal.

A multi-phase clock generator (120) calculates phase difference values between M clock signals from a reference time value and generates M clock signals using the phase difference values.

Fig. 7 shows an example of the waveforms of M clock signals. However, in Fig. 7, M is illustrated as 8.

Specifically, the multi-phase clock generator (120) is configured to include a phase difference value calculator (121), a first phase delay chain circuit (122_1) to an M-th phase delay chain circuit (122_M).

The phase difference value calculator (121) calculates the phase difference value between M clock signals from the reference time value. When the reference time value corresponds to ½ cycle of the reference clock signal and M is 8, the phase difference value calculator (121) can calculate the quotient of the reference time value divided by 4 as the phase difference value. In other words, the phase difference value calculator (121) can calculate a preset number of upper bits among the total bits of the reference time value that shifts the total bits of the reference time value to the right by a preset amount as the phase difference value.

The first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) each include a plurality of third delay cells (dc3) that are connected in series. The characteristics of the plurality of third delay cells (dc3) included in the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) are as described with reference to FIG. 5. However, unlike the first delay cell chain circuit (111) that uses all bits of the reference time value, the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) only use some of the upper bits of the total bits of the reference time value, and therefore the number of the plurality of third delay cells (dc3) can be determined by the number of bits of the phase difference value.

In addition, the unique delay time of each of the plurality of third delay cells (dc3) included in the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) needs to be set to be the same as that of the first delay cell (dc1) that uses the lower bit of the total bits of the reference time value of the first delay cell chain circuit (111) corresponding to the number of bits of the phase difference value as a control signal.

For example, when the number of bits of the phase difference value is 4 bits, it is necessary to configure the first phase delay chain circuit (122_1) to the Mth phase phase delay chain circuit (122_M) to include a third delay cell (dc3) having the same unique delay time as the first delay cell (dc1) that uses the four lower bits of the 6-bit reference time value of the first delay cell chain circuit (111) as a control signal.

That is, when the unique delay time of each of the plurality of first delay cells (dc1) of the first delay cell chain circuit (111) is designed to be 1 ns, 4 ns, 8 ns, 16 ns, and 32 ns, the unique delay time of each of the plurality of third delay cells (dc3) of the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) needs to be designed to be 1 ns, 4 ns, 8 ns, and 16 ns.

In addition, the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) are sequentially connected in series. Each of a plurality of third delay cells (dc3) included in each of the first phase delay chain circuits (122_1) to the M-th phase phase delay chain circuits (122_M) uses one bit of the total bits of the phase difference value as a control signal, and outputs an input signal delayed by a delay time unique to the third delay cell (dc3) or without delay according to the corresponding control signal. Accordingly, the first phase delay chain circuit (122_1) to the M-th phase phase delay chain circuit (122_M) each delays the input signal by the phase difference value and outputs it.

The input signal of the first phase delay chain circuit (122_1) becomes a reference clock signal, and the input signal of each of the second phase delay chain circuits (122_2) to the M-th phase delay chain circuit (122_M) becomes the output of the phase delay chain circuit of the preceding stage.

The pulse width modulation unit (200) generates a pulse signal that is activated for a period corresponding to the value of the M bit signal during one period of the first signal. The first signal is generated by dividing one of the M clock signals. For example, the first signal can be generated by dividing the first clock signal among the M clock signals. For reference, the maximum number of pulse signals that can be activated during one period of the first signal is 2 to the M power.

Specifically, the pulse width modulation unit (200) generates, by using the first signal and M clock signals, a first pulse signal that is activated during a section corresponding to a value of M bits or less of one ½ period of the first signal. In addition, the pulse width modulation unit (200) generates, by using the inverted signal of the first signal and M clock signals, a second pulse signal that is activated during a section corresponding to a value of M bits or less of another ½ period of the first signal, excluding a section in which the first pulse signal is activated.

Additionally, the pulse width modulation unit (200) generates a final pulse signal by outputting a first pulse signal during one ½ cycle of the first signal and outputting a second pulse signal during the other ½ cycle of the first signal.

Fig. 8 shows a configuration diagram of a pulse width modulation unit (200) according to one embodiment. In addition, Fig. 9 shows an example of waveforms of major nodes of a pulse width modulation unit (200) according to one embodiment.

As can be seen from FIG. 8, a pulse width modulation unit (200) according to an embodiment is configured to include a divider (210), M first counters (220_1, ..., 220_M), a first pulse generator (230), M second counters (240_1, ..., 240_M), a second pulse generator (250), and a first multiplexer (260).

The divider (210) can generate a first signal by dividing one of the M clock signals. For example, the first signal can be generated by dividing the first clock signal. The first signal can be designed to have a period of the entire M bits. When M is 8, 8 clock signals are generated, so the first clock signal can be divided by 16 to generate the first signal so that the period corresponds to 256/8=32 reference clock signals. The M clock signals can be expressed as the first clock signal to the M-th clock signal.

The M first counters (220_1, ..., 220_M) each receive one of the first signal and the M clock signals, and output the 1-1th counting value to the 1-Mth counting value, respectively. The first signal is used as a reset signal for the M first counters (220_1, ..., 220_M). For example, in a section where the first signal is high, the M first counters (220_1, ..., 220_M) output the 1-1th counting value to the 1-Mth counting value, respectively, but in a section where the first signal is low, the M first counters (220_1, ..., 220_M) are reset.

The first pulse generator (230) adds up the 1-1 counting value to the 1-M counting value and generates a pulse signal that is activated during a section in which the summed value during the first section is equal to or less than the value of the M-bit signal. Here, the first section is a section corresponding to ½ cycle of the first signal.

That is, if M is 8, and the period of the first signal is 2 to the power of 8, that is, a section that can generate 256 pulse signals. In addition, if the signal of M bits is 11001100 in binary, this corresponds to 204 in decimal, so the first pulse generator (230) generates 128 activated pulse signals during the first section. In addition, if the signal of M bits is 00110011 in binary, this corresponds to 51 in decimal, so the first pulse generator (230) generates 51 activated pulse signals during the first section.

The M second counters (240_1, …, 240_M) each receive an inverted signal of the first signal and one of the M clock signals, and output a 2-1-th counting value to a 2-M-th counting value, respectively. The inverted signal of the first signal is used as a reset signal for the M second counters (240_1, …, 240_M). For example, in a section where the inverted signal of the first signal is high, the M second counters (240_1, …, 240_M) output the 2-1-th counting value to a 2-M-th counting value, respectively, but in a section where the inverted signal of the first signal is low, the M second counters (240_1, …, 240_M) are reset.

The second pulse generator (250) first adds the 2-1 counting value to the 2-M counting value, and secondarily adds the number of pulse signals that can be activated at most during the first section to the result of the first addition. If M is 8, the number of pulse signals that can be activated at most during the first section is 128, which is ½ of the total 256 pulse signals. In addition, the second pulse generator (250) generates a pulse signal that is activated during a section in which the second addition value during the second section corresponds to a value of the M bit signal or less. Here, the second section is a section corresponding to ½ of the cycle of the first signal other than the first section.

That is, if M is 8, the period of the first signal becomes a section that can generate 2^8, that is, 256 pulse signals. In addition, if the signal of M bits is 11001100 in binary, which corresponds to 204 in decimal, the maximum number of pulse signals that can be activated during the first section is 128, and since the second sum value is calculated by adding 128 to the result of the first sum, the number of pulse signals actually activated during the second section is (204-128) = 76. In addition, if the signal of M bits is 00110011 in binary, which corresponds to 51 in decimal, the maximum number of pulse signals that can be activated during the first section is 128, and since the second sum value is calculated by adding 128 to the result of the first sum, the number of pulse signals actually activated during the second section is 0.

The first multiplexer (260) selects and outputs one of the outputs of the first pulse generator (230) and the output of the second pulse generator (250) by using the first signal as a selection signal, thereby outputting a pulse signal having a pulse width of a section corresponding to a value of the M bit signal or less. For example, the first multiplexer (260) may select and output the output of the first pulse generator (230) during a section in which the first signal is high, and select and output the output of the second pulse generator (250) during a section in which the first signal is low.

Finally, the pulse signal output from the first multiplexer (260) is activated for a period corresponding to the value of the M bit signal. That is, if M is 8 and the M bit signal is 11001100 in binary, this corresponds to 204 in decimal, and the first pulse generator (230) generates 128 activated pulse signals, and the second pulse generator (250) generates 76 activated pulse signals, so that the number of pulse signals output from the first multiplexer (260) is 204.

The operating characteristics of the pulse width modulation unit (200) will be summarized again.

When M is 8, the pulse width modulation unit (200) requires 256 clocks for the lower 8 bits. In order to design the pulse width modulation unit (200) to output a 500 kHz signal, only 32 clocks can be used to correspond to the lower 8 bits when 8 multi-phase clocks are used. In other words, the design of the output of the pulse width modulation unit (200) of (16 MHz × 8) / 32 = 0.5 MHz is possible. In addition, by generating a reset signal divided by 16 from a 16㎒ first clock signal as the first signal, and using eight first counters (220_1, ..., 220_M) during ½ period of the first signal and eight second counters (240_1, ..., 240_M) during the remaining ½ period of the first signal, it is possible to design the first counter (220_1, ..., 220_M) and the second counter (240_1, ..., 240_M) with small bits.

If it is assumed that 16 clock signals having different phases are generated in the multi-phase clock generation unit (100), the frequency of the pulse width modulation unit (200) can be changed to 1 MHz.

Figure 10 shows a configuration diagram of a signal generation unit (300) according to one embodiment.

As can be seen from FIG. 10, the signal generation unit (300) according to one embodiment may be configured to include an adder (310) and a second multiplexer (320). The adder (310) adds 1 to the signal of the upper N bits and outputs it. That is, the second multiplexer (320) selects and outputs either the signal of the upper N bits among L bits or a signal that is 1 greater than the signal of the upper N bits, using the pulse signal output from the pulse width modulation unit (200) as a selection signal. For example, when the activation of the pulse is set to an active high state, if the corresponding pulse signal is in a high state, the second multiplexer (320) outputs a signal that is 1 greater than the signal of the upper N bits, and if the corresponding pulse signal is in a low state, the second multiplexer (320) outputs a signal of the upper N bits.

As described above, according to the digital-to-analog converter (1000) of one embodiment, it can be seen that high bit and high data conversion frequency can be implemented.

1000 : Digital-to-Analog Converter
100: Multi-phase clock generation unit 200: Pulse width modulation unit
300: Signal generation unit 400: Conversion unit
500: Integral filter section 600: Amplifier section
110 : Reference time measuring device 120 : Multi-phase clock generator
210 : Divider
220_1, …, 220_M: 1st counter
230: 1st pulse generator
240_1, …, 240_M: Second counter
250: 2nd pulse generator 260: 1st multiplexer
310: Adder 320: Second multiplexer
111: 1st delay cell chain circuit 112: 2nd delay cell chain circuit
113 : Flip-flop 114 : Up-down counter
121: Phase difference value generator
122_1, …, 122_M: Phase delay chain circuit
dc, dc1, dc2, dc3 : Delay cells

Claims (11)

delete delete delete delete delete In a digital-to-analog converter that converts a digital signal of L bits into an analog signal,
A multi-phase clock generation unit which receives a reference clock signal and generates M clock signals having different phases; a pulse width modulation unit which receives a signal of lower M bits of the L bits and the M clock signals and generates a pulse signal having a pulse width corresponding to a value of the signal of the M bits; a signal generation unit which receives the pulse signal and a signal of upper N bits of the L bits and generates and outputs a digital signal of N bits corresponding to a digital signal of the L bits; and a conversion unit which converts the output of the signal generation unit into an analog signal;
The above M and the above N are each natural numbers greater than or equal to 3,
The above L has a value that is the sum of the above M and the above N,
The pulse width modulation unit generates the pulse signal that is activated for a period corresponding to the value of the M bit signal among the periods of one cycle of the first signal,
The above first signal is generated by dividing one of the M clock signals,
The pulse width modulation unit comprises: M first counters which respectively receive the first signal and one of the M clock signals and output a 1-1 counting value to a 1-M counting value; a first pulse generator which adds the 1-1 counting value to the 1-M counting value and generates the pulse signal which is activated during a section in which the summed value during a first section is less than or equal to the value of the M bit signal; M second counters which respectively receive an inverted signal of the first signal and one of the M clock signals and output a 2-1 counting value to a 2-M counting value; a second pulse generator which first adds the 2-1 counting value to the 2-M counting value, secondly adds the number of pulse signals which can be activated at most during the first section to the result of the first addition, and secondly generates the pulse signal which is activated during a section in which the second addition during a second section is less than or equal to the value of the M bit signal; And it is configured to include a first multiplexer that outputs a pulse signal having a pulse width of a section corresponding to a value of the M bit signal or less by selecting and outputting one of the outputs of the first pulse generator and the output of the second pulse generator using the first signal as a selection signal;
The above first section is a section corresponding to ½ cycle of the above first signal,
A digital-to-analog converter, wherein the second section is a section corresponding to ½ a period of the first signal other than the first section. delete In a digital-to-analog converter that converts a digital signal of L bits into an analog signal,
A multi-phase clock generation unit which receives a reference clock signal and generates M clock signals having different phases; a pulse width modulation unit which receives a signal of lower M bits of the L bits and the M clock signals and generates a pulse signal having a pulse width corresponding to a value of the signal of the M bits; a signal generation unit which receives the pulse signal and a signal of upper N bits of the L bits and generates and outputs a digital signal of N bits corresponding to a digital signal of the L bits; and a conversion unit which converts the output of the signal generation unit into an analog signal;
The above M and the above N are each natural numbers greater than or equal to 3,
The above L has a value that is the sum of the above M and the above N,
The above multi-phase clock generation unit is configured to include a reference time measuring unit that receives the reference clock signal and measures a reference time value corresponding to a 1/T period of the reference clock signal; and a multi-phase clock generator that calculates a phase difference value between the M clock signals from the reference time value and generates the M clock signals having different phases using the phase difference value;
The above T is a natural number greater than or equal to 1,
The above-mentioned reference time measuring device comprises: a first delay cell chain circuit including a plurality of first delay cells connected in series, and capable of delaying or outputting the reference clock signal without delay using the plurality of first delay cells; a second delay cell chain circuit including a plurality of second delay cells connected in series, and capable of delaying or outputting the reference clock signal without delay using the plurality of second delay cells; a flip-flop which receives one of the outputs of the first delay cell chain circuit and the second delay cell chain circuit as data, and receives the other of the outputs of the first delay cell chain circuit and the second delay cell chain circuit as a clock signal; and an up-down counter which uses the reference clock signal as a clock, receives an output of the flip-flop, counts it, and outputs the reference time value;
A digital-to-analog converter in which each of a plurality of first delay cells of the first delay cell chain circuit uses one bit of the total bits of the reference time value as a control signal, delays the input reference clock signal or the output of the first delay cell of the previous stage by a delay time unique to the first delay cell according to the control signal, or outputs the output of the first delay cell of the previous stage without delay. In a digital-to-analog converter that converts a digital signal of L bits into an analog signal,
A multi-phase clock generation unit which receives a reference clock signal and generates M clock signals having different phases; a pulse width modulation unit which receives a signal of lower M bits of the L bits and the M clock signals and generates a pulse signal having a pulse width corresponding to a value of the signal of the M bits; a signal generation unit which receives the pulse signal and a signal of upper N bits of the L bits and generates and outputs a digital signal of N bits corresponding to a digital signal of the L bits; and a conversion unit which converts the output of the signal generation unit into an analog signal;
The above M and the above N are each natural numbers greater than or equal to 3,
The above L has a value that is the sum of the above M and the above N,
The above multi-phase clock generation unit is configured to include a reference time measuring unit that receives the reference clock signal and measures a reference time value corresponding to a 1/T period of the reference clock signal; and a multi-phase clock generator that calculates a phase difference value between the M clock signals from the reference time value and generates the M clock signals having different phases using the phase difference value;
The above T is a natural number greater than or equal to 1,
The above multi-phase clock generator comprises: a first phase delay chain circuit to an M-th phase phase delay chain circuit, each of which includes a plurality of third delay cells connected in series;
The above first phase delay chain circuit to the above M-th phase phase delay chain circuit are connected in series sequentially,
The above first phase delay chain circuit delays the reference clock signal by the phase difference value and outputs it.
A digital-to-analog converter, wherein each of the second phase delay chain circuit to the M-th phase phase delay chain circuit delays the output of the phase delay chain circuit of the previous stage by the phase difference value and outputs it. In Article 9,
Each of the above multiple third delay cells,
A digital-to-analog converter that outputs an input signal by delaying the delay time of a third delay cell or without delay according to the control signal by using one bit of the total bits of the above phase difference value as each control signal. In Article 9,
The above signal generating unit,
Consisting of a second multiplexer,
The above second multiplexer,
A digital-to-analog converter that selects one of the upper N bits of the L bits or a signal that is 1 greater than the upper N bits of the L bits, using the pulse signal as a selection signal, and outputs a digital signal of the N bits.

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