KR102816400B1 - Liquid Crystal Display Device And Method Of Driving The Same - Google Patents

Abstract

The present invention provides a liquid crystal display device including a plurality of gate wires; a plurality of data wires intersecting the plurality of gate wires; first and second auxiliary data wires intersecting the plurality of gate wires and arranged on the left and right sides of the plurality of data wires, respectively; and a plurality of sub-pixels connected to the plurality of gate wires, the plurality of data wires, and the first and second auxiliary data wires and arranged in a matrix form, wherein two of the plurality of sub-pixels are arranged in each column between two adjacent ones of the plurality of data wires, and one of the plurality of sub-pixels is arranged in each column between the first auxiliary data wire and the plurality of data wires and between the plurality of data wires and the second auxiliary data wire.

Description

Liquid Crystal Display Device And Method Of Driving The Same

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof in which defects in a black and white pattern are minimized by supplying a data voltage to a subpixel at the outermost portion through an auxiliary data line.

Recently, as society has entered the full-fledged information age, interest in information displays that process and display large amounts of information has increased, and as the demand for portable information media has increased, various lightweight and thin flat panel display devices have been developed to meet this demand and are receiving attention.

Among these flat panel display devices, liquid crystal display devices display images by adjusting the transmittance of the liquid crystal layer according to the data voltage. However, if a direct current voltage is applied to the liquid crystal layer for a long period of time, charges accumulate, causing afterimages.

To prevent this, an inversion driving method that inverts the data voltage based on the common voltage was proposed. The inversion driving method is classified into frame inversion, line inversion, column inversion, and dot inversion.

Meanwhile, in order to cope with the increase in driving speed and resolution, a double rate driving (DRD) method was proposed, which supplies data voltage to two subpixels with a single data line.

This type of double-rate liquid crystal display can display images in a horizontal 2-dot inversion manner.

However, when a specific pattern, such as a black-and-white pattern in which high-grayscale white and low-grayscale black are displayed alternately, is displayed in a horizontal 2-dot inversion manner, the positive (+) or negative (-) polarity becomes dominant in the two subpixels displaying white, and depending on the dominant polarity, a fluctuation (ripple) occurs in the common voltage, causing the data voltage supplied to adjacent subpixels to fluctuate, resulting in defects such as vertical dim or smear and a deterioration in the display quality of the image.

The present invention has been proposed to solve such problems, and aims to provide a liquid crystal display device and a driving method thereof in which defects such as vertical dim or smear in a black and white pattern are minimized by supplying data voltage to a central subpixel through a data wire and supplying data voltage to an outermost subpixel through an auxiliary data wire.

Another object of the present invention is to provide a liquid crystal display device and a driving method thereof, which reduce power consumption and manufacturing cost and improve image display quality by driving subpixels in the central and outermost portions by frame inversion, horizontal 2-dot inversion, and vertical 1-dot inversion.

In order to solve the above problem, the present invention provides a liquid crystal display device including a plurality of gate wires; a plurality of data wires intersecting the plurality of gate wires, first and second auxiliary data wires; and a plurality of sub-pixels connected to the plurality of gate wires, the plurality of data wires, and the first and second auxiliary data wires and arranged in a matrix form, wherein the plurality of data wires are arranged between the first and second auxiliary data wires, and two of the plurality of sub-pixels are arranged in at least one row between two adjacent data wires among the plurality of data wires, and one of the plurality of sub-pixels is arranged in at least one row between the first auxiliary data wire and the leftmost data wire among the plurality of data wires and between the rightmost data wire among the plurality of data wires and the second auxiliary data wire.

And, among the plurality of sub-pixels arranged in one column between the first auxiliary data wire and the leftmost data wire, a sub-pixel arranged in one of the even-numbered rows and the odd-numbered rows may be connected to the first auxiliary data wire, and a sub-pixel arranged in the remaining one of the even-numbered and odd-numbered rows may be connected to the leftmost data wire.

In addition, the plurality of subpixels arranged in two columns between two adjacent ones of the plurality of data wires may be alternately connected to two adjacent ones of the plurality of data wires for each row.

And, the plurality of gate wirings include first to fourth gate wirings, the plurality of data wirings include first to nth data wirings, the plurality of sub-pixels include eleventh to seventeenth sub-pixels and twenty-first to twenty-seventh sub-pixels, the eleventh sub-pixel can be connected to the first gate wiring and the first auxiliary data wiring, and the twenty-first sub-pixel can be connected to the third gate wiring and the first data wiring.

In addition, the 12th sub-pixel is connected to the first gate wiring and the first data wiring, the 13th sub-pixel is connected to the second gate wiring and the first data wiring, the 14th sub-pixel is connected to the second gate wiring and the second data wiring, the 15th sub-pixel is connected to the first gate wiring and the second data wiring, the 16th sub-pixel is connected to the second gate wiring and the third data wiring, the 17th sub-pixel is connected to the first gate wiring and the third data wiring, the 22nd sub-pixel is connected to the third gate wiring and the second data wiring, the 23rd sub-pixel is connected to the fourth gate wiring and the second data wiring, the 24th sub-pixel is connected to the fourth gate wiring and the third data wiring, and the 25th sub-pixel is connected to the third gate wiring and the The 26th sub-pixel may be connected to the 4th gate wiring and the 4th data wiring, and the 27th sub-pixel may be connected to the 3rd gate wiring and the 4th data wiring.

And, during the first frame, a positive data voltage can be supplied through the first and third data wires, and a negative data voltage can be supplied through the first auxiliary data wire and the second and fourth data wires, and during the second frame, a negative data voltage can be supplied through the first and third data wires, and a positive data voltage can be supplied through the first auxiliary data wire and the second and fourth data wires.

In addition, the plurality of gate wirings include first to fourth gate wirings, the plurality of data wirings include first to n-th data wirings, the plurality of sub-pixels include first (2n-6) to first (2n)-th sub-pixels and second (2n-6) to second (2n)-th sub-pixels, the first (2n) sub-pixels can be connected to the first gate wiring and the n-th data wiring, and the second (2n) sub-pixels can be connected to the third gate wiring and the second auxiliary data wiring.

And, the first (2n-6) sub-pixel is connected to the first gate wiring and the (n-3) data wiring, the first (2n-5) sub-pixel is connected to the second gate wiring and the (n-3) data wiring, the first (2n-4) sub-pixel is connected to the second gate wiring and the (n-2) data wiring, the first (2n-3) sub-pixel is connected to the first gate wiring and the (n-2) data wiring, the first (2n-2) sub-pixel is connected to the second gate wiring and the (n-1) data wiring, the first (2n-1) sub-pixel is connected to the first gate wiring and the (n-1) data wiring, the second (2n-6) sub-pixel is connected to the third gate wiring and the (n-2) data wiring, and the The second (2n-5) sub-pixel may be connected to the fourth gate wiring and the (n-2) data wiring, the second (2n-4) sub-pixel may be connected to the fourth gate wiring and the (n-1) data wiring, the second (2n-3) sub-pixel may be connected to the third gate wiring and the (n-1) data wiring, the second (2n-2) sub-pixel may be connected to the fourth gate wiring and the n-th data wiring, and the second (2n-1) sub-pixel may be connected to the third gate wiring and the n-th data wiring.

In addition, during the first frame, a positive data voltage can be supplied through the (n-2)-th and n-th data wires, and a negative data voltage can be supplied through the (n-3)-th and (n-1)-th data wires and the second auxiliary data wire, and during the second frame, a negative data voltage can be supplied through the (n-2)-th and n-th data wires, and a positive data voltage can be supplied through the (n-3)-th and (n-1)-th data wires and the second auxiliary data wire.

And, the above plurality of sub-pixels display one of the following: a first pattern in which a white vertical line of two pixels and a black vertical line of two pixels are repeated, a second pattern in which a white dot of one pixel and a black dot of one pixel are repeated, a third pattern in which a white dot of two pixels and a black dot of two pixels are repeated, a fourth pattern in which a white dot of three pixels and a black dot of three pixels are repeated, and a fifth pattern in which a white dot of four pixels and a black dot of four pixels are repeated, and the sum of the polarities of the sub-pixels constituting the white vertical lines of the first pattern and the white dots of the second to fifth patterns may be 0.

Meanwhile, the present invention provides a method for driving a liquid crystal display device including first to fourth gate wires, first to n-th data wires, first and second auxiliary data wires, 11th to 17th sub-pixels, and 21st to 27th sub-pixels, the step of supplying a gate voltage to the first gate wire, supplying a data voltage to the 11th sub-pixel through the first auxiliary data wire, supplying the data voltage to the 12th sub-pixel through the first data wire, supplying the data voltage to the 15th sub-pixel through the second data wire, and supplying the data voltage to the 17th sub-pixel through the third data wire; A step of supplying the gate voltage to the second gate wiring, supplying the data voltage to the 13th sub-pixel through the first data wiring, supplying the data voltage to the 14th sub-pixel through the second data wiring, and supplying the data voltage to the 16th sub-pixel through the third data wiring; A step of supplying the gate voltage to the third gate wiring, supplying the data voltage to the 21st sub-pixel through the first data wiring, supplying the data voltage to the 22nd sub-pixel through the second data wiring, supplying the data voltage to the 25th sub-pixel through the third data wiring, and supplying the data voltage to the 27th sub-pixel through the 4 data wiring; A method for driving a liquid crystal display device is provided, including the steps of supplying the gate voltage to the fourth gate wiring, supplying the data voltage to the 23rd sub-pixel through the second data wiring, supplying the data voltage to the 24th sub-pixel through the third data wiring, and supplying the data voltage to the 26th sub-pixel through the fourth data wiring.

And, the liquid crystal display further includes first (n-3) to first (2n) sub-pixels and second (n-3) to second (2n) sub-pixels, and a driving method of the liquid crystal display includes the steps of: supplying a gate voltage to the first gate wire, supplying a data voltage to the first (2n-6) sub-pixel through the (n-3)-th data wire, supplying the data voltage to the first (2n-3) sub-pixel through the (n-2)-th data wire, supplying the data voltage to the first (2n-1) sub-pixel through the (n-1)-th data wire, and supplying the data voltage to the first (2n) sub-pixel through the n-th data wire; A step of supplying the gate voltage to the second gate wiring, supplying the data voltage to the first (2n-5) sub-pixel through the (n-3)th data wiring, supplying the data voltage to the first (2n-4) sub-pixel through the (n-2)th data wiring, and supplying the data voltage to the first (2n-2) sub-pixel through the (n-1)th data wiring; A step of supplying the gate voltage to the third gate wiring, supplying the data voltage to the second (2n-6) sub-pixel through the (n-2)th data wiring, supplying the data voltage to the second (2n-3) sub-pixel through the (n-1)th data wiring, supplying the data voltage to the second (2n-1) sub-pixel through the nth data wiring, and supplying the data voltage to the second (2n) sub-pixel through the second auxiliary data wiring; The method may further include a step of supplying the gate voltage to the fourth gate wiring, supplying the data voltage to the second (2n-5) subpixel through the (n-2)th data wiring, supplying the data voltage to the second (2n-4) subpixel through the (n-1)th data wiring, and supplying the data voltage to the second (2n-2) subpixel through the nth data wiring.

The present invention has the effect of minimizing defects such as vertical dim or smear in a black and white pattern by supplying data voltage to a central subpixel through a data wire and supplying data voltage to an outermost subpixel through an auxiliary data wire.

In addition, the present invention has the effects of reducing power consumption, saving manufacturing costs, and improving image display quality by driving the sub-pixels in the central and outermost portions in a frame inversion, horizontal 2-dot inversion, and vertical 1-dot inversion manner.

FIG. 1 is a drawing illustrating a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a subpixel of a liquid crystal display device according to an embodiment of the present invention.
FIGS. 3A and 3B are diagrams illustrating polarity states of first and second frames of a display panel of a liquid crystal display device according to an embodiment of the present invention, respectively.
FIG. 4 is a drawing illustrating a display state of a first pattern of a liquid crystal display device according to an embodiment of the present invention.
FIG. 5 is a drawing illustrating a display state of a second pattern of a liquid crystal display device according to an embodiment of the present invention.
FIG. 6 is a drawing illustrating a display state of a third pattern of a liquid crystal display device according to an embodiment of the present invention.
FIG. 7 is a drawing illustrating a display state of a fourth pattern of a liquid crystal display device according to an embodiment of the present invention.
FIG. 8 is a drawing illustrating a display state of a fifth pattern of a liquid crystal display device according to an embodiment of the present invention.

Hereinafter, a liquid crystal display device and its driving method according to the present invention will be described with reference to the attached drawings.

FIG. 1 is a drawing illustrating a liquid crystal display device according to an embodiment of the present invention.

As illustrated in FIG. 1, a liquid crystal display device (LCD device) (110) according to an embodiment of the present invention includes a timing control unit (120), a data driving unit (130), a gate driving unit (140), and a display panel (150).

The timing control unit (120) can generate image data, data control signals, and gate control signals using a plurality of timing signals, such as an image signal, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock, transmitted from an external system (not shown) such as a graphics card or a TV system. In addition, the timing control unit (120) transmits the generated image data and data control signals to the data driving unit (130), and transmits the generated gate control signals to the gate driving unit (140).

The data driving unit (130) generates a data voltage (data signal) using the data control signal and image data transmitted from the timing control unit (120), and applies the generated data voltage to the data wiring (DL) of the display panel (150).

The gate driving unit (140) generates a gate voltage (gate signal) using a gate control signal transmitted from the timing control unit (120) and applies the generated gate voltage to the gate wiring (GL) of the display panel (150).

Here, the gate driving unit (140) may be a gate-in-panel (GIP) type formed on the substrate of the display panel (150) together with a gate wire (GL), a data wire (DL), and a pixel (P) and placed in a non-display area (NDA).

The display panel (150) displays an image using a gate voltage and a data voltage, and includes a central display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) includes a plurality of pixels (P), and each of the plurality of pixels (P) includes red, green, and blue subpixels (SPr, SPg, SPb).

To this end, the display panel (150) includes first and second substrates facing each other and spaced apart from each other, and a liquid crystal layer disposed between the first and second substrates.

Specifically, gate lines (GL) and data lines (DL) that intersect with each other and define red, green, and blue subpixels (SPr, SPg, SPb) are arranged on the upper part of the first substrate, and a pixel transistor (Td) is arranged for each of the red, green, and blue subpixels (SPr, SPg, SPb).

The gate electrode of the pixel transistor (Td) is connected to the gate wiring (GL), the source electrode of the pixel transistor (Td) is connected to the data wiring (DL), and the drain electrode of the pixel transistor (Td) is connected to the pixel electrode and the storage capacitor (Cst).

A liquid crystal layer is arranged on top of the pixel electrode, a common electrode is arranged on top of the liquid crystal layer, and the pixel electrode, liquid crystal layer, and common electrode form a liquid crystal capacitor (Clc).

The connection configuration of the subpixels of the display panel (150) of the liquid crystal display device (110) is explained with reference to the drawings.

FIG. 2 is a circuit diagram showing a subpixel of a liquid crystal display device according to an embodiment of the present invention, which will be described with reference to FIG. 1.

As illustrated in FIG. 2, the display panel (150) of the liquid crystal display (110) according to the embodiment of the present invention includes first to eighth gate lines (GL1 to GL8), first to nth data lines (DL1 to DLn), first and second auxiliary data lines (DLa1, DLa2), eleventh to first (2n) sub-pixels (SP11 to SP1 (2n)), twenty-first to second (2n) sub-pixels (SP21 to SP2 (2n)), thirty-first to third (2n) sub-pixels (SP31 to SP3 (2n)), and forty-first to fourth (2n) sub-pixels (SP41 to SP4 (2n)).

Specifically, the first to eighth gate wires (GL1 to GL8) are arranged spaced apart from each other and parallel to each other, and the first to nth data wires (DL1 to DLn) and the first and second auxiliary data wires (DLa1, DLa2) intersect the first to eighth gate wires (GL1 to GL8) and are arranged spaced apart from each other and parallel to each other.

Between the first and second gate wirings (GL1, GL2), the first (2n) sub-pixels (SP11 to SP1(2n)) are arranged, between the third and fourth gate wirings (GL3, GL4), the twenty-first to second (2n) sub-pixels (SP21 to SP2(2n)) are arranged, between the fifth and sixth gate wirings (GL5, GL6), the thirty-first to third (2n) sub-pixels (SP31 to SP3(2n)) are arranged, and between the seventh and eighth gate wirings (GL7, GL8), the forty-first to fourth (2n) sub-pixels (SP41 to SP4(2n)) are arranged.

That is, two gate lines (GL) can be placed between two subpixels (SP) that are vertically adjacent.

The first to nth data wires (DL1 to DLn) are arranged in the central portion (CA) of the display area (DA), and the first and second auxiliary data wires (DLa1, DLa2) are arranged in the outermost portion (PA) of the display area (DA), respectively. The first auxiliary data wire (DLa1) may be arranged to the left of the first data wire (DL1), and the second auxiliary data wire (DLa2) may be arranged to the right of the nth data wire (DLn).

Between the first auxiliary data wire (DLa1) and the first data wire (DL1), the 11th, 21st, 31st, and 41st sub-pixels (SP11, SP21, SP31, SP41) are arranged, between the first and second data wires (DL1, DL2), the 12th, 13th, 22nd, 23rd, 32nd, 33rd, 42nd, and 43rd sub-pixels (SP12, SP13, SP22, SP23, SP32, SP33, SP42, SP43) are arranged, and between the second and third data wires (DL2, DL3), the 14th, 15th, 24th, 25th, 34th, 35th, 44th, and 45th sub-pixels (SP14, SP15, SP24, SP25, SP34, SP35, SP44, SP45) are arranged.

Similarly, between the (n-2)th and (n-1)th data lines (DL(n-2), DL(n-1), the first (2n-4), the first (2n-3), the second (2n-4), the second (2n-3), the third (2n-4), the third (2n-3), the fourth (2n-4), the fourth (2n-3) subpixels (SP1(2n-4), SP1(2n-3), SP2(2n-4), SP2(2n-3), SP3(2n-4), SP3(2n-3), SP4(2n-4), SP4(2n-3)) are arranged, and between the (n-1)th and nth data lines (DL(n-1), DLn), the first (2n-2), the first (2n-1), the second (2n-2), the second (2n-1), the third (2n-2), The third (2n-1), fourth (2n-2), and fourth (2n-1) sub-pixels (SP1 (2n-2), SP1 (2n-1), SP2 (2n-2), SP2 (2n-1), SP3 (2n-2), SP3 (2n-1), SP4 (2n-2), SP4 (2n-1)) are arranged, and the first (2n), second (2n), third (2n), and fourth (2n) sub-pixels (SP1 (2n), SP2 (2n), SP3 (2n), SP4 (2n)) are arranged between the nth data line (DLn) and the second auxiliary data line (DLa2).

That is, two subpixels can be arranged in each column between two data wires that are adjacent in the horizontal direction (horizontal direction), and one subpixel can be arranged in each column between the first auxiliary data wire (DLa1) and the data wire and between the second auxiliary data wire (DLa2) and the data wire.

Here, the eleventh to fourth (2n) subpixels (SP11 to SP4(2n)) have a color arrangement in a stripe shape, for example, the subpixels of the first, fourth, seventh, ..., (2n-4), (2n-1)-th columns, which are vertical pixel lines, may correspond to red, the subpixels of the second, fifth, ..., (2n-6), (2n-3), (2n)-th columns may correspond to green, and the subpixels of the third, sixth, ..., (2n-5), (2n-2)-th columns may correspond to blue.

The 11th sub-pixel (SP11) is connected to the first gate wiring (GL1) and the first auxiliary data wiring (DLa1), and the 21st sub-pixel (SP21) is connected to the third gate wiring (GL3) and the first data wiring (DL1).

The 31st and 41st sub-pixels (SP31, SP41) are connected to the gate wiring (GL) and data wiring (DL) similarly to the 11th and 21st sub-pixels (SP11, SP21), and the connection structure of the 11th and 21st sub-pixels (SP11, SP21) is repeated in the sub-pixels of the first row.

The 12th sub-pixel (SP12) is connected to the first gate wiring (GL1) and the first data wiring (DL1), the 13th sub-pixel (SP13) is connected to the second gate wiring (GL2) and the first data wiring (DL1), the 14th sub-pixel (SP14) is connected to the second gate wiring (GL2) and the second data wiring (DL2), the 15th sub-pixel (SP15) is connected to the first gate wiring (GL1) and the second data wiring (DL2), the 16th sub-pixel (SP16) is connected to the second gate wiring (GL2) and the third data wiring (DL3), and the 17th sub-pixel (SP17) is connected to the first gate wiring (GL1) and the third data wiring (DL3).

And, the 22nd sub-pixel (SP22) is connected to the third gate wiring (GL3) and the second data wiring (DL2), the 23rd sub-pixel (SP23) is connected to the fourth gate wiring (GL4) and the second data wiring (DL2), the 24th sub-pixel (SP24) is connected to the fourth gate wiring (GL4) and the third data wiring (DL3), the 25th sub-pixel (SP25) is connected to the third gate wiring (GL4) and the third data wiring (DL3), the 26th sub-pixel (SP26) is connected to the fourth gate wiring (GL4) and the fourth data wiring (DL4), and the 27th sub-pixel (SP27) is connected to the third gate wiring (GL3) and the fourth data wiring (DL4).

The first (2n-6) to the first (2n-1) subpixels (SP1 (2n-6) to SP1 (2n-1)) and the second (2n-6) to the second (2n-1) subpixels (SP1 (2n-6) to SP1 (2n-1)), SP2 (2n-6) to SP2 (2n-1)), the 32nd to 37th subpixels (SP32 to SP37) and the 42nd to 47th subpixels (SP42 to SP47), the third (2n-6) to the third (2n-1) subpixels (SP3 (2n-6) to SP3 (2n-1)) and the fourth (2n-6) to fourth (2n-1) subpixels (SP4 (2n-6) to SP4 (2n-1)) are the 12th to 17th subpixels (SP12 to SP17) and the 22nd to Similarly to the 27th sub-pixel (SP22 to SP27), it is connected to the gate wiring (GL) and the data wiring (DL), and in the sub-pixels of the 2nd to (2n-1)th columns, the connection structure of the 12th to 17th sub-pixels (SP12 to SP17) and the 22nd to 27th sub-pixels (SP22 to SP27) is repeated.

The first (2n) sub-pixel (SP1(2n)) is connected to the first gate wiring (GL1) and the nth data wiring (DLn), and the second (2n) sub-pixel (SP2(2n)) is connected to the third gate wiring (GL3) and the second auxiliary data wiring (DLa2).

The third (2n) and fourth (2n) subpixels (SP3 (2n), SP4 (2n)) are connected to gate wiring (GL) and data wiring (DL) similarly to the first (2n) and second (2n) subpixels (SP1 (2n), SP2 (2n)), and in the subpixels of the (2n) column, the connection structure of the third (2n), fourth (2n) subpixels (SP3 (2n), SP4 (2n)) is repeated.

That is, in the first column of the left outermost portion (PA), the unit connection structure of the 11th and 21st subpixels (SP11, SP21) is repeated, in the second to (2n-1) columns of the central portion (CA), the unit connection structures of the 12th to 17th subpixels (SP12 to SP17) and the 22nd to 27th subpixels (SP22 to SP27) are repeated, and in the (2n) column of the right outermost portion (PA), the unit connection structures of the 1st (2n) and 2nd (2n) subpixels (SP1 (2n), SP2 (2n)) are repeated.

In the central portion (CA) of the display panel (150), the data voltage supplied through the first data wire (DL1) is sequentially supplied to the 12th, 13th, and 21st sub-pixels (SP12, SP13, SP21), the data voltage supplied through the second data wire (DL2) is sequentially supplied to the 15th, 14th, 22nd, and 23rd sub-pixels (SP15, SP14, SP22, SP23), and the data voltage supplied through the third data wire (DL3) is sequentially supplied to the 17th, 16th, 15th, and 24th sub-pixels (SP17, SP16, SP15, SP24).

The supply order of these data voltages is the same in the unit connection structure of the central area (CA).

Here, each data line (DL) can reduce power consumption by supplying data voltage of the same polarity in one frame.

The polarity status of each frame of these display panels is explained with reference to the drawings.

FIGS. 3A and 3B are drawings showing polarity states of the first and second frames of the display panel of the liquid crystal display device according to an embodiment of the present invention, respectively, and will be described with reference to FIGS. 1 and 2.

As shown in FIGS. 3a and 3b, in the display panel (150) of the liquid crystal display device (110) according to the embodiment of the present invention, the central portion (CA) operates in a frame inversion, horizontal 2-dot inversion, and vertical 1-dot inversion manner, and the outermost portion (PA) operates in a frame inversion, horizontal 1-dot inversion, and vertical 1-dot inversion manner.

As illustrated in FIG. 3a, during the first frame, a positive (+) data voltage is supplied through the first, third, ..., (n-2), nth data wires (DL1, DL3, ..., DL(n-2), DLn), and a negative (-) data voltage is supplied through the first auxiliary data wire (DLa1), the second, fourth, ..., (n-3), (n-1), and second auxiliary data wires (DLa2).

Accordingly, the 11th, 21st, 31st, and 41st subpixels (SP11, SP21, SP31, and SP41) of the left outermost portion (PA) have negative polarity (-), positive polarity (+), negative polarity (-), and positive polarity (+), respectively, and the 1st (2n), 2nd (2n), 3rd (2n), and 4th (2n) subpixels (SP1 (2n), SP2 (2n), SP3 (2n), and SP4 (2n)) of the right outermost portion (PA) have positive polarity (+), negative polarity (-), positive polarity (+), and negative polarity (-), respectively.

The 12th to 17th subpixels (SP12 to SP17), which are the unit connection structures of the central area (CA), have positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), and positive polarity (+), respectively, and the 22nd to 27th subpixels (SP22 to SP27), which are the unit connection structures, have negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and negative polarity (-), respectively.

The remaining subpixels in the central area (CA) have the same polarity as the unit connection structures of the 12th to 17th subpixels and the 22nd to 27th subpixels.

As illustrated in FIG. 3b, during the second frame after the first frame, a negative (-) data voltage is supplied through the first, third, ..., (n-2), nth data wires (DL1, DL3, ..., DL(n-2), DLn), and a positive (+) data voltage is supplied through the first auxiliary data wire (DLa1), the second, fourth, ..., (n-3), (n-1), and second auxiliary data wires (DLa2).

Accordingly, the 11th, 21st, 31st, and 41st subpixels (SP11, SP21, SP31, SP41) of the left outermost portion (PA) have positive polarity (+), negative polarity (-), positive polarity (+), and negative polarity (-), respectively, and the 1st (2n), 2nd (2n), 3rd (2n), and 4th (2n) subpixels (SP1 (2n), SP2 (2n), SP3 (2n), SP4 (2n)) of the right outermost portion (PA) have negative polarity (-), positive polarity (+), negative polarity (-), and positive polarity (+), respectively.

The 12th to 17th subpixels (SP12 to SP17), which are the unit connection structures of the central area (CA), have negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and negative polarity (-), respectively, and the 22nd to 27th subpixels (SP22 to SP27), which are the unit connection structures, have positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), and positive polarity (+), respectively.

The remaining subpixels in the central area (CA) have the same polarity as the unit connection structures of the 12th to 17th subpixels and the 22nd to 27th subpixels.

As described above, in the liquid crystal display device (110) according to the embodiment of the present invention, the subpixel (SP) of the display panel (150) of the second frame has an opposite polarity to the subpixel (SP) of the display panel (150) of the first frame, thereby preventing charge from accumulating in the liquid crystal layer.

And, by supplying a data voltage having an opposite polarity to the subpixels of the adjacent central portion (CA) through the first and second auxiliary data lines (DLa1, DLa2) to the subpixels of the left and right outermost portions (PA), the sum of the polarities of the subpixels of a plurality of pixels displaying a specific pattern is canceled out, thereby minimizing defects such as vertical dim or smear.

The polarity cancellation by these outermost subpixels is explained with reference to the drawing.

FIG. 4 is a drawing illustrating a display state of a first pattern of a liquid crystal display device according to an embodiment of the present invention, FIG. 5 is a drawing illustrating a display state of a second pattern of a liquid crystal display device according to an embodiment of the present invention, FIG. 6 is a drawing illustrating a display state of a third pattern of a liquid crystal display device according to an embodiment of the present invention, FIG. 7 is a drawing illustrating a display state of a fourth pattern of a liquid crystal display device according to an embodiment of the present invention, and FIG. 8 is a drawing illustrating a display state of a fifth pattern of a liquid crystal display device according to an embodiment of the present invention, which will be described with reference to FIGS. 1 to 3B together.

As illustrated in FIG. 4, when the liquid crystal display device (110) according to the embodiment of the present invention displays a first pattern in which a white vertical line of two pixels and a black vertical line of two pixels (2PW/2PB Line) are repeated, the 11th, 21st, 31st, and 41st sub-pixels (SP11, SP21, SP31, and SP41) of the outermost part (PA) which is the first region (A1) and the 12th to 16th, 22nd to 26th, 32nd to 36th, and 42nd to 46th sub-pixels (SP12 to SP16, SP22 to SP26, SP32 to SP36, SP42 to SP46) of the central part (CA) which is the second region (A2) constitute the first white vertical line, and the 1st (13) to 1st (18), 2nd (13) to 2nd (18), 3rd (13) to 4th (18) sub-pixels of the central part (CA) which is the second region (A2) constitute the first white vertical line. The third (18), fourth (13) to fourth (18) sub-pixels (SP1 (13) to SP1 (18), SP2 (13) to SP2 (18), SP3 (13) to SP3 (18), SP4 (13) to SP4 (18)) form a second white vertical line, and the first (7) to first (12), second (7) to second (12), third (7) to third (12), fourth (7) to fourth (12) sub-pixels (SP1 (7) to SP1 (12), SP2 (7) to SP2 (12), SP3 (7) to SP3 (12), SP4 (7) to SP4 (12)) of the central portion (CA) between the first and second areas (A1, A2) form a first black vertical line.

Here, the 11th to 16th sub-pixels (SP11 to SP16) of the first region (A1) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), respectively, the 21st to 26th sub-pixels (SP21 to SP26) have positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), respectively, the 31st to 36th sub-pixels (SP31 to SP36) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (+), respectively, and the 41st to 46th sub-pixels (SP41 to SP46) have positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), respectively. It has negative polarity (-).

Accordingly, the positive polarity (+) and negative polarity (-) of the subpixels of the first region (A1) cancel each other out, so that the sum of the polarities becomes 0.

And, the first (13) to the first (18) subpixels (SP1 (13) to SP1 (18)) of the second region (A2) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), respectively, the second (13) to the second (18) subpixels (SP2 (13) to SP2 (18)) have positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), respectively, the third (13) to the third (18) subpixels (SP3 (13) to SP3 (18)) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (+), positive polarity (+), respectively, and the fourth (13) to The fourth (18) subpixels (SP4 (13) to SP4 (18)) have positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), and negative polarity (-), respectively.

Accordingly, the positive (+) and negative (-) polarities of the subpixels of the second area (A2) cancel each other out, so that the sum of the polarities becomes 0.

Accordingly, when the liquid crystal display device (110) according to the embodiment of the present invention displays a first pattern in which a two-pixel white vertical line and a two-pixel black vertical line (2PW/2PB Line) are repeated, the polarities of the subpixels constituting each of the two-pixel white vertical lines are offset so that the sum of the polarities becomes 0, so that fluctuations in the common voltage due to the dominant polarity of the data voltage are minimized, and distortions in the data voltage due to fluctuations in the common voltage are minimized, thereby preventing defects such as vertical dim or smear and improving the display quality of the image.

As illustrated in FIG. 5, when the liquid crystal display device (110) according to the embodiment of the present invention displays a second pattern in which a white dot of 1 pixel and a black dot of 1 pixel (1PW/1PB Dot) are repeated, the 11th sub-pixel (SP11) of the outermost portion (PA) in the first region (A1), the 12th and 13th sub-pixels (SP12, SP13) of the central portion (CA), the 1st (13) to 1st (15) sub-pixels (SP1(13) to SP1(15)) of the central portion (CA), the 31st sub-pixel (SP31) of the outermost portion (PA), the 32nd and 33rd sub-pixels (SP32, SP33) of the central portion (CA), and the 3rd (13) to 3rd (15) sub-pixels (SP3(13) to SP3(15)) of the central portion (CA) are the first, third, fifth, The seventh white dot is formed by the 17th to 19th sub-pixels (SP17 to SP19) of the central portion (CA) which is the second area (A2), the 1st (19) to 1st (21) sub-pixels (SP1 (19) to SP1 (21)) of the central portion (CA), the 37th to 39th sub-pixels (SP37 to SP39) of the central portion (CA), and the 3rd (19) to 3rd (21) sub-pixels (SP3 (19) to SP3 (21)) of the central portion (CA) forming the second, fourth, sixth, and eighth white dots, respectively, and the 14th to 16th sub-pixels (SP14 to SP16), the 1st (10) to 1st (12) sub-pixels (SP1 (10) to SP1 (12)) of the central portion (CA) between the first and second areas (A1, A2), the 1st (16) to The first (18) subpixel (SP1 (16) to SP1 (18), the 34th to 36th subpixel (SP34 to SP36), the third (10) to third (12) subpixel (SP3 (10) to SP3 (12)), and the third (16) to third (18) subpixel (SP3 (16) to SP3 (18)) constitute the first to sixth black dots, respectively.

Here, the 11th, 12th, and 13th sub-pixels (SP11, SP12, SP13) of the first region (A1) have negative polarity (-), positive polarity (+), and positive polarity (+), respectively, the 1st (13), 1st (14), and 1st (15th) sub-pixels (SP1 (13), SP1 (14), SP1 (15)) have negative polarity (-), positive polarity (+), and positive polarity (+), respectively, the 31st, 32nd, and 33rd sub-pixels (SP31, SP32, SP33) have negative polarity (-), positive polarity (+), and positive polarity (+), respectively, and the 3rd (13), 3rd (14), and 3rd (15th) sub-pixels (SP3 (13), SP3 (14), SP3 (15)) have negative polarity (-), positive polarity (+), and positive polarity (+), respectively.

And, the 17th, 18th, and 19th sub-pixels (SP17, SP18, SP19) of the second region (A2) have positive polarity (+), negative polarity (-), and negative polarity (-), respectively, the 1st (19), 1st (20), and 1st (21st) sub-pixels (SP1 (19), SP1 (20), SP1 (21)) have positive polarity (+), negative polarity (-), and negative polarity (-), respectively, the 37th, 38th, and 39th sub-pixels (SP37, SP38, SP39) have positive polarity (+), negative polarity (-), and negative polarity (-), and the 3rd (19), 3rd (20), and 3rd (21st) sub-pixels (SP3 (19), SP3 (20), SP3 (21)) have positive polarity (+), negative polarity (-), and negative polarity (-).

Accordingly, the subpixel of the first region (A1) has a predominant polarity of positive (+), and the subpixel of the second region (A2) has a predominant polarity of negative (-), but the predominant polarity of the positive (+) subpixel of the first region (A1) and the predominant polarity of the negative (-) subpixel of the second region (A2) cancel each other out, so that the sum of the polarities becomes 0.

Accordingly, when the liquid crystal display device (110) according to the embodiment of the present invention displays a second pattern in which a white dot of 1 pixel and a black dot of 1 pixel (1PW/1PB Dot) are repeated, the dominant polarities of the subpixels constituting the white dot of 1 pixel cancel each other out so that the sum of the polarities becomes 0, so that the variation of the common voltage due to the dominant polarity of the data voltage is minimized, and the distortion of the data voltage due to the variation of the common voltage is minimized, thereby preventing defects such as vertical dim or smear, and improving the display quality of the image.

As illustrated in FIG. 6, when the liquid crystal display device (110) according to the embodiment of the present invention displays a third pattern in which two white dots and two black dots (2PW/2PB Dot) are repeated, the 11th sub-pixel (SP11) of the outermost portion (PA) of the first region (A1) and the 12th to 16th sub-pixels (SP12 to SP16) of the central portion (CA), the 31st sub-pixel (SP31) of the outermost portion (PA) and the 32nd to 36th sub-pixels (SP32 to SP36) of the central portion (CA) constitute the first and third white dots, respectively, and the 1st (13) to 1st (18) sub-pixels (SP1 (13) to SP1 (18)) and the 3rd (13) to 3rd (18) sub-pixels (SP3 (13) to SP3 (18)) of the central portion (CA) of the second region (A2) constitute the first and third white dots, respectively. SP3(18)) constitute the second and fourth white dots, respectively, and the 17th to 1st (12th) sub-pixels (SP17 to SP1(12)) and the 37th to 3rd (12th) sub-pixels (SP37 to SP3(12)) in the central portion (CA) between the first and second areas (A1, A2) constitute the first and second black dots, respectively.

Here, the 11th to 16th sub-pixels (SP11 to SP16) of the first region (A1) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), and positive polarity (+), respectively, and the 31st to 36th sub-pixels (SP31 to SP36) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and positive polarity (+), respectively.

Accordingly, the positive polarity (+) and negative polarity (-) of the subpixels of the first region (A1) cancel each other out, so that the sum of the polarities becomes 0.

And, the first (13) to first (18) subpixels (SP1 (13) to SP1 (18)) of the second region (A2) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), and positive polarity (+), respectively, and the third (13) to third (18) subpixels (SP3 (13) to SP3 (18)) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and positive polarity (+), respectively.

Accordingly, the positive (+) and negative (-) polarities of the subpixels of the second area (A2) cancel each other out, so that the sum of the polarities becomes 0.

Accordingly, when the liquid crystal display device (110) according to the embodiment of the present invention displays a third pattern in which two white dots and two black dots (2PW/2PB Dot) are repeated, the polarities of the subpixels constituting each of the two white dots are mutually canceled out so that the sum of the polarities becomes 0, so that the variation of the common voltage due to the dominant polarity of the data voltage is minimized, and the distortion of the data voltage due to the variation of the common voltage is minimized, thereby preventing defects such as vertical dim or smear, and improving the display quality of the image.

As illustrated in FIG. 7, when the liquid crystal display device (110) according to the embodiment of the present invention displays a fourth pattern in which three white dots and three black dots (3PW/3PB Dot) are repeated, the 11th sub-pixel (SP11) of the outermost portion (PA) of the first region (A1) and the 12th to 19th sub-pixels (SP12 to SP19) of the central portion (CA), the 31st sub-pixel (SP31) of the outermost portion (PA) and the 32nd to 39th sub-pixels (SP32 to SP39) of the central portion (CA) constitute the first and third white dots, respectively, and the 1st (19) to 1st (27) sub-pixels (SP1 (19) to SP1 (27)) and the 3rd (19) to 3rd (27) sub-pixels (SP3 (19) to SP3 (27)) of the central portion (CA) of the second region (A2) constitute the first and third white dots, respectively. SP3(27)) constitute the second and fourth white dots, respectively, and the first (10) to first (18) sub-pixels (SP1(10) to SP1(18)) and the third (10) to third (18) sub-pixels (SP3(10) to SP3(18)) of the central portion (CA) between the first and second areas (A1, A2) constitute the first and second black dots, respectively.

Here, the 11th to 19th sub-pixels (SP11 to SP19) of the first region (A1) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), respectively, and the 31st to 39th sub-pixels (SP31 to SP39) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), respectively.

And, the first (19) to first (27) subpixels (SP1 (19) to SP1 (27)) of the second region (A2) have positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), and the third (19) to third (27) subpixels (SP3 (19) to SP3 (27)) have positive polarity (+), negative polarity (-), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), and positive polarity (+), respectively.

Accordingly, the subpixel of the first region (A1) has a predominant polarity of negative (-), and the subpixel of the second region (A2) has a predominant polarity of positive (+), but the predominant polarity of the negative (-) polarity of the subpixel of the first region (A1) and the predominant polarity of the positive (+) polarity of the subpixel of the second region (A2) cancel each other out, so that the sum of the polarities becomes 0.

Accordingly, when the liquid crystal display device (110) according to the embodiment of the present invention displays a fourth pattern in which three white dots and three black dots (3PW/3PB Dot) are repeated, the dominant polarities of the subpixels constituting the three white dots cancel each other out so that the sum of the polarities becomes 0, so that the variation of the common voltage due to the dominant polarity of the data voltage is minimized, and the distortion of the data voltage due to the variation of the common voltage is minimized, thereby preventing defects such as vertical dim or smear, and improving the display quality of the image.

As illustrated in FIG. 8, when the liquid crystal display device (110) according to the embodiment of the present invention displays a fifth pattern in which four white dots and four black dots (4PW/4PB Dot) are repeated, the eleventh sub-pixel (SP11) of the outermost portion (PA) of the first region (A1) and the twelfth to first (12) sub-pixels (SP12 to SP1(12)) of the central portion (CA), the 31st sub-pixel (SP31) of the outermost portion (PA) and the 32nd to third (12) sub-pixels (SP32 to SP3(12)) of the central portion (CA) constitute the first and third white dots, respectively, and the first (25) to first (36) sub-pixels (SP1(25) to SP1(36)) of the central portion (CA) of the second region (A2) and the third (25) to first (36) sub-pixels (SP1(25) to SP1(36)) of the central portion (CA) of the second region (A2) constitute the first and third white dots, respectively. The third (36) sub-pixels (SP3 (25) to SP3 (36)) constitute the second and fourth white dots, respectively, and the first (13) to first (24) sub-pixels (SP1 (13) to SP1 (24)) and the third (13) to third (24) sub-pixels (SP3 (13) to SP3 (24)) in the central portion (CA) between the first and second areas (A1, A2) constitute the first and second black dots, respectively.

Here, the 11th to 12th subpixels (SP11 to SP1(12)) of the first region (A1) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and the 31st to 3rd (12th) subpixels (SP31 to SP3(12)) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), negative polarity (-).

Accordingly, the positive polarity (+) and negative polarity (-) of the subpixels of the first region (A1) cancel each other out, so that the sum of the polarities becomes 0.

And, the first (25) to first (36) subpixels (SP1 (25) to SP1 (36)) of the second region (A2) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), and the third (25) to third (36) subpixels (SP3 (25) to SP3 (36)) have negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-), positive polarity (+), negative polarity (-), positive polarity (+), positive polarity (+), negative polarity (-).

Accordingly, the positive (+) and negative (-) polarities of the subpixels of the second area (A2) cancel each other out, so that the sum of the polarities becomes 0.

Accordingly, when the liquid crystal display device (110) according to the embodiment of the present invention displays a fifth pattern in which four white dots and four black dots (4PW/4PB Dot) are repeated, the polarities of the subpixels constituting each of the four white dots are mutually canceled out so that the sum of the polarities becomes 0, so that the variation of the common voltage due to the dominant polarity of the data voltage is minimized, and the distortion of the data voltage due to the variation of the common voltage is minimized, thereby preventing defects such as vertical dim or smear, and improving the display quality of the image.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the technical spirit and scope of the present invention as set forth in the claims below.

110: Liquid crystal display device 120: Timing control unit
130: Data drive unit 140: Gate drive unit
150: Display panel

Claims (13)

A number of gate wiring;
A plurality of data wires, first auxiliary data wires and second auxiliary data wires intersecting with the above plurality of gate wires;
A plurality of sub-pixels connected to the above plurality of gate wires, the above plurality of data wires, and the first and second auxiliary data wires, and arranged in a matrix form
Including,
The above-mentioned plurality of data wires are arranged between the first and second auxiliary data wires,
Two of the plurality of subpixels are arranged in at least one row between two adjacent data lines of the plurality of data lines,
One of the plurality of sub-pixels is arranged in at least one row between the first auxiliary data wire and the leftmost data wire among the plurality of data wires, and between the rightmost data wire among the plurality of data wires and the second auxiliary data wire.
The above plurality of gate wirings include first to fourth gate wirings,
The above-mentioned plurality of data wires include first and second data wires,
The above multiple subpixels include the 11th to 13th subpixels and the 21st to 23rd subpixels,
The first gate wiring is arranged above the 11th to 13th sub-pixels, the second and third gate wirings are arranged between the 11th to 13th sub-pixels and the 21st to 23rd sub-pixels, and the fourth gate wiring is arranged below the 21st to 23rd sub-pixels.
The first auxiliary data wire is arranged on the left side of the 11th and 21st sub-pixels, the first data wire is arranged between the 11th and 21st sub-pixels and the 12th and 22nd sub-pixels, and the second data wire is arranged on the right side of the 13th and 23rd sub-pixels.
The 11th sub-pixel is connected to the first gate wiring and the first auxiliary data wiring, the 12th sub-pixel is connected to the first gate wiring and the first data wiring, and the 13th sub-pixel is connected to the second gate wiring and the first data wiring.
A liquid crystal display device, wherein the 21st sub-pixel is connected to the third gate wiring and the first data wiring, the 22nd sub-pixel is connected to the third gate wiring and the second data wiring, and the 23rd sub-pixel is connected to the fourth gate wiring and the second data wiring.
In paragraph 1,
A liquid crystal display device, wherein, among the plurality of sub-pixels arranged in one column between the first auxiliary data wire and the leftmost data wire, a sub-pixel arranged in one of the even rows and the odd rows is connected to the first auxiliary data wire, and a sub-pixel arranged in the remaining one of the even and odd rows is connected to the leftmost data wire.
In paragraph 1,
A liquid crystal display device in which the plurality of subpixels arranged in two columns between two adjacent ones of the plurality of data wires are alternately connected to two adjacent ones of the plurality of data wires for each row.
In paragraph 1,
The above plurality of data lines further include third to nth data lines,
A liquid crystal display device wherein the above plurality of sub-pixels further include 14th to 17th sub-pixels and 24th to 27th sub-pixels.
In paragraph 4,
The above 12th sub-pixel is connected to the first gate wiring and the first data wiring,
The above 13th sub-pixel is connected to the second gate wiring and the first data wiring,
The above 14th sub-pixel is connected to the second gate wiring and the second data wiring,
The above 15th sub-pixel is connected to the first gate wiring and the second data wiring,
The above 16th sub-pixel is connected to the second gate wiring and the third data wiring,
The above 17th subpixel is connected to the first gate wiring and the third data wiring,
The above 22nd sub-pixel is connected to the third gate wiring and the second data wiring,
The above 23rd subpixel is connected to the 4th gate wiring and the 2nd data wiring,
The above 24th sub-pixel is connected to the 4th gate wiring and the 3rd data wiring,
The above 25th subpixel is connected to the third gate wiring and the third data wiring,
The above 26th subpixel is connected to the 4th gate wiring and the 4th data wiring,
The above 27th sub-pixel is a liquid crystal display device connected to the third gate wire and the fourth data wire.
In paragraph 4,
During the first frame, a positive data voltage is supplied through the first and third data wires, and a negative data voltage is supplied through the first auxiliary data wire and the second and fourth data wires.
A liquid crystal display device that supplies a negative data voltage through the first and third data wires during the second frame, and supplies a positive data voltage through the first auxiliary data wire and the second and fourth data wires.
A number of gate wiring;
A plurality of data wires, first auxiliary data wires and second auxiliary data wires intersecting with the above plurality of gate wires;
A plurality of sub-pixels connected to the above plurality of gate wires, the above plurality of data wires, and the first and second auxiliary data wires, and arranged in a matrix form
Including,
The above-mentioned plurality of data wires are arranged between the first and second auxiliary data wires,
Two of the plurality of subpixels are arranged in at least one row between two adjacent data lines of the plurality of data lines,
One of the plurality of sub-pixels is arranged in at least one row between the first auxiliary data wire and the leftmost data wire among the plurality of data wires, and between the rightmost data wire among the plurality of data wires and the second auxiliary data wire.
The above plurality of gate wirings include first to fourth gate wirings,
The above-mentioned plurality of data wires include first to nth data wires,
The above plurality of subpixels include the first (2n-6) to the first (2n) subpixel and the second (2n-6) to the second (2n) subpixel,
The above first (2n) subpixel is connected to the first gate wiring and the nth data wiring,
A liquid crystal display device in which the second (2n) subpixel is connected to the third gate wiring and the second auxiliary data wiring.
In paragraph 7,
The above first (2n-6) sub-pixel is connected to the first gate wiring and the (n-3) data wiring,
The above first (2n-5) sub-pixel is connected to the second gate wiring and the (n-3) data wiring,
The above first (2n-4) sub-pixel is connected to the second gate wiring and the (n-2) data wiring,
The above first (2n-3)th subpixel is connected to the first gate wiring and the (n-2)th data wiring,
The above first (2n-2) subpixel is connected to the second gate wiring and the (n-1) data wiring,
The above first (2n-1) subpixel is connected to the first gate wiring and the (n-1) data wiring,
The above second (2n-6) sub-pixel is connected to the third gate wiring and the (n-2) data wiring,
The above second (2n-5) sub-pixel is connected to the fourth gate wiring and the (n-2) data wiring,
The above second (2n-4) sub-pixel is connected to the fourth gate wiring and the (n-1) data wiring,
The above second (2n-3) subpixel is connected to the third gate wiring and the (n-1) data wiring,
The above second (2n-2) subpixel is connected to the fourth gate wiring and the nth data wiring,
A liquid crystal display device in which the second (2n-1) sub-pixel is connected to the third gate wiring and the nth data wiring.
In paragraph 4,
During the first frame, a positive data voltage is supplied through the (n-2)th and nth data wires, and a negative data voltage is supplied through the (n-3)th and (n-1)th data wires and the second auxiliary data wire.
A liquid crystal display device that supplies a negative data voltage through the (n-2)-th and n-th data wires during the second frame, and supplies a positive data voltage through the (n-3)-th and (n-1)-th data wires and the second auxiliary data wire.
In paragraph 1,
The above plurality of sub-pixels display one of the following: a first pattern in which a white vertical line of two pixels and a black vertical line of two pixels are repeated, a second pattern in which a white dot of one pixel and a black dot of one pixel are repeated, a third pattern in which a white dot of two pixels and a black dot of two pixels are repeated, a fourth pattern in which a white dot of three pixels and a black dot of three pixels are repeated, and a fifth pattern in which a white dot of four pixels and a black dot of four pixels are repeated.
A liquid crystal display device in which the sum of the polarities of the subpixels constituting the white vertical lines of the first pattern and the white dots of the second to fifth patterns is 0.
In a driving method of a liquid crystal display device including first to fourth gate wiring, first to nth data wiring, first and second auxiliary data wiring, 11th to 17th sub-pixels and 21st to 27th sub-pixels,
A step of supplying a gate voltage to the first gate wiring, supplying a data voltage to the 11th sub-pixel through the first auxiliary data wiring, supplying the data voltage to the 12th sub-pixel through the first data wiring, supplying the data voltage to the 15th sub-pixel through the second data wiring, and supplying the data voltage to the 17th sub-pixel through the third data wiring;
A step of supplying the gate voltage to the second gate wiring, supplying the data voltage to the 13th sub-pixel through the first data wiring, supplying the data voltage to the 14th sub-pixel through the second data wiring, and supplying the data voltage to the 16th sub-pixel through the third data wiring;
A step of supplying a gate voltage to the third gate wiring, supplying the data voltage to the 21st sub-pixel through the first data wiring, supplying the data voltage to the 22nd sub-pixel through the second data wiring, supplying the data voltage to the 25th sub-pixel through the third data wiring, and supplying the data voltage to the 27th sub-pixel through the fourth data wiring;
A step of supplying the gate voltage to the fourth gate wiring, supplying the data voltage to the 23rd subpixel through the second data wiring, supplying the data voltage to the 24th subpixel through the third data wiring, and supplying the data voltage to the 26th subpixel through the fourth data wiring.
A method for driving a liquid crystal display device including a .
In Article 11,
The above liquid crystal display device further includes first (n-3) to first (2n) sub-pixels and second (n-3) to second (2n) sub-pixels,
A step of supplying a gate voltage to the first gate wiring, supplying a data voltage to the first (2n-6) subpixel through the (n-3)th data wiring, supplying the data voltage to the first (2n-3) subpixel through the (n-2)th data wiring, supplying the data voltage to the first (2n-1) subpixel through the (n-1)th data wiring, and supplying the data voltage to the first (2n) subpixel through the nth data wiring;
A step of supplying the gate voltage to the second gate wiring, supplying the data voltage to the first (2n-5) subpixel through the (n-3)th data wiring, supplying the data voltage to the first (2n-4) subpixel through the (n-2)th data wiring, and supplying the data voltage to the first (2n-2) subpixel through the (n-1)th data wiring;
A step of supplying a gate voltage to the third gate wiring, supplying the data voltage to the second (2n-6) sub-pixel through the (n-2)th data wiring, supplying the data voltage to the second (2n-3) sub-pixel through the (n-1)th data wiring, supplying the data voltage to the second (2n-1) sub-pixel through the nth data wiring, and supplying the data voltage to the second (2n) sub-pixel through the second auxiliary data wiring;
A step of supplying the gate voltage to the fourth gate wiring, supplying the data voltage to the second (2n-5) subpixel through the (n-2)th data wiring, supplying the data voltage to the second (2n-4) subpixel through the (n-1)th data wiring, and supplying the data voltage to the second (2n-2) subpixel through the nth data wiring.
A method for driving a liquid crystal display device further comprising:
In paragraph 1,
The above multiple data lines further include a third data line,
The above multiple subpixels further include the 14th and 15th subpixels and the 24th and 25th subpixels,
The first gate wiring is arranged above the 14th and 15th sub-pixels, the second and third gate wirings are arranged between the 14th and 15th sub-pixels and the 24th and 25th sub-pixels, and the fourth gate wiring is arranged below the 24th and 25th sub-pixels.
The second data wire is arranged between the 13th and 23rd sub-pixels and the 14th and 24th sub-pixels, and the third data wire is arranged to the right of the 15th and 25th sub-pixels.
The above 14th sub-pixel is connected to the second gate wiring and the second data wiring, and the above 15th sub-pixel is connected to the first gate wiring and the second data wiring.
A liquid crystal display device, wherein the 24th sub-pixel is connected to the 4th gate wiring and the 3rd data wiring, and the 25th sub-pixel is connected to the 3rd gate wiring and the 3rd data wiring.