KR102815147B1 - Digital display system including pixel driving circuit formed on interposer - Google Patents

Abstract

A digital display system is disclosed. According to an embodiment, a pixel driving circuit of a digital display device is a circuit formed on an interposer electrically connected to a display substrate through a plurality of bumps, and includes: a row terminal connected to a row line of a row driving circuit among the plurality of bumps and a column terminal connected to a column bump connected to a column line of a column driving circuit among the plurality of bumps; a common element sharing at least one of the row terminal and the column terminal for L (L is a positive integer greater than or equal to 2) display pixels formed on the interposer; and L individual pixel elements connected to the common element and for driving a plurality of light emitters included in each of the L display pixels.

Description

{DIGITAL DISPLAY SYSTEM INCLUDING PIXEL DRIVING CIRCUIT FORMED ON INTERPOSER}

The technical field relates to digital display systems, and to display pixels and their driving circuits.

Displays using light-emitting diodes (LEDs) can be applied to a wide range of fields, from small mobile devices to large outdoor displays. In particular, displays are being used in a wider range of fields, such as various devices for vehicles, AR (Augmented Reality) and VR (Virtual Reality) devices.

Therefore, improvements in various characteristics such as various areas, various shapes, high resolution, process time, manufacturing cost, high reliability, and fast response speed are still required.

In addition, the driving circuit for driving the display still requires improvement in various characteristics.

Korean Patent Publication No. 10-2023-0008684, “Organic light-emitting diode display panel and display device thereof”

The technical problem of the present invention is to provide a digital display system with improved various characteristics through embodiments.

A pixel driving circuit of a digital display device according to one embodiment of the present invention is a circuit formed on an interposer electrically connected to a display substrate through a plurality of bumps, the circuit including: a row terminal connected to a row line of a row driving circuit among the plurality of bumps and a column terminal connected to a column bump connected to a column line of a column driving circuit among the plurality of bumps; a common element sharing at least one of the row terminal and the column terminal for L (L is a positive integer greater than or equal to 2) display pixels formed on the interposer; and L individual pixel elements connected to the common element and for driving a plurality of light emitters included in each of the L display pixels.

The interposer can be any one of a film interposer, a glass interposer, and a silicon interposer.

The pixel driver circuit may further include at least one sensor disposed in a sensor area formed on the interposer.

The common element may include at least one of a power generation unit that generates power required for a pixel driving circuit, a column signal distribution unit that distributes a signal input through a column terminal to L individual pixel elements, and a row signal distribution unit that distributes a signal input through a row terminal to L individual pixel elements.

Each of the L pixel individual elements may include a pixel built-in memory section for storing video data input through a column signal distribution section.

The sub-pixel regions in which a plurality of light-emitting elements of each of the L display pixels are arranged can be formed at the corners or periphery of the display pixels so as to be adjacent to each other.

According to an embodiment of the present invention, a digital display device includes display pixels arranged in M (M is a positive integer) rows and N (N is a positive integer) columns, and a plurality of pixel driving circuits for driving the display pixels, wherein the M x N display pixels are divided into a plurality of macro pixels each composed of m x n (m is a positive integer smaller than M, and n is a positive integer smaller than N) display pixels, each of the plurality of macro pixels is grouped with each of the corresponding pixel driving circuits to form a plurality of groups, and the plurality of groups are formed on a plurality of interposers that are electrically connected to a substrate through a plurality of bumps, and each of the plurality of pixel driving circuits is connected to at least one corresponding row line and at least one column line, and can distribute a signal input through at least one of the row lines and the column lines to the m x n display pixels within the macro pixels grouped into the same group.

Each of the plurality of pixel driving circuits may include a common element sharing at least one of the row lines and the column lines with the m x n display pixels within the same group of macro pixels, and m x n pixel individual elements connected to the common element and driving the plurality of light-emitting elements included in each of the m x n display pixels within the same group of macro pixels.

The number of row lines and column lines shared with m x n display pixels is determined based on at least one of a fill factor and an application type of a pixel driving circuit, and the fill factor can be determined based on a design condition of a size of a pixel area of a display substrate and a sub-pixel area in which a plurality of light-emitting elements are arranged.

The application types of the pixel driving circuit are divided into large-area displays, monitor displays, and mobile displays, and the fill factor can be determined to have a smaller value in the order of large-area displays, monitor displays, and mobile displays.

The interposer can be any one of a film interposer, a glass interposer, and a silicon interposer.

Each of the plurality of pixel driving circuits may further include at least one sensor disposed in a sensor area formed on a corresponding interposer.

Each of the display pixels is arranged in a pixel area formed on a corresponding interposer, and the pixel area includes sub-pixel areas in which a plurality of light-emitting elements are arranged and a non-active area excluding the sub-pixel areas, and each of the plurality of macro pixels includes a pixel driving circuit area in which a pixel driving circuit is arranged, wherein at least a portion of the pixel driving circuit area can overlap the plurality of non-active areas.

Subpixel regions may be formed at the corners or periphery of a display pixel so as to be adjacent to each other.

Each of the m x n pixel individual elements may include a pixel built-in memory section storing video data input through a column signal distribution section and a pixel driver section controlling driving of a plurality of light-emitting elements based on video data and driving signals input through a row signal distribution section.

The present invention can improve the ease of testing and repairing of display pixels and pixel driving circuits by mounting a plurality of display pixels and pixel driving circuits on a single interposer and connecting them to a display substrate.

The present invention can improve various characteristics of a digital display system through the following embodiments.

FIG. 1 is a drawing for explaining a display pixel arrangement structure according to one embodiment.
Figure 2 is a drawing for explaining the structure of a display pixel in Figure 1.
FIG. 3 is a drawing for explaining an example of the layout structure of display pixels and pixel driving circuits according to conventional technology.
FIG. 4 is a drawing for explaining another example of the arrangement structure of display pixels and pixel driving circuits according to the prior art.
Figure 5 is a drawing for explaining the structure of a display driving circuit according to conventional technology.
FIG. 6 is a drawing for explaining a digital display device according to one embodiment of the present invention.
FIGS. 7A to 7F are drawings for explaining a pixel driving circuit according to one embodiment of the present invention.
FIG. 8 is a drawing for explaining an implementation example of a pixel driving circuit according to one embodiment of the present invention.
FIG. 9 is a drawing for explaining macro pixel driving according to one embodiment of the present invention.
FIG. 10 is a drawing for explaining macro pixel driving according to another embodiment of the present invention.
FIG. 11 is a drawing for explaining macro pixel driving according to another embodiment of the present invention.
FIG. 12 is a drawing for explaining a display driving circuit according to one embodiment of the present invention.
Figure 13 is a drawing for explaining an example of a display array configuration according to conventional technology.
FIG. 14a and FIG. 14b are drawings for explaining an example of a display array configuration according to an embodiment of the present invention.
FIG. 15a is a drawing for explaining macro pixel driving applicable to the display array configuration of FIG. 14a, and FIG. 15b is a drawing for explaining macro pixel driving applicable to the display array configuration of FIG. 14b.
FIG. 16 is a drawing for explaining another example of a display array configuration according to one embodiment of the present invention.
FIG. 17 is a drawing for explaining the concept of display pixel current driving according to one embodiment of the present invention.
FIGS. 18 to 20 are drawings for explaining examples of the arrangement structure of display pixels and pixel driving circuits according to embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings and the contents described in the attached drawings, but the present invention is not limited or restricted by the embodiments.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. As used herein, the singular includes the plural unless the context clearly dictates otherwise. The terms "comprises" and/or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and/or elements.

The words “embodiment,” “example,” “aspect,” and “example” as used herein are not to be construed as implying that any aspect or design described is better or advantageous over other aspects or designs.

Also, the term 'or' implies an inclusive or rather than an exclusive or. That is, unless stated otherwise or clear from the context, the expression 'x utilizes a or b' means any one of the natural inclusive permutations.

Additionally, as used in this specification and claims, the singular forms “a” or “an” should generally be construed to mean “one or more,” unless otherwise indicated or clear from the context to be in the singular form.

Additionally, the terms first, second, etc. used in this specification and claims may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used with a meaning that can be commonly understood by a person of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries shall not be ideally or excessively interpreted unless explicitly specifically defined.

Meanwhile, when explaining the present invention, if it is judged that a specific description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. In addition, the terminology used in this specification is a terminology used to appropriately express the embodiments of the present invention, and this may vary depending on the intention of the user or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be made based on the contents throughout this specification.

FIG. 1 is a drawing for explaining a display pixel arrangement structure according to one embodiment.

Referring to FIG. 1, the display panel (100) includes a plurality of display pixels (Px) disposed or arranged in a matrix form of M x N (M and N are each positive integers). Here, the display pixels (Pxs) arranged in M rows and N columns may be referred to as an 'array of pixels'.

Therefore, the array of pixels contains pixels arranged in M rows and N columns.

The M rows can be called a 'row line', and the N columns can be called a 'column line'.

At this time, the row lines may be called horizontal lines or scan lines or gate lines, and the column lines may be called vertical lines or data lines.

The terms row line, column line, horizontal line, and vertical line may be used to refer to lines formed by pixels on a pixel array, and the terms scan line, gate line, and data line may also be used to refer to actual wiring on a display panel (100) through which data or signals are transmitted.

Each display pixel (Px) may include a plurality of light-emitting elements. In this case, the plurality of light-emitting elements may be inorganic light-emitting elements.

Although not shown in FIG. 1, the display panel (100) may include a pixel driving circuit provided for each display pixel (Px).

Figure 2 is a drawing for explaining the structure of a display pixel in Figure 1.

Referring to FIG. 2, a display pixel (200) includes a sub-pixel region (205) in which a plurality of light-emitting elements are arranged. At this time, the sub-pixel region (205) may also be referred to as an 'active' region.

The portion (201) excluding the sub-pixel area (205) in the display pixel (200) may be called a ‘non-active area’ or a ‘black area’.

The plurality of light-emitting elements may include three types of sub-pixels, such as a red (R, red) sub-pixel, a green (G, green) sub-pixel, and a blue (B, blue) sub-pixel. In other words, each of the plurality of light-emitting elements may be called a sub-pixel. At this time, the number of red (R) sub-pixels may be one or two. The types and number of sub-pixels arranged in one display pixel may be combined in various ways.

A fill factor for an array of display pixels can be determined based on the area of a sub-pixel region (205) in a display pixel (200).

Here, the fill factor can be determined based on the design conditions of the size of the pixel area of the display substrate and the sub-pixel area where a plurality of light-emitting elements are arranged.

For example, when the pitch of the display pixel (200) is 0.1 [mm], the display panel (100) can be expressed as a '0.1 mm-pitch display panel'. At this time, the total surface area of the display pixel (200) is 0.01 [mm ² ]. Red, Green, and Blue can be implemented by light-emitting elements, respectively, and the size of each light-emitting element can be 0.0016 [mm ² ]. In this case, since only one light-emitting element chip may emit light in a general display operation, the minimum fill factor F = 0.16 (1.6/10). Meanwhile, the fill factor may be determined by considering the entire area of the sub-pixel area (205), and when the entire area of the sub-pixel area (205) is 0.0048 [[mm ² ], the fill factor F is 0.48.

FIG. 3 is a drawing for explaining an example of the layout structure of display pixels and pixel driving circuits according to conventional technology.

Referring to FIG. 3, a display pixel (200) may be formed with a display pixel driving circuit region (310).

The display pixel driving circuit area (310) may be a semiconductor wafer, for example, a silicon semiconductor wafer, for forming a display pixel driving circuit.

The display pixel driving circuit can be connected to a light-emitting element placed in a sub-pixel area (205) through electrical wiring (301).

FIG. 4 is a drawing for explaining another example of the arrangement structure of display pixels and pixel driving circuits according to the prior art.

Referring to FIG. 4, the display pixel (401) of (A) illustrated in FIG. 4 shows an example in which the area where the light-emitting elements (410) are arranged and the area (420) where the pixel driving circuit is formed are formed on the same layer.

The display pixel (401) of (B) illustrated in Fig. 4 shows an example in which the area where the light-emitting elements (410) are arranged and the area (420) where the pixel driving circuit is formed are formed in different layers.

For example, the region (420) where the pixel driving circuit is formed may be a TFT (Thin Film Transistor) layer under the light-emitting element. At this time, the pixel driving circuit may exist for each light-emitting element corresponding to the TFT layer.

For convenience of explanation in Fig. 4, the electrical wiring connecting the pixel driving circuit and the light-emitting element is omitted.

Figure 5 is a drawing for explaining the structure of a display driving circuit according to conventional technology.

Referring to FIG. 5, the display driving circuit includes a row driver circuit (ROW Driver) (510), a column driver circuit (COLUMN Driver) (520), and pixel driver circuits (Pixel Drivers) provided for each display pixel.

Each pixel driving circuit can provide driving current to the light-emitting element of the display pixel based on the video data voltage applied from the column driving circuit (520). At this time, the video data voltage can include a constant current generator (CCU) data voltage and a PWM (Pulse Width Modulation) data voltage.

Each pixel driving circuit can express the gradation of an image (Gradation expression or Tone-expression) by providing a driving current of a magnitude corresponding to the constant current source data voltage to the light-emitting element for a time corresponding to the PWM data voltage.

The example illustrated in Fig. 5 can be applied to an array of display pixels arranged in a 4 x 5 configuration. Accordingly, the first to fifth column lines are required to supply column signals to 20 display pixels. In addition, four row lines are required to supply row signals to 20 display pixels.

Column lines and row lines corresponding to display pixels increase electrical wiring and can increase manufacturing process costs.

FIG. 6 is a drawing for explaining a digital display device according to one embodiment of the present invention.

Referring to FIG. 6, a digital display device according to an embodiment may include display pixels (1-1, 1-2, ..., 4-5) arranged in M (M is a positive integer) rows and N (N is a positive integer) columns, and a plurality of pixel driving circuits (A-1, A-2, ..., B-3) for driving the display pixels (1-1, 1-2, ..., 4-5).

In the example of FIG. 6, a digital display device according to one embodiment is a common interface-based display device, including a plurality of pixel driving circuits for driving display pixels, wherein the plurality of pixel driving circuits mean 'common interface-based pixel driving circuits'. For example, reference symbol 'A-1' in FIG. 6 is a common interface-based pixel driving circuit for driving a first macro pixel (620).

Hereinafter, the ‘common interface-based pixel driver circuit’ may be simply referred to as a pixel driver circuit.

Additionally, each display pixel is expressed in the format of 'row number - column number', and according to Fig. 6, M is 4 and N is 5, but is not limited thereto.

That is, for the convenience of explanation and comparison with the prior art, the 4 x 5 shape illustrated in Fig. 5 is exemplified. However, it is of course possible to expand the number of display pixels as desired.

In an embodiment of the present invention, the concepts of 'macro pixel' and 'common interface' are introduced to improve the increase in electrical wiring and the complexity of devices.

Specifically, the M x N display pixels can be divided into a plurality of macro pixels (620, 630) each of which is composed of m x n display pixels (m is a positive integer less than M, n is a positive integer less than N).

The term 'common interface' in this specification means a device that shares a column line or column terminal for a macro pixel.

The concepts of 'macropixel' and 'common interface' will become clearer in the following explanations.

In the example illustrated in Fig. 6, the values of m and n are each 2. In addition, adjacent m x n display pixels can also be referred to as 'adjacent L (L is an integer) display pixels'. In this case, the value of L in the example illustrated in Fig. 6 is 4.

Therefore, the M x N display pixels illustrated in FIG. 6 can be divided into multiple macro pixels each consisting of m x n display pixels.

For example, the first macro pixel (620) may be a pixel group composed of display pixels 1-1, 1-2, 2-1, and 2-2.

Additionally, the second macro pixel (630) may be referred to as a pixel group consisting of display pixels 1-5 and 2-5.

Meanwhile, a digital display device may be configured such that each of a plurality of macro pixels is grouped with each of the corresponding pixel driving circuits to form a plurality of groups, and the plurality of groups may be formed on a plurality of interposers that are electrically connected to a substrate through a plurality of bumps.

For example, the interposer can be any one of a film interposer, a glass interposer, and a silicon interposer. If the digital display device is a high-resolution display device, a silicon interposer can be applied, and if the digital display device is a low-resolution display device, a low-cost film interposer can be applied.

Specifically, pixels 1-1, 1-2, 2-1 and 2-2 and pixel driving circuit A-1 may be grouped together and mounted on the same interposer, pixels 1-3, 1-4, 2-3 and 2-4 and pixel driving circuit A-2 may be grouped together and mounted on the same interposer, pixels 3-1, 3-2, 4-1 and 4-2 and pixel driving circuit B-1 may be grouped together and mounted on the same interposer, and pixels 3-3, 3-4, 4-3 and 4-4 and pixel driving circuit B-2 may be grouped together and mounted on the same interposer.

Additionally, pixels 1-5 and 2-5 and pixel driving circuit A-3 may be grouped together and mounted on the same interposer, and pixels 3-5 and 4-5 and pixel driving circuit B-3 may be grouped together and mounted on the same interposer.

Each of the plurality of pixel driving circuits is connected to at least one corresponding row line (611, 613) and at least one column line (601, 603, 605), and can distribute a signal input through at least one of the row lines and the column lines to m x n display pixels within a macro pixel grouped into the same group.

The example of Fig. 6 illustrates a configuration in which one pixel driving circuit is connected to one row line and one column line, respectively, but is not limited thereto. That is, in the case where one pixel driving circuit is connected to 2 x 2 display pixels as in Fig. 6, two row lines and two column lines may be connected to the pixel driving circuit.

Specifically, the pixel driver circuit A-1 can distribute a signal input through the first row line (611) to 2 x 2 display pixels 1-1, 1-2, 2-1, and 2-2 within the first macro pixel (620), and can also distribute a signal input through the first column line (601) to display pixels 1-1, 1-2, 2-1, and 2-2 within the first macro pixel (620).

The pixel driver circuit A-2 can perform the same operation as the pixel driver circuit A-1. Accordingly, the pixel driver circuit A-2 can distribute a signal input through the second column line (603) to the display pixels 1-3, 1-4, 2-3, and 2-4 within the macro pixel, and can also distribute a signal input through the first row line (611) to the display pixels 1-3, 1-4, 2-3, and 2-4 within the macro pixel.

The pixel driver circuit B-1 can distribute a signal input through the first column line (601) to display pixels 3-1, 3-2, 4-1, and 4-2 within the macro pixel (620), and can also distribute a signal input through the second row line (613) to display pixels 3-1, 3-2, 4-1, and 4-2 within the macro pixel.

The pixel driving circuit B-2 can distribute a signal input through the second column line (603) to the display pixels 3-3, 3-4, 4-3, and 4-4 within the macro pixel (620), and the pixel driving circuit B-2 can also distribute a signal input through the second row line (613) to the display pixels 3-3, 3-4, 4-3, and 4-4 within the macro pixel.

The pixel driver circuit A-3 can distribute a signal input through the third column line (605) to display pixels 1-5 and 2-5 within the second macro pixel (630), and can distribute a signal input through the first row line (611) to display pixels 1-5 and 2-5 within the second macro pixel (630).

The pixel driver circuit B-3 can distribute a signal input through the third column line (605) to display pixels 3-5 and 4-5 within the macro pixel, and can also distribute a signal input through the second row line (613) to display pixels 3-5 and 4-5 within the macro pixel.

Each of the plurality of pixel driving circuits (A-1, A-2, ?? B-3) may include a common element that shares at least one of a row line and a column line with m x n display pixels within a macro pixel grouped into the same group, and m x n pixel individual elements connected to the common element and for driving a plurality of light-emitting elements included in each of the m x n display pixels within the macro pixel grouped into the same group.

For example, each of the m x n pixel individual elements may include a pixel built-in memory section that stores video data input through a column signal distribution section and a pixel driver section that controls driving of a plurality of light-emitting elements based on video data and driving signals input through a row signal distribution section.

The number of row lines and column lines shared with the m x n display pixels is determined based on at least one of a fill factor and an application type of a pixel driving circuit, wherein the fill factor can be determined based on a size design condition of a pixel area of a display substrate and a sub-pixel area in which a plurality of light-emitting elements are arranged.

For example, the application types of the pixel driving circuit are divided into large-area displays, monitor displays, and mobile displays, and the fill factor can be determined to have a smaller value in the order of large-area displays, monitor displays, and mobile displays.

Each of the plurality of pixel driving circuits (A-1, A-2, ?? B-3) may further include at least one sensor arranged in a sensor area formed on a corresponding interposer.

Meanwhile, each of the display pixels is arranged in a pixel area formed on a corresponding interposer, wherein the pixel area may include sub-pixel areas in which a plurality of light-emitting elements are arranged and a non-active area excluding the sub-pixel areas.

Additionally, each of the plurality of macro pixels includes a pixel driving circuit area in which a pixel driving circuit is arranged, wherein at least a portion of the pixel driving circuit area may overlap with the plurality of non-active areas.

The above sub-pixel regions may be formed at the corners or periphery of a display pixel so as to be adjacent to each other.

The pixel driving circuit according to one embodiment will be described in more detail later with reference to FIGS. 7a to 7f.

A digital display device according to an embodiment will be described in more detail later with reference to FIGS. 8 to 20.

FIGS. 7A to 7F are drawings for explaining a pixel driving circuit according to one embodiment of the present invention.

Referring to FIGS. 7a to 7f, a pixel driving circuit (MPD, micro pixel driving IC) may be formed on an interposer electrically connected to a display substrate through a plurality of bumps.

For example, the interposer may be any one of a film interposer, a glass interposer, and a silicon interposer. Additionally, the interposer may be formed based on a reel to reel process.

The multiple bumps may include column bumps, row bumps, and voltage bumps.

More specifically, the interposer may have eight bumps formed on its lower surface, namely, a first column bump (Col 1), a second column bump (Col 2), a first row bump (Row 1), a second row bump (Row 2), a V _CC voltage bump (VCC), a V _DD voltage bump (VDD), a reference voltage bump (VREF), and a ground bump (GND), but is not limited thereto, and the configuration of the bumps may be easily changed according to the design. For example, the interposer may have only one column bump and one row bump.

For example, the plurality of bumps may include at least one metal material among gold (Au) and copper (Cu), but is not limited thereto, and known metal materials constituting the bumps may be applied.

More specifically, the plurality of bumps may be at least one of copper pillar bumps having a size (pitch) of 40 μm to 120 μm, gold stud bumps having a size of 20 μm to 60 μm, and micro bumps having a size of 5 μm to 40 μm.

For example, the plurality of bumps may further include magnetic nano powder, which may control the plurality of bumps to self-align and be placed in the correct position during the interposer forming process.

A pixel driver circuit (MPD) may include a row terminal connected to a row line of a row driver circuit among a plurality of bumps and a column terminal connected to a column bump connected to a column line of a column driver circuit among a plurality of bumps.

Additionally, the pixel driver circuit (MPD) may include a common element sharing at least one of the row terminals and the column terminals for L (L is a positive integer greater than or equal to 2) display pixels formed on the interposer, and L individual pixel elements connected to the common element and driving a plurality of light-emitting elements (R, G, B) included in each of the L display pixels.

For example, the pixel driver circuit (MPD) may include, but is not limited to, a first column terminal, a second column terminal, a first row terminal, a second row terminal, a V _CC voltage terminal, a V _DD voltage terminal, a reference voltage terminal, and a ground terminal, each connected to eight bumps through vias formed inside the interposer.

Additionally, the pixel driver circuit (MPD) may further include a plurality of terminals respectively connected to a plurality of light-emitting elements (R, G, B) included in each of the display pixels.

The pixel driver circuit (MPD) may further include at least one sensor disposed in a sensor area (710) formed on the interposer. For example, the at least one sensor may be a touch sensor, but is not limited thereto.

The common element may include at least one of a power generation unit that generates power required for a pixel driving circuit, a column signal distribution unit that distributes a signal input through the column terminal to L individual pixel elements, and a row signal distribution unit that distributes a signal input through the row terminal to L individual pixel elements.

Additionally, each of the L pixel individual elements may include a pixel built-in memory section for storing video data input through the column signal distribution section.

Meanwhile, the sub-pixel regions in which multiple light-emitting elements of each of the L display pixels are arranged may be formed at the corners or periphery of the display pixels so as to be adjacent to each other.

The pixel driver circuit (MPD) may be arranged on the same side (top side) of the interposer as the L individual pixel elements, but is not limited thereto and may be arranged on different sides.

Specifically, the pixel driver circuit (MPD) may be placed on the lower surface (i.e., the back surface) of the interposer, and the L pixel individual elements may be placed on the upper surface of the interposer, thereby minimizing damage to the elements or chips (chip damage) due to electrostatic discharge (ESD) (Fig. 7d).

More specifically, when the pixel driver circuit (MPD) is arranged on the lower surface of the interposer, the pixel individual elements can be arranged on the upper surface of the interposer without spatial constraints even when the number of pixel individual elements (L) is more than 4 (for example, 6, 8, 16, etc.), thereby securing a spatial margin and uniformly arranging the L pixel individual elements within the pixel cluster (FIGS. 7e and 7f).

FIG. 8 is a drawing for explaining an implementation example of a pixel driving circuit according to one embodiment of the present invention.

Referring to FIG. 8, the pixel driving circuit (800) includes a common element (810), a plurality of terminals (861, 863, 865), and pixel individual elements (820, 830, 840, 850).

A common element (810) can share at least one of a column line of a column driving circuit and a row line of a row driving circuit for display pixels within a macro pixel.

Through the common element (810), display pixels within a macro pixel can share at least one of a column line and a row line.

For example, the common element (810) may be a component of the pixel driving circuit A-1 illustrated in FIG. 6. At this time, the common element (810) may share the first column line (601) and the first row line (611) for the display pixels (1-1, 1-2, 2-1, 2-2) within the first macro pixel (620).

The common element (810) can be connected to the low line of the low driving circuit through the low terminal (861) and to the column line of the column driving circuit through the column terminal (863).

Here, the expression 'sharing a column line for the display pixels' may also be expressed as 'sharing a column terminal for the display pixels'. Accordingly, the common element (810) may share at least one of the row terminal (861) and the column terminal (863) for the display pixels within the macro pixel.

The common element (810) may include a power generation unit (811) that generates the power required for the pixel driving circuit, a row signal distribution unit (861), and a column signal distribution unit (863). In addition, the common element (810) may further include a reset unit (not shown).

The reset unit can generate a reset signal for initializing the pixel built-in memory unit included in each pixel individual element (820, 830, 840, 850). At this time, the reset unit can initialize the pixel built-in memory unit based on the row signal and the column signal in a preset video data reset section.

The power generation unit (811) can generate a reference voltage (VDD) using a low signal input from a low terminal (861) and a column signal input from a column terminal (863). The reference voltage can be output to each pixel individual element (820, 830, 840, 850).

In Fig. 8, two thick lines between the common element (810) and the pixel individual elements (820, 830, 840, 850) represent electrical wiring that transmits the reference voltage and reset signal.

The area where the pixel driving circuit (800) is placed may be determined as a specific position within the macro pixel by taking into consideration the manufacturing process of the electrical wiring between the common element (810) and the pixel individual elements (820, 830, 840, 850), the transfer (or Pick and Place) process of the light emitting element, cracks in the glass substrate that may be included in the display panel, bonding of the TFT layer, etc. For example, the area where the pixel driving circuit (800) is placed, i.e., the 'pixel driving circuit area', may be formed to overlap a plurality of non-active areas within the macro pixel.

The column signal distribution unit (815) distributes the signal input through the column terminal (863) to the individual pixel elements (820, 830, 840, 850).

The signal input through the column terminal (863) may be video data stored in the pixel built-in memory of each pixel individual element (820, 830, 840, 850).

Here, the video data can be four digital data for display pixels corresponding to each pixel individual element (820, 830, 840, 850).

Accordingly, four digital data are input at once through the column terminal (863), and the column signal distribution unit (815) can distribute the four digital data to each pixel individual element (820, 830, 840, 850) based on the addressing data or code command included in the input signal.

The low signal distribution unit (813) distributes the signal input through the low terminal (861) to the individual pixel elements (820, 830, 840, 850).

The signal input through the low terminal (861) may be a PWM driving signal for PWM driving each pixel individual element (820, 830, 840, 850).

When a PWM driving signal input through a low terminal (861) is input at once, the low signal distribution unit (813) can distribute the PWM driving signal to each pixel individual element (820, 830, 840, 850) based on the addressing data or code command included in the input signal.

At this time, the low signal distribution unit (813) can distribute a timing signal for controlling the driving time of each display pixel within the macro pixel to each pixel individual element (820, 830, 840, 850).

In Fig. 8, two lines expressed as thin lines between the row signal distribution unit (813) and the pixel individual elements (820, 830, 840, 850) represent electrical wiring for distribution of the row signal. In addition, two lines expressed as thin lines between the column signal distribution unit (815) and the pixel individual elements (820, 830, 840, 850) represent electrical wiring for distribution of the column signal.

Each of the pixel individual elements (820, 830, 840, 850) is connected to a common element (810) and drives a plurality of light emitters included in each of the display pixels within the macro pixel.

Each of the pixel individual elements (820, 830, 840, 850) may include a pixel built-in memory that stores video data input through the column signal distribution unit (815).

Each of the pixel individual elements (820, 830, 840, 850) may include a pixel driver that controls driving of a plurality of light-emitting elements based on video data and a PWM driving signal.

Each of the pixel individual elements (820, 830, 840, 850) may include a plurality of terminals or electrodes connected to the light-emitting elements. For example, each of the pixel individual elements (820, 830, 840, 850) may include R, G, B electrodes connected to the light-emitting elements.

In Fig. 8, reference numerals 865 and 867 represent voltage input terminals and ground terminals that may be additionally provided in the pixel driving circuit.

Meanwhile, a common interface for driving display pixels within a macro pixel can be designed considering the fill factor. In addition, the common interface can be designed considering the application type of the pixel driving circuit.

Therefore, the number of column terminals and row terminals shared for a macro pixel can be determined based on at least one of a fill factor and an application type of a pixel driving circuit.

The application types of pixel driving circuits can be divided into large-area displays, monitor displays, and mobile displays.

At this time, the fill factor can be determined to have a smaller value in the order of large-area displays, monitor displays, and mobile displays.

For example, displays for televisions and large displays for outdoor installation can be large-area displays. In this case, large-area displays can be designed with a fill factor of 10 to 30%.

For example, displays for computer monitors, vehicle displays, and pad devices may be monitor displays. In this case, monitor displays may be designed with a fill factor of 30 to 50%.

For example, a display for a mobile smartphone or wearable device may be a mobile display. In this case, the mobile display may be designed with a fill factor of 50 to 100%.

Below, various examples of common interface designs for driving macro pixels are described through FIGS. 9 to 11.

FIG. 9 is a drawing for explaining macro pixel driving according to one embodiment of the present invention.

The embodiment illustrated in Fig. 9 can be applied to large-area displays.

Referring to Figure 9, a macro pixel is composed of four display pixels Px1, Px2, Px3, and Px4.

At this time, the pixel driving circuit (920a, 920b) may include a first common element arranged in the pixel driving circuit 920a and a second common element arranged in the pixel driving circuit 920b. The pixel driving circuits (920a, 920b) may each include two pixel individual elements.

Pixels Px1 and Px3 can share a column line (901) via electrical wiring (901-1). Pixels Px2 and Px4 can share a column line (903) via electrical wiring (903-1).

Accordingly, each of the pixel driving circuits (920a, 920b) may be provided with a distribution unit for distributing a column line signal.

The example illustrated in Fig. 9 shows a structure in which row lines are not shared in macro pixels. In the case of large-area displays, it may be desirable not to share row lines in consideration of efficient PWM driving and power distribution.

Accordingly, each pixel driving circuit (920a, 920b) may not have a distribution section for distributing low line signals.

The pixel driving circuit (920a) can receive a low signal input from a low line (911) through an electrical wiring (911-1). At this time, the low signal input through the electrical wiring (911-1) is a signal for driving Px1.

The pixel driving circuit (920b) can receive a low signal input from a low line (911) through an electrical wiring (911-2). At this time, the low signal input through the electrical wiring (911-2) is a signal for driving Px2.

The pixel driving circuit (920a) can receive a low signal input from a low line (913) through an electrical wiring (913-1). At this time, the low signal input through the electrical wiring (913-1) is a signal for driving Px3.

The pixel driving circuit (920b) can receive a low signal input from a low line (913) through an electrical wiring (913-2). At this time, the low signal input through the electrical wiring (913-2) is a signal for driving Px4.

FIG. 10 is a drawing for explaining macro pixel driving according to another embodiment of the present invention.

The example shown in Fig. 10 can be applied to a display for a monitor.

Referring to Figure 10, a macro pixel is composed of four display pixels Px1, Px2, Px3, and Px4.

The pixel driver circuit (1020) may include one common element or two common elements. The pixel driver circuit (1020) may include four pixel individual elements.

Pixels Px1 and Px3 can share a column line (1001) via electrical wiring (1001-1). Pixels Px2 and Px4 can share a column line (1003) via electrical wiring (1003-1).

The pixel driving circuit (1020) may have a distribution unit for distributing column line signals.

The example shown in Fig. 10 can share low lines, unlike large-area displays.

The pixel driving circuit (1020) can receive a low signal input from a low line (1011) through an electrical wiring (1011-1). At this time, the low signal input through the electrical wiring (1011-1) is a signal for driving Px1 and Px2. Alternatively, the low signal input through the electrical wiring (1011-1) may be a signal for driving Px1 and Px3.

The pixel driving circuit (1020) can receive a low signal input from a low line (1013) through an electrical wiring (1013-1). At this time, the low signal input through the electrical wiring (1013-1) is a signal for driving Px3 and Px4. Alternatively, the low signal input through the electrical wiring (1013-1) may be a signal for driving Px2 and Px4.

FIG. 11 is a drawing for explaining macro pixel driving according to another embodiment of the present invention.

The example shown in Fig. 11 can be applied to a mobile display.

Referring to Figure 11, a macro pixel is composed of four display pixels Px1, Px2, Px3, and Px4.

The pixel driver circuit (1120) may include one common element and four individual pixel elements.

Pixels Px1, Px2, Px3, and Px4 can share a column line (1101) through electrical wiring (1101-1).

The pixel driving circuit (1120) may be provided with a distribution unit for distributing a column line signal.

Pixels Px1, Px2, Px3, and Px4 can share a low line (1111) via electrical wiring (1111-1).

The pixel driving circuit (1120) may have a distribution unit for distributing a low line signal.

In Fig. 11, the column line (1103) can supply a column signal to the next macro pixel. Additionally, the row line (1113) can supply a row signal to another macro pixel.

FIG. 12 is a drawing for explaining a display driving circuit according to one embodiment of the present invention.

The macro pixels and common interface applied in FIG. 12 may include examples described through FIGS. 6 to 10.

According to one embodiment of the present invention, unlike the display driving circuit according to the prior art illustrated in FIG. 5, the number of column lines and row lines on the display panel can be reduced.

Here, the number of column lines (1221, 1223, 1225) and row lines (1211, 1213) on the display panel can be determined based on the following mathematical expression 1.

[Mathematical formula 1]

Here, Row _N is The number of row lines _, Col _N is the number of column lines, and MOD(X, Y) is the remainder of X/Y.

Referring to Figure 12, M is 4 and m is 2. Therefore, MOD(M, m) is 0, and the total number of row lines is 3.

Referring to Figure 12, N is 5 and n is 2. Therefore, MOD(M, n) is 1, and the total number of column lines is 3.

In Fig. 12, addressing data or code commands for distributing column signals to individual pixel elements may be generated in the COLUMN Driver (1220). Additionally, the addressing data or code commands may be generated in a separate column addressing unit (1230).

To perform the same operation as video data input according to the prior art, the column addressing unit (1230) can input the column signals input from Col1 and Col2 to the pixel driving circuits A-1 and B-1 through serial/parallel conversion or combination.

For example, a signal output from Col1 may be a video data column input to pixels 1-1, 2-1, 3-1, and 4-1. A signal output from Col2 may be a video data column input to pixels 1-2, 2-2, 3-2, and 4-2.

The column addressing unit (1230) can combine column signals input from Col1 and Col2 and convert them into a sequence corresponding to pixels 1-1, 2-1, 1-2, 2-2, 3-1, 4-1, 3-2, 4-2.

At this time, the sequence corresponding to pixels 1-1, 2-1, 1-2, 2-2 is input to pixel driver circuit A-1. The sequence corresponding to pixels 3-1, 4-1, 3-2, 4-2 can be input to pixel driver circuit B-1.

In Fig. 12, addressing data or code commands for distributing row signals to individual pixel elements may be generated in the ROW Driver (1210). Additionally, the addressing data or code commands may be generated in a separate row addressing unit (1240).

For example, a signal output from ROW1 may be a PWM driving signal input to pixels 1-1, 1-2, 1-3, 1-4, and 1-5. A signal output from ROW2 may be a driving signal input to pixels 2-1, 2-2, 2-3, 2-4, and 2-5.

The row addressing unit (1240) can combine column signals input from ROW1 and ROW2 and convert them into a sequence corresponding to pixels 1-1, 1-2, 2-1, 2-2, 1-3, 1-4, 2-3, 2-4, 1-5, 2-5.

At this time, the sequence corresponding to pixels 1-1, 1-2, 2-1, 2-2 is input to pixel driver circuit A-1. The sequence corresponding to pixels 1-3, 1-4, 2-3, 2-4 can be input to pixel driver circuit B-1. The sequence corresponding to pixels 1-5, 2-5 can be input to pixel driver circuit A-3.

By reducing the column lines and row lines formed on the display panel, the thickness of the electrical wiring can be formed thicker. For example, if the thickness of the wire formed on the display panel is thickened, the IR-Drop (voltage drop) can be reduced.

A reduction in the number of lines formed on a display panel can lead to the benefits of simpler electrical wiring, improved assembly, lower manufacturing costs, and reduced complexity.

Figure 13 is a drawing for explaining an example of a display array configuration according to conventional technology.

The introduction of macro pixels and common interfaces can be said to be an improvement in the characteristics of the display system from the viewpoint of the display driving circuit. Macro pixels and common interfaces can also be applied to display array configurations according to the prior art. FIGS. 9 to 11 can be said to be examples of applying macro pixels and common interfaces to display array configurations according to the prior art.

Meanwhile, in the case of a micro LED display that arranges multiple light-emitting elements (1305) in a display pixel (1300), improvement of characteristics considering the transfer (or pick and place) process may be required.

When the chip size is less than 10μm, difficulties arise in the transfer process.

FIGS. 14a and 14b are drawings for explaining an example of a display array configuration according to an embodiment of the present invention.

Referring to FIG. 14a, m x n display pixels (Px1, Px2, Px3, Px4) within a macro pixel (1410) include sub-pixel areas (1411, 1413, 1415, 1417) in which a plurality of light-emitting elements are arranged.

The sub-pixel areas (1411, 1413, 1415, 1417) of each of the m x n display pixels (Px1, Px2, Px3, Px4) can be formed at the corners or periphery of the display pixels so as to be adjacent to each other.

In other words, the sub-pixel areas (1411, 1413, 1415, 1417) can be transferred to the corners or periphery of a display pixel.

At least one macro pixel (1410) among a plurality of macro pixels on the display array may be composed of a first display pixel (Px1), a second display pixel (Px2) positioned to the right of the first display pixel (Px1), a third display pixel (Px3) positioned below the first display pixel (Px1), and a fourth display pixel (Px4) positioned to the right of the third display pixel (Px3).

At this time, at least a portion of the sub-pixel area (1411) of the first display pixel (Px1) may be formed (transferred) to the lower right corner portion of the first display pixel (Px1).

At least a portion of the sub-pixel area (1415) of the second display pixel (Px2) can be formed (transferred) to the lower left corner portion of the second display pixel (Px2).

At least a portion of the sub-pixel area (1413) of the third display pixel (Px3) may be formed at an upper right corner portion of the third display pixel (Px3).

At least a portion of the sub-pixel area (1417) of the fourth display pixel (Px4) may be formed at an upper left corner portion of the fourth display pixel (Px4).

Meanwhile, a macro pixel (1420) may be composed of two display pixels. At this time, the sub-pixel areas (1421, 1423) may be formed at the corners or periphery of the display pixel so as to be adjacent to each other.

The display pixel array structure illustrated in Fig. 14a may have the same physical dimensions and fill factor as the structure according to the prior art.

By dividing adjacent pixels into macro pixel units and applying transfer on a macro pixel basis, transfer of the entire macro pixel can be performed at once. Therefore, transfer efficiency can be improved.

Another transfer method according to an embodiment of the present invention has the advantage of increasing transfer efficiency while maintaining physical size and fill factor.

Meanwhile, depending on the characteristics of the light-emitting element, it may be necessary to minimize light interference between display pixels. Fig. 14b shows an example in which the sub-pixel area is placed on the periphery when it is necessary to reduce light interference between display pixels. At this time, a barrier may be formed in the cover layer to reduce light interference between display pixels.

Referring to FIG. 14b, each of m x n display pixels (Px1b, Px2b, Px3b, Px4b) within a macro pixel (1430) includes a sub-pixel area (1431, 1433, 1435, 1437).

The light emitting elements arranged in the sub-pixel areas (1431, 1433, 1435, 1437) are shown as examples including one red (R) sub-pixel, one green (G) sub-pixel, and one blue (B) sub-pixel, respectively. As described above, the types and numbers of sub-pixels arranged in one display pixel can be combined in various ways.

The sub-pixel areas (1431, 1433, 1435, 1437) are arranged further out from the center (1430-1) of the macro pixel (1430) than a typical sub-pixel area, for example, 1431-1.

The arrows depicted around the center (1430-1) in Fig. 14b indicate that the sub-pixel areas (1431, 1433, 1435, 1437) can be arranged further apart than the general sub-pixel areas.

Similar to the macro pixel (1420) of Fig. 14A, the macro pixel (1440) of Fig. 14B may be composed of two display pixels. At this time, the sub-pixel areas (1441, 1443) may be formed further outward from the center (1440-1) than before.

FIG. 15a is a drawing for explaining macro pixel driving applicable to the display array configuration of FIG. 14a, and FIG. 15b is a drawing for explaining macro pixel driving applicable to the display array configuration of FIG. 14b.

Referring to FIG. 15a, the pixel driving circuit (1520a, 1520b) may include a common element arranged in the pixel driving circuit 1520a and a common element arranged in the pixel driving circuit 1520b. The pixel driving circuits (1520a, 1520b) may each include two pixel individual elements.

Pixels Px1 and Px3 can share a column line (1501) via electrical wiring (1501-1). Pixels Px2 and Px4 can share a column line (1503) via electrical wiring (1503-1).

Referring to Figure 15a, macro pixels may or may not share row lines.

The pixel driver circuit (1520a) can receive a low signal input from a low line (1511) through an electrical wiring (1511-1).

The pixel driver circuit (1520b) can receive a low signal input from a low line (1511) through an electrical wiring (1511-2).

The pixel driver circuit (1520a) can receive a low signal input from a low line (1513) through an electrical wiring (1513-1).

The structure illustrated in Fig. 15a is a structure that can increase transfer efficiency. In addition, by concentrating the sub-pixel area, the pixel driving circuit can be placed in an area where the non-active area is widely distributed. Accordingly, the freedom of placement of the pixel driving circuit can also increase.

Referring to FIG. 15b, the pixel driving circuit (1540) may have the same configuration as the pixel driving circuit (1020) of FIG. 10 or the pixel driving circuit (1120) of FIG. 11.

Accordingly, the pixel driver circuit (1540) may include one common element or two common elements. The pixel driver circuit (1540) may include four pixel individual elements.

Additionally, pixels Px1b and Px2b can share a low line (1515) via electrical wiring (1515-1). Pixels Px3b and Px4b can share a low line (1517) via electrical wiring (1517-1).

Pixels Px1b and Px3b can share column line (1505) via electrical wiring (1505-1). Pixels Px2b and Px4b can share column line (1507) via electrical wiring (1507-1).

At this time, the structure of Fig. 15b has a sub-pixel region located further outward than the structure of Fig. 10 or Fig. 11. Accordingly, the arrangement process of the pixel driving circuit (1540) may be advantageous compared to the structure of Fig. 10 or Fig. 11.

FIG. 16 is a drawing for explaining another example of a display array configuration according to one embodiment of the present invention.

Referring to FIG. 16, a display array according to one embodiment may include a macro pixel (1610) composed of six display pixels (Px1, Px2, Px3, Px4, Px5, Px6).

Considering the pixel dimension and fill factor, six or more adjacent pixels can be configured as one macro pixel.

For example, in the case of mobile displays, the sub-pixel area can be increased to increase the fill factor. Additionally, the sub-pixel areas can be placed at the periphery or corner portions of the display pixels through a transfer process according to one embodiment.

If the fill factor is designed to be close to 1, that is, close to 100%, a macro pixel can be configured in units of eight or more display pixels.

FIG. 17 is a drawing for explaining the concept of display pixel current driving according to one embodiment of the present invention.

Referring to FIG. 17, a display pixel (1710) may include a light emitting element ED and a pixel circuit (40, 50).

The display pixels (1710, 1720, 1730, 1740) may be display pixels within a macro pixel.

Reference numeral 1700 denotes a current supply source. The current supply source (1700) can supply driving current by forming a current mirror with a transistor (1701) within the pixel circuit.

The pixel circuit (40, 50) can control the emission and non-emission of the light-emitting element in response to a control signal, for example, a PWM signal.

The pixel circuit (40, 50) may include a level shifter (1705).

The transistor (1701) can output a driving current. The gate of the transistor (1701) is connected to the transistor of the current supply source (1700), and a current mirror circuit can be formed with the current supply source (1700).

The pixel circuit (40, 50) is additionally provided with a transistor that can be turned on or off depending on the voltage output from the level shifter (1705).

The level shifter (1705) is connected to the output terminal of the PWM (Pulse Width Modulation) controller (1701) and can convert the voltage level of the first PWM signal output by the PWM controller (1741) to generate a second PWM signal. The level shifter (1705) can generate a second PWM signal by converting the first PWM signal into a gate-on voltage level signal capable of turning on a transistor and a gate-off level signal capable of turning off the transistor.

The pulse voltage level of the second PWM signal output by the level shifter (1705) may be higher than the pulse voltage level of the first PWM signal. The level shifter (1705) may include a boost circuit that boosts the input voltage. The level shifter (1705) may be implemented with a plurality of transistors.

The turn-on time and turn-off time of the transistor during one frame can be determined according to the pulse width of the first PWM signal.

The pixel circuit (40) can store the bit value of data applied from the column driving circuit during the data writing period for each frame, and generate a first PWM signal based on the bit value and the clock signal during the light emission period.

The pixel circuit (50) may include a PWM controller (1741) and memory (1743).

The PWM controller (1741) can generate a first PWM signal based on a clock signal (CK) input during the light emission period and a bit value of data read from the memory (1743).

When a clock signal in subframe units is input, the PWM controller (1741) can read the corresponding data bit value from the memory (1743) and generate a first PWM signal.

The PWM controller (1741) can control the pulse width of the first PWM signal based on the bit value of data in subframe units and the signal width of the clock signal.

For example, if the bit value of the video data is 1, the pulse output of the PWM signal can be turned on for the signal width of the clock signal, and if the bit value of the video data is 0, the pulse output of the PWM signal can be turned off for the signal width of the clock signal.

The PWM controller (1741) may include one or more logic circuits (e.g., OR gate circuits) implemented with one or more transistors.

FIGS. 18 to 20 are drawings for explaining examples of the arrangement structure of display pixels and pixel driving circuits according to embodiments of the present invention.

Referring to FIG. 18, a macro pixel (1800) shows an example in which the area where the light-emitting elements (1811, 1813, 1815, 1817) of each display pixel are arranged and the pixel driving circuit area (1820) are formed on the same layer.

For example, the structure illustrated in FIG. 18 can be applied to all of the examples illustrated in FIGS. 9, 10, and 11.

Referring to FIG. 19, a macro pixel (1900) includes an area (1920) where common elements are arranged and areas (1931, 1933, 1935, 1937) where four individual elements are arranged.

At this time, the area (1920) where the common elements are arranged and the areas (1931, 1933, 1935, 1937) where the four individual elements are arranged can be formed on the same layer. And, the area where the light-emitting elements (1911, 1913, 1915, 1917) of the display pixels are arranged can be formed on an upper layer of the areas (1931, 1933, 1935, 1937) where the individual elements are arranged.

The structure illustrated in Fig. 19 can be mainly applied to the examples illustrated in Figs. 9 and 10.

Referring to Fig. 20, the macro pixel (2000) can be applied to a structure with a high fill factor.

The area where common elements are placed and the area where individual elements are placed can be formed in one area (2020) without distinction.

The area where the light-emitting elements (2011, 2013, 2015, 2017) of the display pixels are arranged may be formed in a different layer from the area (2020) where the pixel driving circuit is arranged.

In FIGS. 18 to 20, at least a portion of the area where the pixel driving circuit is arranged can be formed to overlap the non-active area of each of the display pixels. Through this, process efficiency and wafer-to-wafer bonding efficiency can be increased.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone, but those skilled in the art will appreciate that the processing device may include multiple processing elements and/or multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

Although the embodiments have been described above by way of limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, appropriate results can be achieved even if the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or are replaced or substituted by other components or equivalents.

Therefore, other implementations, other embodiments, and equivalents to the claims are also included in the scope of the claims described below.

MPD: Pixel Driver Circuit Interposer: Interposer
Substrate: substrate R, G, B: light-emitting element

Claims (15)

delete delete delete delete delete delete A digital display device that drives display pixels digitally.
M x N pixels formed on the upper surface of the interposer, arranged in M (where M is a positive integer) rows and N (where N is a positive integer) columns;
A light emitting element arranged in each of the above M x N pixels;
A total of K macro pixel driving circuits that configure two or more adjacent pixels among the above M x N pixels as one macro pixel, thereby forming a total of K (M x N > K) macro pixels, and provide a PWM control method driving current for video data and gradation expression to each macro pixel, and control the light emission of a light emitting element included in each macro pixel;
A column driving circuit for transmitting video data to the K macro pixel driving circuits;
A row driving circuit providing a timing signal for controlling the driving time to the K macro pixel driving circuits; and
An interposer is included that forms electrical contact between the light-emitting element included in each of the above macro pixels and the macro pixel driving circuit, and between the column driving circuit and the row driving circuit and the macro pixel driving circuit.
The light emitting element and the macro pixel driving circuit included in each of the above macro pixels are formed on the interposer, and the column driving circuit and the row driving circuit are formed outside the interposer.
The above macro pixel driving circuit is formed on the lower surface or upper surface of the interposer, and the light emitting element included in each macro pixel is formed on the upper surface of the interposer.
The above macro pixel driving circuit controls the light emission of the light emitting element included in each macro pixel by PWM control through the electrical contact formed in the interposer.
The above column driving circuit and the above row driving circuit are characterized in that they form electrical contact with the interposer through a plurality of bumps to supply the video data and timing signal to the macro pixel driving circuit.
Digital display device. In Article 7,
Each of the above macro pixel driving circuits,
The plurality of bumps are connected through vias formed inside the interposer, and the column driving circuit and the row driving circuit are formed on a display substrate connected to the plurality of bumps.
Digital display device. In Article 8,
The above multiple bumps are for each macro pixel,
It consists of a first column bump (Col 1), a second column bump (Col 2), a first row bump (Row 1), a second row bump (Row 2), a VCC voltage bump (VCC) and a VDD voltage bump (VDD) for power supply, a reference voltage bump (VREF) for providing a reference voltage, and a ground bump (GND) for grounding.
Digital display device. delete In Article 7,
The above interposer is one of a film interposer, a glass interposer, and a silicon interposer.
Digital display device. In Article 7,
Each of the above macro pixel driving circuits further includes at least one sensor arranged in a sensor area formed on a corresponding interposer.
Digital display device. In Article 7,
Each of the above display pixels is arranged in a pixel area formed on a corresponding interposer,
The above pixel area includes sub-pixel areas in which a plurality of light-emitting elements are arranged and a non-active area excluding the sub-pixel areas,
Each of the above macro pixels includes a pixel driving circuit area in which a macro pixel driving circuit is arranged, and at least a portion of the pixel driving circuit area overlaps a plurality of non-active areas.
Digital display device. delete In Article 7,
The above macro pixel driving circuit,
A pixel built-in memory that stores video data transmitted through the above column driving circuit; and
A pixel driver that controls PWM driving of the plurality of light-emitting elements based on the timing signal input through the video data and the row driving circuit.
Digital display device.