KR102701801B1 - Light emitting diode with high process margin - Google Patents

Abstract

In one embodiment, a light emitting diode comprises: a substrate; a semiconductor laminate disposed on the substrate; a finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge; a current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; and a metal layer disposed between the substrate and the current block layer and electrically connected to the semiconductor laminate through the holes of the current block layer, wherein the holes of the current block layer are disposed below regions between the fingers so as not to overlap the fingers, and a maximum spacing between the fingers which are parallel to each other is less than 120 um, and a minimum spacing is greater than 90 um.

Description

LIGHT EMITTING DIODE WITH HIGH PROCESS MARGIN

The present invention relates to a light emitting diode having a large process margin, and more particularly, to a light emitting diode capable of reducing the deviation in forward voltage between light emitting diodes manufactured through the same process on a single wafer.

Light-emitting diodes are inorganic semiconductor light-emitting devices that convert electrical energy into light energy. Typically, light-emitting diodes include an active layer between an n-type semiconductor layer and a p-type semiconductor layer, and current is injected through electrodes that make ohmic contacts with the n-type semiconductor layer and the p-type semiconductor layer, and light is generated through the recombination of electrons and holes in the active layer.

Since semiconductor layers have higher resistivity than metals, it is necessary to distribute the current in the horizontal direction of the light-emitting diode. Fingers are generally used for current distribution.

Additionally, when the electrodes overlap each other vertically, a current blocking layer is used to distribute the current horizontally. In particular, the current blocking layer is arranged opposite the finger so that the current from the finger is distributed horizontally.

Meanwhile, light-emitting diodes are formed by depositing semiconductor layers on a wafer, and multiple light-emitting diodes are formed together on a single wafer. Light-emitting diodes manufactured on the same wafer need to have small performance deviations, and therefore light-emitting diodes with a large process margin are required.

The problem to be solved by the present invention is to provide a vertically structured light-emitting diode that has a large process margin and can reduce performance differences between light-emitting diodes manufactured through the same process.

According to one embodiment of the present invention, a light emitting diode comprises: a substrate; a semiconductor laminate disposed on the substrate; a finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge; a current block layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; and a metal layer disposed between the substrate and the current block layer and electrically connected to the semiconductor laminate through the holes of the current block layer, wherein the holes of the current block layer are disposed below regions between the fingers so as not to overlap the fingers, and a maximum spacing between the fingers which are parallel to each other is less than 120 um, and a minimum spacing is 90 um or more.

According to embodiments of the present invention, a vertically structured light-emitting diode can be provided that increases process margin and reduces performance deviation and forward voltage deviation between light-emitting diodes.

FIG. 1 is a schematic plan view of a vertical light-emitting diode according to one embodiment of the present invention.
Figure 2a is a schematic cross-sectional view taken along the cutting line AA of Figure 1.
Fig. 2b is a schematic cross-sectional view taken along the cut line BB of Fig. 1.
Figure 3 is a plan view illustrating samples used to verify forward voltage and optical output according to the number of fingers and p contact area.
Figure 4a is a graph showing the forward voltage according to the number of fingers and the p contact area.
Figure 4b is a graph showing the optical output according to the number of fingers and the p contact area.
Figure 5 is a graph for explaining changes in forward voltage and optical output according to deformation of the finger structure.
Figure 6 is a graph for explaining the change in forward voltage and optical output according to the branching structure of the finger.
Figure 7 is a graph explaining the change in forward voltage and optical output depending on whether an additional pad layer is applied.
Figure 8 is a graph explaining the external quantum efficiency according to the finger width.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples so that the spirit of the present disclosure can be sufficiently conveyed to those skilled in the art to which the present disclosure belongs. Accordingly, the present disclosure is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. In addition, when one component is described as being "over" or "on" another component, it includes not only the cases where each part is "directly over" or "directly on" the other part, but also the cases where another component is interposed between each component and the other component. Like reference numerals represent like components throughout the specification.

According to one embodiment of the present disclosure, a light emitting diode is provided, comprising: a substrate; a semiconductor laminate disposed on the substrate; a finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge; a current blocking layer disposed between the semiconductor laminate and the substrate and having a plurality of holes exposing the semiconductor laminate; and a metal layer disposed between the substrate and the current blocking layer and electrically connected to the semiconductor laminate through the holes of the current blocking layer, wherein the holes of the current blocking layer are disposed below regions between the fingers so as not to overlap with the fingers, and a maximum spacing between the fingers which are parallel to each other is less than 120 um and a minimum spacing is 90 um or more.

By setting the spacing between fingers within the above range, it is possible to reduce performance deviations between light-emitting diodes manufactured together even when deviations in the spacing between fingers occur due to fluctuations in the manufacturing process.

The total contact area of the metal layer connected to the semiconductor laminate through the holes may be within a range of 1 to 4% of the lower surface area of the semiconductor laminate.

By setting the contact area of the metal layer within this range, the performance variation between light-emitting diodes can be reduced.

Furthermore, the total contact area of the metal layer may be within a range of 1 to 2% of the lower surface area of the semiconductor laminate. By limiting the total contact area of the metal layer within this range, a decrease in the light output of the light-emitting diode can be suppressed.

In one embodiment, the number of fingers may be nine or more.

Meanwhile, the minimum transverse gap between the holes and the fingers can be 20 um or more.

Further, the spacing between the holes may be greater than the minimum spacing between the holes and the fingers.

The above holes may have a width (or diameter) smaller than the maximum spacing between the hole and the finger.

The finger structure may include: a pad positioned near the center of one edge of the semiconductor laminate; a connecting portion extending to both sides of the pad along the one edge of the semiconductor laminate; fingers extending from the connecting portion toward the other edge of the semiconductor laminate; and at least one finger extending from the pad toward the other edge of the semiconductor laminate.

Furthermore, the light emitting diode may further include an additional pad layer disposed on the pad.

In one embodiment, the pad can be formed of AuGe or AuGe-Ni, and the additional pad layer can be formed of Au.

Meanwhile, the connecting portion may include a first connecting portion extending from the pad with a constant width; and a second connecting portion extending from the pad in contact with the first connecting portion, wherein the second connecting portion is shorter than the first connecting portion.

In some embodiments, a plurality of fingers may extend from the pad.

Furthermore, at least one of the fingers extending from the pad may include an extension extending toward an edge other than one edge and the other edge of the semiconductor laminate structure.

Meanwhile, the metal layer may include an ohmic layer and a reflective metal layer.

In one embodiment, the line width of each of the fingers can be in the range of 4 um to 5 um.

In one embodiment, the semiconductor laminate may include at least two active layers.

The above light-emitting diode and the semiconductor laminate may include an n-type semiconductor layer and a p-type semiconductor layer, and the finger structure may contact the n-type semiconductor layer, and the metal layer may contact the p-type semiconductor layer.

In certain embodiments, the n-type and p-type semiconductor layers may include AlGaAs, and the active layer may include GaAs.

Furthermore, the n-type semiconductor layer may include a roughened surface.

It may further include a protective layer covering the above finger structure and the semiconductor laminate.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view of a vertical light emitting diode according to one embodiment of the present invention, FIG. 2a is a schematic cross-sectional view taken along the cutting line A-A of FIG. 1, and FIG. 2b is a schematic cross-sectional view taken along the cutting line B-B of FIG. 1.

Referring to FIGS. 1, 2a and 2b, the light emitting diode may include a substrate (51), a semiconductor laminate (30), a current blocking layer (33), a metal layer (35), a bonding layer (53), a finger structure (55), a protective layer (57) and an additional pad layer (59).

The substrate (51) is a supporting substrate for supporting the semiconductor laminate (30), and is not particularly limited. In one embodiment, the substrate (51) has electrical conductivity and may be, for example, a silicon substrate or a metal substrate. In another embodiment, the substrate (51) may be an insulating substrate, such as a sapphire substrate, a quartz substrate, or a glass substrate.

The substrate (51) is distinct from the growth substrate used to grow the semiconductor laminate (30), and the semiconductor laminate (30) grown on the growth substrate is transferred to the substrate (51). The growth substrate can be separated from the semiconductor laminate (30).

The semiconductor laminate (30) is arranged on one surface of the substrate (51). As shown in FIGS. 2A and 2B, the semiconductor laminate (30) may have a size smaller than the area of the substrate (51), and thus, the substrate (51) may be exposed around the semiconductor laminate (30).

The semiconductor laminate (30) may have a multi-stack structure having a plurality of active layers (23, 29). The upper active layer (23) may be interposed between the upper first conductive semiconductor layer (21) and the upper second conductive semiconductor layer (25), and the lower active layer (29) may be interposed between the lower first conductive semiconductor layer (27) and the lower second conductive semiconductor layer (31). Meanwhile, a tunnel layer (26) may be arranged between the upper second conductive semiconductor layer (25) and the lower first conductive semiconductor layer (27).

The upper first conductive semiconductor layer (21) can be formed of a III-V series compound semiconductor, for example, can be formed of AlGaAs. The lower first conductive semiconductor layer (21) can be formed of a single layer, but is not limited thereto and can be formed of multiple layers.

The upper first-challenge semiconductor layer (21) may include an n-type impurity, for example, an n-type impurity, Si, within a range of 5E17/cm ³ to 5E19/cm ³ . In this range, the efficiency of carrier injection into the upper active layer (23) can be increased, and light absorption by carriers can be reduced.

The upper first-challenge semiconductor layer (21) may have roughness on its upper surface. The roughness may be formed particularly in the area between the fingers (55d, 55e). The roughness improves light extraction efficiency.

The upper active layer (23) generates light by the recombination of electrons and holes. The upper active layer (23) may have a single quantum well structure having a single well layer or a multi-quantum well structure having a barrier layer together with a plurality of well layers. The well layer has a band gap narrower than the band gaps of the upper first conductivity type semiconductor layer (21) and the upper second conductivity type semiconductor layer (25). The well layer may be formed of a III-V series compound semiconductor expressed as AlGaInAsP, and may be formed of, for example, GaAs. The upper active layer (23) may have a multi-quantum well structure in which, for example, GaAs/AlGaAs are repeatedly stacked.

The upper second conductive semiconductor layer (25) can be formed of a III-V series compound semiconductor and can have a p-type impurity such as C, Mg or Zn. The upper second conductive semiconductor layer (25) has a wider band gap than the band gap of the upper active layer (23). The upper second conductive semiconductor layer (25) can be formed of a compound semiconductor having the same composition as the upper first conductive semiconductor layer (21), for example, AlGaAs, but is not necessarily limited thereto.

The upper second challenge type semiconductor layer (25) may be formed as a single layer, but is not limited thereto and may be formed as multiple layers.

The lower first conductive semiconductor layer (27) can be formed of a III-V series compound semiconductor, for example, can be formed of AlGaAs. The lower first conductive semiconductor layer (27) can be formed as a single layer, but is not limited thereto and can be formed as a multilayer.

The lower active layer (29) may have a single quantum well structure or a multiple quantum well structure. The well layer of the lower active layer (29) may be formed of a III-V series compound semiconductor expressed as AlGaInAsP, but is formed of a compound semiconductor having a band gap equal to or smaller than that of the well layer of the upper active layer (23). The lower active layer (29) may also have a multiple quantum well structure in which GaAs/AlGaAs are repeatedly stacked, similar to the upper active layer (23). Light generated in the lower active layer (29) transmits through the upper active layer (23) and is emitted to the outside. In order to prevent light generated in the lower active layer (29) from being absorbed by the upper active layer (23), the band gap of the well layer in the upper active layer (23) needs to be similar to or wider than the band gap of the well layer in the lower active layer (29).

The lower second conductive semiconductor layer (31) may be formed of a III-V series compound semiconductor and may have a p-type impurity such as C, Mg or Zn. The lower second conductive semiconductor layer (31) may be formed of a III-V series compound semiconductor having the same composition as the lower first conductive semiconductor layer (27), for example, AlGaAs, but is not limited thereto.

Meanwhile, the tunnel layer (26) tunnel-joins the lower first-conductivity semiconductor layer (27) and the upper second-conductivity semiconductor layer (25). The tunnel layer (26) is a layer grown as a thin film of a III-V series compound semiconductor doped with a high concentration of n/p-type impurities, and may be, for example, AlGaAs. The tunnel layer (26) may have an n/p-type impurity doping concentration within the range of, for example, 1E20/cm ³ to 1E21/cm ³ . The forward voltage may be reduced by the doping concentration within this range.

The tunnel layer (26) contains a high concentration of n/p-type impurities, thereby tunnel-bonding the lower first conductive semiconductor layer (27) and the upper second conductive semiconductor layer (25). Accordingly, current can flow from the lower first conductive semiconductor layer (25) to the upper second conductive semiconductor layer (27).

In this embodiment, the tunnel layer (26) is described as being positioned between the lower first conductive semiconductor layer (27) and the upper second conductive semiconductor layer (25) for tunnel junction, but the tunnel layer (26) may be omitted, and the lower first conductive semiconductor layer (27) may include a high concentration of impurities to perform the function of the tunnel layer.

By stacking the upper active layer (23) and the lower active layer (29), the light output of the light-emitting diode can be improved through dual emission.

The current blocking layer (33) is arranged between the lower second conductive semiconductor layer (31) and the substrate (51). The current blocking layer (33) may be formed of, for example, silicon oxide or silicon nitride. The current blocking layer (33) may be formed to a thickness capable of transmitting light of a corresponding wavelength range, and may be formed of, for example, silicon oxide having a thickness of about 1500 Å. In another embodiment, the current blocking layer (33) may be formed as a distributed Bragg reflector.

The current block layer (33) has holes (33a) that expose the lower second conductive semiconductor layer (31). The holes (33a) may be arranged so as not to vertically overlap with the finger structures (55). For example, the holes (33a) may have a diameter of about 10 μm and may be spaced apart from the fingers (55d, 55e) by 20 μm or more in the horizontal direction. Meanwhile, the spacing between the holes (33a) may be larger than the minimum spacing between the holes and the fingers, for example, may be 50 μm or more.

The contact area between the metal layer (35) and the second conductive semiconductor layer (31) is determined by the holes (33a). The contact area determined by the holes (33a) may be 1% or more of the lower surface area of the entire semiconductor laminate (30). When the ratio of the contact area is 1% or more of the lower surface area of the semiconductor laminate (30), the performance deviation of the light-emitting diode due to the deviation of the contact area, for example, the deviation of the forward voltage, can be reduced. Meanwhile, the performance deviation of the light-emitting diode can be reduced as the contact area increases, but if the contact area increases excessively, the light output is greatly reduced. Therefore, the contact area may be 4% or less, further, 2% or less, of the lower surface area of the semiconductor laminate (30).

The metal layer (35) may be arranged between the current block layer (33) and the substrate (51). The metal layer (35) may include an ohmic layer that contacts the lower second conductive semiconductor layer (31). The ohmic layer may be formed of, for example, TiAu or AuBe. The ohmic layer contacts the lower second conductive semiconductor layer (31) within the holes (33a). The ohmic layer may be formed to be, for example, about 3000 Å.

Meanwhile, the metal layer (35) may include a reflective metal layer covering the ohmic layer. For example, the reflective metal layer may include Au, Cu, Ag, Al, Pd, and may be formed of an alloy such as AgPdCu. The reflective metal layer may be formed to a thickness of, for example, about 0.5 um.

The bonding layer (53) bonds the semiconductor laminate (30) to the substrate (51). The bonding layer (53) can bond the metal layer (35) and the substrate (51). The material of the bonding layer (53) is not particularly limited, and may be formed of, for example, an eutectic alloy such as Au-In or Au-Sn.

Meanwhile, the finger structure (55) is arranged on the semiconductor laminate (30) and may include a pad (55a), a first connection portion (55b), a second connection portion (55c), and finger portions (55d, 55e). The finger structure (55) may be formed of an AuGe or AuGe-Ni alloy layer and may make an ohmic contact with the upper first conductive semiconductor layer (21).

The pad (55a) may be placed near the center of one edge of the semiconductor laminate (30). The pad (55a) may have a relatively large area for bonding wires.

The first connecting portion (55b) can extend from the pad (55a) to both sides along the one edge. The first connecting portion (55b) can have a wider width than the fingers (55d, 55e). The first connecting portion (55b) can extend with a width of, for example, 30 um or more.

The second connecting portion (55c) extends from the pad (55a) to both sides. The second connecting portion (55c) extends by being attached to the first connecting portion (55b), and is shorter than the first connecting portion (55b). Accordingly, the first connecting portion (55b) and the second connecting portion (55c) provide a connecting portion (55bc) having a step portion formed. That is, a connecting portion having a relatively wide width is formed around the pad (55a), and a connecting portion having a relatively narrow width is formed on the outside thereof.

The length of the second connecting portion (55c) is smaller than that of the first connecting portion (55b), and in particular, may be smaller than half that of the first connecting portion (55b). The width of the second connecting portion (55c) may be smaller than or equal to that of the first connecting portion (55b). The second connecting portion (55c) may have a width of, for example, about 10 um.

The fingers (55d, 55e) extend from one edge toward the opposite edge at substantially equal intervals from each other. The fingers (55d) extend from the pad (55a), and the fingers (55e) extend from the connecting portion (55bc).

One of the fingers (55d) may be arranged at the center of the semiconductor laminate (30). The finger (55d) arranged at the center may be straight. Meanwhile, the other fingers (55d) other than the finger (55d) arranged at the center are generally straight, but may have a shape that is first bent near the pad (55a). In order to ensure that the fingers (55d) are spaced apart from each other at equal intervals, the fingers (55d) may extend diagonally from the pad (55a) toward an edge other than one edge and the other edge, and then extend straight toward the opposite edge. The extension portion extending in the diagonal direction may be straight or curved.

Meanwhile, the fingers (55e) extend from the connecting portion (55bc) toward the edge of the opposite layer. The fingers (55e) may all be straight.

The width of the fingers (55d, 55e) can be selected according to the current density. In general, when the bottom surface area of the semiconductor laminate (30) is about 1 mm×1 mm, the width of the fingers (55d, 55e) can be selected, for example, within a range of 4 um to 5 um. Under a high current density, for example, when a current of 500 mA is injected under the area of the semiconductor laminate (30), the width of the fingers (55d, 55e) can be closer to about 4 um rather than 5 um, thereby increasing the internal quantum efficiency. In contrast, under a low current density, for example, when a current of 100 mA is injected under the area of the semiconductor laminate (30), the width can be closer to about 5 um rather than 4 um. When operating under both high current density and low current density conditions, the width can be close to about 4.5 um. Both fingers (55d) and fingers (55e) can have the same width, but are not necessarily limited thereto.

The fingers (55d, 55e) are spaced apart from each other at substantially the same interval, except around the pad (55a), as illustrated in FIG. 1. The interval between the fingers (55d, 55e) affects the forward voltage of the light-emitting diode. In particular, the interval between the fingers (55d, 55e) can affect the deviation of the forward voltage between the light-emitting diodes according to the change in the process conditions. During the light-emitting diode manufacturing process, a large number of light-emitting diodes are manufactured simultaneously under the same conditions. These light-emitting diodes have deviations in their performance due to slight differences in the process conditions, and it is advantageous that the deviation in the performance of the light-emitting diodes does not significantly occur even when the process conditions fluctuate.

To this end, the performance deviation of the light-emitting diodes is different depending on the spacing between the fingers (55d, 55e), and in particular, the performance deviation of the light-emitting diodes can be reduced when the spacing between the fingers is less than about 120 um. Here, the spacing between the fingers means the spacing between the fingers that are parallel to each other. By adjusting the number of fingers under the width of the above fingers (55d, 55e), the spacing between the fingers (55d, 55e) can be adjusted. For example, the number of fingers (55d, 55e) under the area of the above semiconductor laminate (30) can be 9 or more. The spacing between the fingers (55d, 55e) can be generally constant, but is not necessarily limited thereto. At this time, the maximum spacing between the fingers that are parallel to each other can be less than about 120 um.

Meanwhile, as the number of fingers (55d, 55e) increases, the forward voltage can be lowered, but the fingers (55d, 55e) block light, thereby reducing the light output. Therefore, the spacing between the fingers (55d, 55e) may be 90 um or more, and the number of fingers (55d, 55e) under the area of the semiconductor laminate (30) above may be 11 or less. The spacing between the fingers (55d, 55e) may be generally constant, but is not necessarily limited thereto. In this case, the minimum spacing between the fingers that are parallel to each other may be about 90 um or more.

The protective layer (57) covers the finger structure (55) and the upper first conductive semiconductor layer (21). The protective layer (57) may be formed along the unevenness formed on the surface of the first conductive semiconductor layer (21). The protective layer (57) may also cover the side surface of the semiconductor laminate (30) and may cover the substrate (51) exposed around the semiconductor laminate (30). The protective layer (57) may have an opening exposing the pad (55a).

The protective layer (57) can be formed of silicon oxide or silicon nitride, and can be formed to a thickness that can transmit light of a corresponding wavelength range, and for example, can be formed of silicon oxide having a thickness of about 4500 Å.

An additional pad layer (59) may be formed on the pad (55a). The additional pad layer (59) may be positioned within the opening of the protective layer (57). The additional pad layer (59) may be formed of, for example, an Au layer having a thickness of about 1 μm.

(Experimental Example 1)

Figure 3 is a plan view illustrating samples used to verify forward voltage and optical output according to the number of fingers and p contact area.

Light-emitting diodes having 7 to 11 fingers were fabricated on a semiconductor laminate (30) having an area of about 1×1 mm ² . The width of the fingers was set to be the same at about 4.5 um, and the connection portion (55bc) was set to have a constant width without a step portion. The structures of the light-emitting diodes other than the finger structures were fabricated under the same conditions as described above with reference to FIGS. 1, 2a, and 2b. The forward voltage and light output of the light-emitting diode having 7 fingers and a p-contact area ratio of 0.5% to the semiconductor laminate were each set to 100%, and the forward voltage and light output of the other light-emitting diodes were expressed as a percentage.

Fig. 4a is a graph for showing the forward voltage according to the number of fingers and the p contact area, and Fig. 4b is a graph for showing the light output according to the number of fingers and the p contact area.

First, referring to Fig. 4a, as the number of fingers increases, the forward voltage of the light-emitting diode decreases. It can be seen that the decrease in forward voltage due to the increase in the number of fingers is larger as the number of fingers decreases and the p-contact area decreases. That is, the decrease in forward voltage is significantly larger when the number of fingers increases from 7 to 8 than when the number of fingers increases from 9 to 10 or from 10 to 11. It can also be seen that the forward voltage decreases significantly when the number of fingers increases from 8 to 9. Therefore, in terms of forward voltage reduction, the number of fingers is appropriate to be 9 or more.

Furthermore, as the p contact area increases from 0.5% to 4%, the forward voltage decrease due to the difference in contact area becomes smaller. That is, the forward voltage change is smaller when the p contact area increases from 1% to 1.5% than when it increases from 0.5% to 1%. The forward voltage change due to the increase in the p contact area becomes smaller as the number of fingers increases. That is, the forward voltage deviation between the light-emitting diodes can be reduced as the number of fingers and the p contact area increase.

Meanwhile, referring to Fig. 4b, the light output decreases as the number of fingers increases and as the p contact area increases. The decrease in light output as the number of fingers increases is generally constant, and therefore, it can be seen that the decrease in light output does not decrease even if the number of fingers increases. On the other hand, although the change in light output tends to decrease as the p contact area increases, the difference was not large. That is, the light output decreases by a generally constant amount even as the p contact area increases. Therefore, in order to prevent the decrease in light output, it is necessary to reduce the number of fingers and reduce the p contact area.

In conclusion, in order to reduce the deviation of the forward voltage, it is recommended that the number of fingers be 9 or more and the p-contact area be 1% or more, but in order to prevent a significant decrease in the light output, it is not recommended that the number of fingers exceed 11 or the p-contact area be 4% or more. Furthermore, under the above conditions, the number of fingers is 9 and the p-contact area is in the range of 1 to 2%.

Figure 5 is a graph for explaining changes in forward voltage and optical output according to deformation of the finger structure. A reference sample (comparative example) in which a finger structure was formed using only a first connection part (55b) without a second connection part (55c), and a sample of an example (exemplary example) in which a step-type connection part (55bc) was formed by adding a second connection part (55c) were manufactured, and forward voltage and optical output were measured.

Referring to Fig. 5, the sample of the embodiment showed a 0.3% decrease in forward voltage and a 0.6% increase in light output compared to the comparative example. That is, by adding the second connector (55c), the forward voltage can be reduced and the light output can be increased.

Fig. 6 is a graph for explaining changes in forward voltage and optical output according to the branching structure of the fingers. A comparative sample in which all fingers except for the fingers extending straightly from the pad (55a) were manufactured to extend from the connection portion, and a sample of an embodiment in which a plurality of fingers extend from the pad (55a) as described in Fig. 1 were manufactured, and forward voltage and optical output were measured.

Referring to Fig. 6, the sample of the embodiment showed a 5.5% decrease in forward voltage and a 0.5% increase in light output compared to the comparative example. That is, by increasing the fingers extending from the pad (55a), the forward voltage can be reduced and the light output can be increased.

Figure 7 is a graph for explaining the change in forward voltage and optical output depending on whether an additional pad layer is applied. A sample of an example in which an additional pad layer (59) of Au is formed on the pad (55a) was produced along with a comparative example in which a wire is directly bonded to the pad (55a). The additional pad layer (59) was formed with Au to a thickness of about 1 um.

Referring to Fig. 7, by arranging an additional pad layer (59), a forward voltage reduction of 4.9% and an optical output increase of 1.4% could be achieved. Furthermore, the wire bonding strength could also be increased in the wire bonding process of the package.

Figure 8 is a graph to explain the external quantum efficiency according to the finger width. Samples were manufactured with the same number of fingers (9) and only the widths of the fingers were 4 um, 5 um, and 6 um, and the external quantum efficiency according to the finger width was derived.

Referring to Fig. 8, under the low current density condition of 100 mA, the width had a good value at about 5 um and a relatively low value at 4 um. In contrast, under the high current density condition of 500 mA, the external quantum efficiency tended to decrease as the width increased.

That is, it shows that the external quantum efficiency is higher when the finger width is closer to 5 um under low current density conditions, and when the finger width is closer to 4 um under low current density conditions.

Additionally, in determining the finger width, the optimal finger width for the device injection current can be determined through the change in external quantum efficiency at low and high currents.

Although various embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments. In addition, matters or components described for one embodiment may be applied to other embodiments as long as they do not depart from the technical spirit of the present disclosure.

Claims (20)

substrate;
A semiconductor laminate disposed on the above substrate;
A finger structure disposed on the semiconductor laminate and including a plurality of fingers extending from one edge of the substrate to the other edge;
A current blocking layer disposed between the semiconductor laminate and the substrate, the current blocking layer having a plurality of holes exposing the semiconductor laminate; and
A metal layer is disposed between the substrate and the current block layer and is electrically connected to the semiconductor laminate through holes of the current block layer,
The holes of the current block layer are positioned below the areas between the fingers so as not to overlap with the fingers,
The maximum spacing between parallel fingers is less than 120 um, and the minimum spacing is more than 90 um,
The above finger structure is,
A pad positioned near the center of one edge of the semiconductor laminate;
A connecting portion extending along one edge of the semiconductor laminate to both sides of the pad;
Fingers extending from the connecting portion toward the other edge of the semiconductor laminate; and
A light emitting diode comprising at least one finger extending from the pad toward the other edge of the semiconductor laminate. In claim 1,
A light emitting diode wherein the total contact area of the metal layer connected to the semiconductor laminate through the holes is within a range of 1 to 4% of the lower surface area of the semiconductor laminate. In claim 2,
A light emitting diode wherein the total contact area of the metal layer is within a range of 1 to 2% of the lower surface area of the semiconductor laminate. In claim 1,
The number of the above fingers is 9 light emitting diodes. In claim 1,
A light emitting diode wherein the minimum horizontal gap between the holes and the fingers is 20 um or more. In claim 5,
A light emitting diode wherein the spacing between the holes is greater than the minimum spacing between the holes and the fingers. In claim 5,
The above holes are light emitting diodes having a width smaller than the maximum gap between the holes and the fingers. delete In claim 1,
A light emitting diode further comprising an additional pad layer disposed on the above pad. In claim 9,
The above pad is formed of AuGe or AuGe-Ni,
The above additional pad layer is a light emitting diode formed of Au. In claim 1,
The above connecting portion has a first connecting portion extending from the pad with a constant width; and
A second connecting portion extending from the pad and in contact with the first connecting portion,
The above second connecting portion is a shorter light emitting diode than the above first connecting portion. In claim 1,
A light emitting diode having a plurality of fingers extending from the above pad. In claim 12,
A light emitting diode, wherein at least one of the fingers extending from the pad includes an extension portion extending toward an edge other than one edge and the other edge of the semiconductor laminate. In claim 1,
A light-emitting diode comprising an ohmic layer and a reflective metal layer. In claim 1,
A light emitting diode wherein each of the above fingers has a line width in the range of 4 um to 5 um. In claim 1,
A light emitting diode, wherein the semiconductor laminate comprises at least two active layers. In claim 16,
A light emitting diode, wherein the semiconductor laminate comprises an n-type semiconductor layer and a p-type semiconductor layer, wherein the finger structure contacts the n-type semiconductor layer, and the metal layer contacts the p-type semiconductor layer. In claim 17,
The above n-type and p-type semiconductor layers include AlGaAs,
A light-emitting diode wherein the active layer comprises GaAs. In claim 17,
A light-emitting diode wherein the n-type semiconductor layer includes a roughened surface. In claim 1,
A light emitting diode further comprising a protective layer covering the finger structure and the semiconductor laminate.