KR102700006B1 - Resistance variable memory having MIT selection device including distributed metal nanoparticles and method for fabricating the same - Google Patents

Abstract

The present invention relates to a variable resistance memory device having an MIT selection device including dispersed metal nanoparticles and a manufacturing method thereof. The variable resistance memory device comprises: first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells provided at intersections between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes an MIT selection device and a variable resistor connected in series between the corresponding first and second conductive lines. The MIT selection device includes an MIT material layer formed of a material having metal insulator transition characteristics and metal nanoparticles dispersed in the MIT material layer. The MIT material layer includes vanadium oxide such as VO, V_2O_3, or V_2O_5. The metal nanoparticles include platinum (Pt).

Description

Resistance variable memory having MIT selection device including distributed metal nanoparticles and method for fabricating the same

The present invention relates to a variable resistance memory device having an MIT selection element including dispersed metal nanoparticles and a method for manufacturing the same, and more particularly, to a variable resistance memory device having an MIT selection element utilizing a metal-insulator transition phenomenon as a switching element and a method for manufacturing the same.

Recently, with the spread of portable digital devices and the increasing need to store digital data, interest in nonvolatile memory devices that do not lose stored data even when power is turned off is increasing.

Among the semiconductor devices mentioned above, flash memory devices that can be manufactured at low cost by being based on a silicon process, such as DRAM memory devices, are widely used. However, flash memory devices have the disadvantages of having a relatively low integration level, slow operating speed, and requiring a relatively high voltage to store data compared to DRAM memory devices, which are volatile memory devices.

To overcome the shortcomings of such flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) have been proposed. Such next-generation nonvolatile memory devices can operate at relatively low voltages and have fast access times, which significantly offsets the shortcomings of flash memory devices.

In particular, research on next-generation nonvolatile memory devices having a three-dimensional cross-point array structure has been actively conducted recently in response to high integration demands. The cross-point array structure is a structure in which multiple bit lines and multiple word lines are arranged to intersect each other and memory cells are arranged at the cross points of the bit and word lines, thereby enabling random access to each memory cell, making it easy to implement data storage (program) and reading (read).

In such a crosspoint structured memory system, parasitic signals due to interference of unaddressed cells located on the same bit line or word line delay the execution of the crosspoint array. The most serious problem affecting the reliable operation is known as a "sneak current path", and a "sneak current path" means a leakage current that appears when a specific memory cell is addressed within the crosspoint array. The sneak current path affects, for example, the read result of the cell state, causing the memory cell state to be read incorrectly. The sneak path problem generally occurs in passive arrays, especially in situations where the memory cell exhibits linear or nearly linear current-voltage characteristics in the low resistance state. In the high resistance state of the cell, a misread can occur due to leakage current passing through the adjacent cell in the low resistance state.

Therefore, in order to integrate such variable resistance memory devices into a cross-point array, a selection element that acts as a switch capable of suppressing leakage current is required.

The background technology of this invention is disclosed in registered patent No. 10-1481920.

The technical problem to be solved by the present invention is to provide a variable resistance memory device with improved switching characteristics and electrical characteristics and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present invention for achieving the above object, a variable resistance memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, each of the memory cells including an MIT selection element and a variable resistor connected in series between corresponding first and second conductive lines, wherein the MIT selection element includes an MIT material layer formed of a material having metal-insulator transition characteristics and metal nanoparticles dispersed within the MIT material layer, wherein the MIT material layer includes a vanadium oxide such as VO, VO ₂ , V ₂ O ₃ , or V ₂ O ₅ , and the metal nanoparticles include platinum (Pt).

According to one embodiment, the first conductive line includes a barrier film pattern and a lower conductive film pattern sequentially laminated on the substrate, and the variable resistor includes a lower electrode, a variable resistor pattern, and an upper electrode sequentially laminated on the MIT selection element, wherein the MIT selection element may include a body portion whose upper surface and lower surface are in contact with the lower electrode and the lower conductive film pattern, respectively, and a protrusion portion that protrudes from the lower surface of the body portion and is inserted into the lower conductive film pattern.

In one embodiment, the MIT material layer can be a single-crystalline or polycrystalline film.

According to embodiments of the present invention, since the MIT selection element is implemented to include an MIT material layer having metal-insulator transition characteristics and metal nanoparticles dispersed within the MIT material layer, it is possible to operate so that the same amount of current can flow even with a smaller voltage, and the memory effect capable of remembering a previous operation can be maintained for a longer period of time than before, so that the switching characteristics can be further improved.

In addition, the MIT selection element implemented in this manner has the effect of suppressing the occurrence of sneak current by minimizing the voltage drop of the switching element and reducing the threshold voltage value of the element.

Furthermore, since the MIT selection element has a protrusion in the form of being inserted into the lower conductive film pattern, the electrical characteristics can be improved due to a decrease in contact resistance resulting from an increase in the contact area.

As a result, it may be possible to provide a variable resistance memory device with improved switching characteristics and electrical characteristics.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.
FIG. 2 is a plan view illustrating a variable resistance memory device having an MIT selection element including dispersed metal nanoparticles according to one embodiment of the present invention.
Figures 3a and 3b are cross-sectional views taken along lines I-I' and II-II' of Figure 2, respectively.
FIG. 4 is a cross-sectional view illustrating an MIT selection device according to embodiments of the present invention.
FIGS. 5A to 11A are cross-sectional views corresponding to line II' of FIG. 2, illustrating a method for manufacturing a variable resistance memory device having an MIT selection element including dispersed metal nanoparticles according to one embodiment of the present invention.
FIGS. 5b to 11b are cross-sectional views corresponding to line II-II' of FIG. 2, illustrating a method for manufacturing a variable resistance memory device having an MIT selection element including dispersed metal nanoparticles according to one embodiment of the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the present embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In this specification, when it is said that an element is “on” another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. Also, in this specification, when it is said that a part “includes” a certain element, this does not mean that other elements are excluded, but rather that other elements can be included, unless otherwise specifically stated.

The terms “about,” “substantially,” and the like, as used throughout this specification, are used in a meaning that is at or near the numerical value when manufacturing and material tolerances inherent in the meanings referred to are presented, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure, which contains precise or absolute values to aid understanding of this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.

Referring to FIG. 1, first conductive lines (CL1) extending in a first direction (D1) and second conductive lines (CL2) extending in a second direction (D2) intersecting the first direction (D1) may be provided. The second conductive lines (CL2) may be spaced apart from the first conductive lines (CL1) along a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2). A memory cell stack (MCA) may be provided between the first conductive lines (CL1) and the second conductive lines (CL2). The memory cell stack (MCA) may include memory cells (MC) provided at each of the intersections of the first conductive lines (CL1) and the second conductive lines (CL2). The memory cells (MC) may be arranged two-dimensionally to form rows and columns. Although one memory cell stack (MCA) is illustrated in the present embodiment, embodiments of the present invention are not limited thereto. Memory cell stacks (MCAs) can be provided in multiples and stacked vertically.

Each of the memory cells (MC) may include a selection element (SW) and a variable resistor (VR). The selection element (SW) and the variable resistor (VR) may be connected in series with each other between a pair of conductive lines (CL1, CL2) connected thereto.

For example, a selection element (SW) and a variable resistor (VR) included in each of the memory cells (MC) may be connected in series with each other between a corresponding first conductive line (CL1) and a corresponding second conductive line (CL2). Here, the first conductive line (CL1) may be a word line and the second conductive line (CL2) may be a bit line, or vice versa. In addition, although FIG. 1 illustrates that the variable resistor (VR) is provided on the selection element (SW), embodiments of the present invention are not limited thereto. Unlike FIG. 1, the selection element (SW) may also be provided on the variable resistor (VR).

Voltage is applied to the variable resistor (VR) of the memory cell (MC) through the first challenge line (CL1) and the second challenge line (CL2), so that current can flow through the variable resistor (VR), and the resistance of the variable resistor (VR) of the selected memory cell (MC) can change depending on the applied voltage.

According to the change in resistance of the variable resistor (VR), the memory cell (MC) can store digital information such as "0" or "1", and the digital information can be erased from the memory cell (MC). For example, data can be written in the memory cell (MC) in a high resistance state "0" and a low resistance state "1". Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell (MC) according to the embodiments of the present invention is not limited to the digital information of the high resistance state "0" and the low resistance state "1" exemplified above, and can store various resistance states.

For example, the variable resistor (VR) may include a transition metal oxide layer, in which case at least one electrical path may be created or destroyed within the variable resistor (VR) by a program operation. When the electrical path is created, the variable resistor (VR) may have a low resistance value, and when the electrical path is destroyed, the variable resistor (VR) may have a high resistance value. By utilizing the difference in resistance value of the variable resistor (VR), the variable resistance memory element may store data.

As another example, the variable resistor (VR) may include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistor (VR) is not limited thereto, and may include any variable resistor whose resistance value changes depending on an applied voltage.

The selection element (SW) may be a device based on a threshold switching phenomenon having a nonlinear (e.g., S-shaped) I-V curve. For example, the selection element (SW) may be a threshold switching selection element (hereinafter, may be referred to interchangeably as an MIT selection element) utilizing a metal-insulator transition (MIT) phenomenon. The metal-insulator transition (MIT) phenomenon refers to a phenomenon in which metallic properties are exhibited above a specific temperature and insulating properties are exhibited below a specific temperature.

According to embodiments of the present invention, the selection element (SW) may include a metal-insulator transition (MIT) material layer (ML) formed of a material having MIT characteristics and metal nanoparticles (MP) dispersed within the MIT material layer (ML). This will be described in detail later.

Any memory cell (MC) can be addressed by selecting a first challenge line (CL1) and a second challenge line (CL2), and by applying a predetermined signal between the first challenge line (CL1) and the second challenge line (CL2), the memory cell (MC) is programmed, and by measuring a current value through the first challenge line (CL1), information according to the resistance value of a variable resistor constituting the corresponding memory cell (MC) can be read.

Referring to FIGS. 2, 3a, 3b, and 4 below, a variable resistance memory device having an MIT selection element including dispersed metal nanoparticles (MPs) according to one embodiment of the present invention is described.

FIG. 2 is a plan view showing a variable resistance memory device having an MIT selection device including dispersed metal nanoparticles according to one embodiment of the present invention. FIGS. 3A and 3B are cross-sectional views taken along lines I-I' and II-II' of FIG. 2, respectively. FIG. 4 is a cross-sectional view for explaining an MIT selection device according to embodiments of the present invention.

Referring to FIGS. 2, 3A, and 3B, first conductive lines (115) and second conductive lines (190) may be sequentially provided on a substrate (100). The first conductive lines (115) may extend in a first direction (D1) substantially parallel to a top surface of the substrate (100) and may be spaced apart from each other in a second direction (D2) substantially parallel to the top surface of the substrate (100) and intersecting the first direction (D1). The second conductive lines (190) may extend in the second direction (D2) and be spaced apart from each other in the first direction (D1). The first conductive lines (115) and the second conductive lines (190) may be spaced apart from each other in a third direction (D3) perpendicular to the top surface of the substrate (100).

The substrate (100) may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a Si-Ge substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, etc. The substrate (100) may also include a III-V group compound, such as InP, GaP, GaAs, GaSb, etc. Meanwhile, although not shown, a p-type or n-type impurity may be injected into the upper portion of the substrate (100) to form a well.

Each of the first challenge lines (115) may include a barrier film pattern (104) and a lower conductive film pattern (114) sequentially laminated on a substrate (100). Each of the barrier film pattern (104) and the lower conductive film pattern (114) may include a metal such as tungsten (W), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a metal nitride thereof.

In one embodiment, the barrier film pattern (104) and the lower conductive film pattern (114) may include different materials. For example, the barrier film pattern (104) may include titanium nitride (TiN), and the lower conductive film pattern (114) may include tungsten (W). The barrier film pattern (104) may prevent a metal component of the lower conductive film pattern (114) from diffusing downward, and may also increase adhesion between the lower conductive film pattern (114) and a structure below it.

Each of the second challenge lines (190) may include a metal, such as tungsten (W), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a metal nitride thereof.

The second challenge line (190) may further include a barrier film pattern (not shown). The second challenge line (190) may include a material that is substantially the same as or different from the lower challenge film pattern (114). As an example, the second challenge structure (252) may include tungsten (W).

Although not illustrated, an insulating film (not illustrated) may be interposed on the substrate (100). In this case, the first conductive line (102) may be formed on the insulating film. In addition, a peripheral circuit (not illustrated) including a transistor, a contact, a wiring, etc. may be formed on the substrate (100). In addition, a lower insulating film (not illustrated) that at least partially covers the peripheral circuit may be formed on the substrate (100).

Memory cells (MC) may be arranged between first conductive lines (115) and second conductive lines (190), and may be located at intersections of the first conductive lines (115) and second conductive lines (190), respectively. The memory cells (MC) may be two-dimensionally arranged along a first direction (D1) and a second direction (D2). The memory cells (MC) may form one memory cell stack (MCA). For convenience of explanation, only one memory cell stack (MCA) is illustrated, but a plurality of memory cell stacks (MCAs) may be stacked on a substrate (100) along a third direction (D3). In this case, structures corresponding to the first conductive lines (115), the second conductive lines (190), and the memory cells (MC) may be repeatedly stacked on the substrate (100).

Each of the memory cells (MC) may include an MIT selection element (124) and a variable resistor (180) sequentially stacked on a first challenge line (115).

The MIT selection element (124) is a device based on a threshold switching phenomenon having a nonlinear (e.g., S-shaped) I-V curve, and may be a threshold switching selection element utilizing a metal-insulator transition (MIT) phenomenon. According to the concept of the present invention, the MIT selection element (124) may include an MIT material layer (ML) having a metal-insulator transition (MIT) characteristic and metal nanoparticles (MP) dispersed within the MIT material layer (ML), as illustrated in FIG. 4.

For example, the MIT material layer (ML) may include vanadium oxide such as VO, VO ₂ , V ₂ O ₃ , or V ₂ O ₅ . The MIT material layer (ML) has high resistance like an insulator when a voltage lower than a threshold voltage is applied, but has low resistance like a metal when a voltage higher than the threshold voltage is applied. The MIT material layer (ML) having such MIT semiconductor properties can reduce the size of the device (even a size of 10 nm or less is possible) because current can flow without a semiconductor layer, thereby enabling formation of a highly integrated device. In addition, the MIT material layer (ML) may be a single-crystalline or polycrystalline film. Even when the MIT material layer (ML) is a single-crystalline or polycrystalline film, the device yield is excellent and uniform characteristics can be exhibited even over a large area.

When metal nanoparticles (MP) are dispersed within an MIT material layer (ML) having metal-insulator transition properties, the switching characteristics can be further improved because the same amount of current can flow even with a smaller voltage and the memory effect that can remember previous operations can be maintained for a longer period of time than before. For example, the metal nanoparticles (MP) can include platinum (Pt).

In this way, the MIT selection element (124) implemented to include an MIT material layer (ML) having metal-insulator transition (MIT) characteristics and metal nanoparticles (MP) dispersed within the MIT material layer (ML) has the effect of minimizing the voltage drop of the switching element and reducing the threshold voltage value of the element, thereby suppressing the occurrence of sneak current.

According to one embodiment, the MIT selection element (124) may include a body portion (124a) whose upper and lower surfaces are in contact with the lower electrode (134) of the variable resistor (180) and the lower conductive film pattern (114) of the first conductive line (115), respectively, and a protrusion (124b) that protrudes from the lower surface of the body portion (124a) and is inserted into the lower conductive film pattern (114). Since the MIT selection element (124) has the protrusion (124b) that is inserted into the lower conductive film pattern (114), a contact area with the first conductive line (115) increases, and thus, contact resistance may be reduced. As a result, a decrease in a voltage applied to the memory cell (MC) due to contact resistance and a decrease in a current flowing through the memory cell (MC) may be prevented.

The variable resistor (180) may include a lower electrode (134), a variable resistor pattern (144), and an upper electrode (154) sequentially stacked on an MIT selection element (124).

Each of the lower electrode (134) and the upper electrode (154) may include a metal nitride or a metal silicon nitride, such as titanium nitride (TiNx), titanium silicon nitride (TiSiNx), tungsten nitride (WNx), tungsten silicon nitride (WSiNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), zirconium nitride (ZrNx), zirconium silicon nitride (ZrSiNx), and the like. In one embodiment, the lower and upper electrodes (134, 154) may include a different material from the first and second conductive lines (105, 190). Alternatively, the lower and upper electrodes (134, 154) may include substantially the same material as the first and second conductive lines (105, 190).

According to one embodiment, the variable resistance pattern (144) may include a material whose electrical resistance changes due to oxygen vacancy or oxygen movement, and thus, the variable resistance memory device may be a resistive random access memory (ReRAM) device.

For example, the variable resistance pattern (144) may include a perovskite series material or a transition metal oxide. Examples of the perovskite series material include STO (SrTiO3), BTO (BaTiO3), PCMO (Pr1-XCaXMnO3), etc. Examples of the transition metal oxide include titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), niobium oxide (NbOx), cobalt oxide (CoOx), tungsten oxide (WOx), lanthanum oxide (LaOx), zinc oxide (ZnOx), etc. These may be used alone or in combination of two or more.

The variable resistance pattern (144) may have a single film structure including the material described above, or a composite film structure in which multiple films are laminated.

According to another embodiment, the variable resistance pattern (144) may include a material whose resistance changes according to a phase change, and thus the variable resistance memory device may be a phase change random access memory (PRAM) device. For example, the variable resistance pattern (144) may include a chalcogenide series material in which germanium (Ge), antimony (Sb), and/or tellurium (Te) are combined in a predetermined ratio.

The laminated structure of the sequentially stacked MIT selection element (124), the lower electrode (134), the variable resistance pattern (144), and the upper electrode (154) can be connected in series between a pair of conductive lines (102, 190) connected thereto. In the present embodiment, the first and second conductive lines (115, 190), the MIT selection element (124), and the variable resistor (180) can correspond to the first and second conductive lines (CL1, CL2), the selection element (SW), and the variable resistor (VR) of FIG. 1, respectively.

A first mold pattern (162) may be provided in an island shape between the first challenge line (115) and the outer walls of the second direction (D2) of the memory cell (MC), and a second mold pattern (170) in a line shape may be provided between the outer walls of the first direction (D1) of the memory cell (MC). Each of the first mold pattern (162) and the second mold pattern (170) may include silicon oxide and/or silicon nitride.

As described above, a variable resistance memory element can be provided in which variable resistance memory cells (MC) are provided at the cross points of a first challenge line (115) and a second challenge line (190).

FIGS. 5A to 11A are drawings for explaining a method for manufacturing a variable resistance memory device having an MIT selection device including dispersed metal nanoparticles according to an embodiment of the present invention, and are cross-sectional views corresponding to the line I-I' of FIG. 2. FIGS. 5B to 11B are drawings for explaining a method for manufacturing a variable resistance memory device having an MIT selection device including dispersed metal nanoparticles according to an embodiment of the present invention, and are cross-sectional views corresponding to the line II-II' of FIG. 2 For components substantially the same as those described with reference to FIGS. 2, 3A, 3B, and 4, the same reference numerals may be provided, and redundant descriptions may be omitted.

Referring to FIGS. 5a and 5b, a barrier film (102) and a lower conductive film (112) can be formed on a substrate (100).

The barrier film (102) and the lower conductive film (112) may be formed of a metal, such as tungsten (W), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a metal nitride thereof. For example, the barrier film (102) may be formed of titanium nitride (TiN), and the lower conductive film (112) may be formed of tungsten (W).

Each of the barrier film (102) and the lower conductive film (112) can be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process.

Referring to FIGS. 6A and 6B, insertion grooves (112h) may be formed on the upper portion of the lower conductive film (112). For example, the insertion grooves (112h) may be formed by forming a mask pattern (not shown) on the lower conductive film (112) and performing an etching process using the mask pattern as an etching mask. The insertion grooves (112h) may be formed to be spaced apart from each other in the first direction (D1) and the second direction (D2) and to form a plurality of rows and columns.

Referring to FIGS. 7a and 7b, an MIT selection element film (120) may be formed on a lower conductive film (112) in which insertion grooves (112h) are formed. The MIT selection element film (120) may be formed to fill the insertion grooves (112h) and cover the entire upper surface of the lower conductive film (112).

According to embodiments of the present invention, the MIT selection element film (120) may include an MIT material layer (ML) and metal nanoparticles (MP) dispersed within the MIT material layer (ML), as illustrated in FIG. 4. In the present invention, the MIT material layer (ML) may be formed of vanadium oxide, such as VO, VO ₂ , V ₂ O ₃ , or V ₂ O ₅ , and the metal nanoparticles (MP) may include platinum (Pt).

The MIT material layer (ML) can be formed using, for example, a physical vapor deposition (PVD) method such as sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, molecular beam epitaxy (MBE), or chemical vapor deposition (CVD).

The metal nanoparticles (MP) may be formed to be dispersed in the MIT material layer (ML) in-situ during the formation of the MIT material layer (ML), or may be formed to be dispersed in the MIT material layer (ML) through a separate process. For example, the MIT material layer (ML) and the metal nanoparticles (MP) may be formed through a multiple sputtering process using their respective target materials. As another example, the metal nanoparticles (MP) may be formed in an island shape on the lower conductive film (112) using a sputtering process, and the MIT material layer (ML) may be formed on the lower conductive film (112) on which the metal nanoparticles (MP) are formed using sputtering, pulsed laser deposition (PLD), thermal evaporation, electron-beam evaporation, or molecular beam epitaxy (MBE).

Referring to FIGS. 8a and 8b, a heat treatment process can be performed on a substrate (100) on which an MIT selection element film (120) is formed.

The MIT material layer (ML) may be crystallized by the heat treatment process, and the forming voltage for the threshold switching operation of the selection element may be lowered according to the crystallization of the MIT material layer (ML). For example, the heat treatment process may be performed in a vacuum and nitrogen (N2) atmosphere within a temperature range of 500 to 700°C for a predetermined period of time using a rapid thermal process (RTP). When the temperature of the heat treatment is 500°C or lower, crystallization of the MIT material layer (ML) may not occur, and when the temperature of the heat treatment is 700°C or higher, a stabilized crystal phase may be changed into another crystal phase or destroyed, so that the metal-insulator transition characteristics may deteriorate or the threshold switching operation may not occur.

Referring to FIGS. 9a and 9b, a lower electrode film (130), a variable resistance film (140), and an upper electrode film (150) can be sequentially formed on an MIT selection element film (121) on which a heat treatment process has been performed.

Each of the lower electrode film (130) and the upper electrode film (150) may be formed of a metal nitride or a metal silicon nitride, such as titanium nitride (TiNx), titanium silicon nitride (TiSiNx), tungsten nitride (WNx), tungsten silicon nitride (WSiNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), zirconium nitride (ZrNx), zirconium silicon nitride (ZrSiNx), etc.

In one embodiment, the variable resistance film (140) may be formed of a material whose electrical resistance changes by oxygen vacancy or oxygen movement, and thus the variable resistance memory device may be a resistive random access memory (ReRAM) device. For example, the variable resistance film (140) may be formed of a perovskite series material or a transition metal oxide. Examples of the perovskite series material include STO (SrTiO3), BTO (BaTiO3), PCMO (Pr1-XCaXMnO3), and the like. Examples of the above transition metal oxides include titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), niobium oxide (NbOx), cobalt oxide (CoOx), tungsten oxide (WOx), lanthanum oxide (LaOx), zinc oxide (ZnOx), etc. These may be used alone or in combination of two or more.

In another embodiment, the variable resistance film (140) may be formed of a material whose resistance changes according to a phase change, and thus the variable resistance memory device may be a phase change random access memory (PRAM) device. For example, the variable resistance pattern (144) may include a chalcogenide series material in which germanium (Ge), antimony (Sb), and/or tellurium (Te) are combined in a predetermined ratio.

Referring to FIGS. 10A and 10B, the upper electrode film (150), the variable resistance film (140), the lower electrode film (130), the MIT selection element film (121), the lower conductive film (112), and the barrier film (102) may be patterned to form a first trench (T1) extending in the first direction (D1). The patterning may include forming a mask pattern (not shown) on the upper electrode film (150) and performing an anisotropic etching process.

As a result of the above patterning, preliminary cell structures including a preliminary upper electrode pattern (152), a preliminary variable resistance pattern (142), a preliminary lower electrode pattern (132), a preliminary MIT selection element pattern (122), a lower conductive film pattern (114), and a barrier film pattern (104) can be formed on both sides of the first trench (T1). The preliminary cell structures can have a line shape extending in the first direction (D1). The barrier film pattern (104) and the lower conductive film pattern (114) of the preliminary cell structures can correspond to the first conductive line (115).

Next, a preliminary first mold pattern (160) filling the first trench (T1) may be formed. The preliminary first mold pattern (160) may be formed by forming a first mold film filling the first trench (T1) and covering an upper surface of the preliminary cell structure, and then performing a planarization process to expose an upper surface of the preliminary cell structure. The first mold film may be formed of silicon oxide and/or silicon nitride. The planarization process may include, for example, a chemical mechanical polish (CMP) process.

Referring to FIGS. 11A and 11B, a preliminary upper electrode pattern (152), a preliminary variable resistance pattern (142), a preliminary lower electrode pattern (132), a preliminary MIT selection element pattern (122), and a preliminary first mold pattern (160) may be patterned to form a second trench (T2) extending in a second direction (D2). The patterning may include forming a mask pattern (not shown) on the preliminary upper electrode pattern (152) and the preliminary first mold pattern (160), and performing an anisotropic etching process. As a result of the patterning, cell structures including the MIT selection element (124), the lower electrode (134), the variable resistance pattern (144), and the upper electrode (154) may be formed on the first conductive line (115). The cell structures may be spaced apart from each other along the first direction (D1) and the second direction (D2) to form rows and columns. And, island-shaped first mold patterns (162) may be formed between the outer walls of the cell structures in the second direction (D2). Meanwhile, the remainder of the preliminary first mold pattern (160) may remain between the first mold patterns (162) in the first direction (D1) and between the first conductive lines (115) in the second direction (D2).

Referring again to FIGS. 3A and 3B , a second mold pattern (170) may be formed within the second trench (T2). The second mold pattern (170) may be formed by forming a second mold film that fills the second trench (T2) and covers an upper surface of the cell structure, and then performing a planarization process to expose the upper surface of the cell structure. The second mold film may be formed of silicon oxide and/or silicon nitride. The second mold pattern (170) may have a line shape extending in the second direction (D2).

Next, a second conductive line (190) may be formed that is commonly connected to the upper electrodes (154) spaced apart along the second direction (D2). The second conductive line (190) may be formed by forming an upper conductive film on a substrate (100) on which a second mold pattern (170) is formed and then patterning the same. The upper conductive film may include, for example, a metal such as tungsten (W), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a metal nitride thereof.

By performing the above-described processes, a variable resistance memory device having an MIT selection element (124) including dispersed metal nanoparticles (MP) can be completed.

According to embodiments of the present invention, since the MIT selection element (124) is implemented to include an MIT material layer (ML) having metal-insulator transition characteristics and metal nanoparticles (MP) dispersed within the MIT material layer (ML), it is possible to operate so that the same amount of current can flow even with a smaller voltage, and the memory effect capable of remembering a previous operation can be maintained for a longer period of time than before, so that the switching characteristics can be further improved.

In addition, the MIT selection element (124) implemented in this manner has the effect of minimizing the voltage drop of the switching element and reducing the threshold voltage value of the element, thereby suppressing the occurrence of sneak current.

Furthermore, since the MIT selection element (124) has a protrusion (124b) that is inserted into the lower conductive film pattern (114), the electrical characteristics can be improved due to a decrease in contact resistance resulting from an increase in the contact area.

As a result, it may be possible to provide a variable resistance memory device with improved switching characteristics and electrical characteristics.

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments and application examples described above are exemplary in all respects and are not limiting.

Claims (3)

First challenge lines extending in the first direction;
Second challenge lines extending in a second direction intersecting the first direction; and
Including memory cells provided at each intersection between the first challenge lines and the second challenge lines,
Each of the above memory cells includes an MIT selection element and a variable resistor connected in series between corresponding first and second conductive lines,
The above MIT selection element comprises an MIT material layer formed of a material having metal-insulator transition properties and metal nanoparticles dispersed within the MIT material layer,
The above MIT material layer comprises vanadium oxide including VO, VO ₂ , V ₂ O ₃ , or V ₂ O ₅ ,
The above metal nanoparticles are a variable resistance memory element containing platinum (Pt). In the first paragraph,
The above first challenge line includes a barrier film pattern and a lower challenge film pattern sequentially laminated on a substrate,
The above variable resistor comprises a lower electrode, a variable resistor pattern and an upper electrode sequentially stacked on the MIT selection element,
The above MIT selection element is a variable resistance memory element including a body portion whose upper and lower surfaces are in contact with the lower electrode and the lower conductive film pattern, respectively, and a protrusion portion that protrudes from the lower surface of the body portion and is inserted into the lower conductive film pattern. In the second paragraph,
A variable resistance memory element in which the above MIT material layer is a single-crystalline or polycrystalline film.