KR102567815B1 - Liquid crystal display apparatus - Google Patents

Abstract

According to this embodiment, a first pixel receives a gate signal from a first gate line and a data voltage corresponding to a data signal through a first data line, and a gate signal from a second gate line adjacent to the first gate line. and a second pixel receiving a data voltage corresponding to a data signal through a second data line adjacent to the first data line, wherein the first common electrode line receiving common power is connected to the first gate line and the second pixel. Provided is a liquid crystal display device disposed between gate lines and connected to a common electrode disposed to overlap an upper portion of at least one data line among an upper portion of a first data line and an upper portion of a second data line connected to a first common electrode line. can do.
According to the present embodiments, it is possible to provide a liquid crystal display device having an improved aperture ratio and easy to drive high resolution/high frequency.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY APPARATUS}

This embodiment relates to a liquid crystal display device.

A liquid crystal display (LCD) is one of the flat panel display devices that display images using liquid crystals, and is widely used throughout the industry due to its thin, light, and low power consumption advantages. The liquid crystal display device may display an image by selectively transmitting light emitted from a backlight unit for displaying an image by changing an arrangement of liquid crystals.

In such a liquid crystal display device, a plurality of pixels are arranged in a matrix form corresponding to an area where a data line and a gate line intersect, and each pixel includes a circuit unit for transmitting a signal applied to the liquid crystal in response to a data signal. The circuit unit may change the arrangement of liquid crystals according to a voltage applied in response to a data signal for each pixel.

However, the data line, the gate line, and the circuit portion are made of metal and do not transmit light. If the area of the region where light is not transmitted is large, the aperture ratio of the liquid crystal display device may decrease, and luminance may be reduced. In order to overcome the decrease in luminance, the backlight unit can emit light with high luminance, but a problem in that power consumption of the liquid crystal display device increases. Therefore, there is a need for a method to increase luminance without increasing power consumption by increasing the aperture ratio.

In addition, recently, a display device having a high resolution and driven at a high frequency is in the limelight. Therefore, there is a need for a liquid crystal display device capable of driving high resolution/high frequency. In addition, crosstalk may occur between the data line and the common electrode line of the liquid crystal display device, resulting in deterioration of image quality.

An object of the present embodiments is to provide a liquid crystal display device having an improved aperture ratio.

Another object of the present embodiments is to provide a liquid crystal display that is easy to drive with high resolution/high frequency.

Another object of the present embodiments is to provide a liquid crystal display capable of suppressing the occurrence of crosstalk.

In one aspect, in the present embodiments, a first pixel receiving a gate signal from a first gate line and receiving a data voltage corresponding to the data signal through the first data line, and a second gate line adjacent to the first gate line A second pixel receiving a gate signal from and receiving a data voltage corresponding to the data signal through a second data line adjacent to the first data line, wherein the first common electrode line supplied with common power is connected to the first gate A common electrode disposed between the line and the second gate line and overlapping the upper portion of at least one of the upper portion of the first data line and the upper portion of the second data line is connected to the first common electrode line. A liquid crystal display device can be provided.

In another aspect, the present embodiments provide a display panel including a plurality of pixels in which a plurality of data lines and a plurality of gate lines intersect, a data driver for applying a data signal to the display panel, and a gate signal to the display panel. It is possible to provide a liquid crystal display device including a gate driver to supply, wherein each of a plurality of pixels includes a light emitting region and a circuit region, and a first pixel and a second pixel among the plurality of pixels share a circuit region.

According to the present embodiments, a liquid crystal display device having an improved aperture ratio can be provided.

In addition, according to the present embodiments, it is possible to provide a liquid crystal display that is easy to drive with high resolution/high frequency.

In addition, according to the present embodiments, it is possible to provide a liquid crystal display device capable of suppressing the occurrence of crosstalk.

1 is a structural diagram showing an example of a liquid crystal display device according to the present embodiment.
FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a pixel employed in the display panel shown in FIG. 1 .
FIG. 3 is a plan view illustrating a first embodiment of a pixel employed in the display panel shown in FIG. 1 .
FIG. 4 is a plan view illustrating a second embodiment of a pixel employed in the display panel shown in FIG. 1 .
FIG. 5A is an enlarged plan view of the circuit area shown in FIG. 4 .
FIG. 5B is an enlarged plan view of a portion where the third common electrode line shown in FIG. 4 is disposed.
FIG. 6 is a cross-sectional view showing one embodiment of the cross-section lined Ⅰ-I′ shown in FIG. 4 .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. However, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 is a structural diagram showing an example of a liquid crystal display device according to the present embodiment.

Referring to FIG. 1 , a liquid crystal display device 100 may include a display panel 101 , a gate driver 120 , and a data driver 130 .

The display panel 101 includes a plurality of gate lines (G1, G2, ..., Gn-1, Gn) and a plurality of data lines (D1, D2, ..., Dm-1, Dm) in an area defined by crossing. A pixel 110 may be formed. A voltage corresponding to a data signal may be supplied to each of the data lines D1, D2, ..., Dm-1, and Dm, and a gate signal may be sequentially supplied to each gate line. In addition, the plurality of pixels 110 receiving gate signals from the gate lines G1, G2, ..., Gn-1, Gn receive data signals from the data lines D1, D2, ..., Dm-1, Dm, respectively. A corresponding data voltage may be received. Among the plurality of pixels 110, the first pixel 110a and the second pixel 1101b may be arranged in the same column, and the first pixel 110a has a data voltage corresponding to the data signal from the first data line D1. , and the second pixel 110b can receive the data voltage corresponding to the data signal from the second data line D2. Also, a first gate line G1 and a second gate line G2 may be disposed between the first pixel 110a and the second pixel 1101b.

The gate driver 120 is connected to the plurality of gate lines (G1, G2, ..., Gn-1, Gn) of the display panel 101, and sequentially transmits gate signals to the plurality of gate lines (G1, G2, ..., Gn). -1, Gn) can be supplied. Sequential transmission of the gate signal may mean that the gate signal is transmitted to the next adjacent gate lines (G1, G2, ..., Gn-1, Gn) after the gate signal is transmitted to one gate line. Here, the gate driver 120 is shown as a component separate from the display panel 110, but is not limited thereto, and the gate driver 120 may be formed in a non-display area (not shown) of the display panel 110. can The gate driver 120 may have a Gate In Panel (GIP) circuit disposed in a non-display area of the display panel 110 .

The data driver 130 is connected to the plurality of data lines D1, D2, ..., Dm-1, Dm of the display panel 110, and transmits data voltages corresponding to data signals to the plurality of data lines D1, D2, ... , Dm-1, Dm) can be supplied. The data driver 130 may output data signals in parallel. Here, the data driver 130 is illustrated as a single component, but is not limited thereto and may include a plurality of components corresponding to the resolution of the display panel 110 .

In addition, the liquid crystal display device 100 may further include a controller 140 . The control unit 140 transmits a clock signal, a gate driver control signal, a data driver control signal, and an image signal to the gate driver 120 and/or the data driver 130 to drive the display panel 110 to display an image. can do.

FIG. 2 is a circuit diagram illustrating an exemplary embodiment of a pixel employed in the display panel shown in FIG. 1 .

Referring to FIG. 2 , in the display panel 210 , the first common power line Vcoma may be disposed between the first gate line Sj and the second gate line Sj+1. Further, the first pixel 201a is disposed between the first gate line Sj and the first common electrode line Vcoma, and the second pixel 201b has the first common power line Vcoma and the second gate line ( Sj+1). The first gate line Sj and the second gate line Sj+1 sequentially receive gate signals, and the first common power line Vcoma supplies common power to the first pixel 201a and the second pixel 201b. can supply Further, the first pixel 201a receives a voltage corresponding to the data signal through the first data line Dk, and the second pixel 201b receives a voltage corresponding to the data signal through the second data line Dk+1. voltage can be transmitted.

Also, the first pixel 201a may be further connected to the second common power line Vcomb1 and the second pixel 201b may be further connected to the third common power line Vcomb2. The first common power line Vcoma shared by the first pixel 201a and the second pixel 201b becomes one electrode of the storage capacitors Cst1 and Cst2 to store the voltage of the data signal corresponding to the data signal. . In addition, in the first pixel 201a, the second common power line Vcomb1 is connected to the liquid crystal cell LC1 corresponding to the first pixel 201a, and the second pixel 201b has a third common power line Vcomb2. It is connected to the liquid crystal cell LC2 corresponding to the second pixel 201b to supply a common power to each of the liquid crystal cells LC1 and LC2.

Due to the above connection, the first pixel 201a and the second pixel 201b can share the first common power line Vcom1. Therefore, the area occupied by the first common power line Vcoma in the display panel 210 is reduced compared to the case where the first common power line Vcom1 is connected to the first pixel 201a and the second pixel 201b, respectively. Therefore, the aperture ratio of the display panel 210 can be increased. In addition, since the aperture ratio of the display panel 210 is increased by sharing the first common power line Vcoma, a separate additional process for improving the aperture ratio is not required, thereby reducing the manufacturing cost of the display device. In addition, since the storage capacitors Cst1 and Cst2 are connected in series, charging and discharging of the data voltage corresponding to the data signal can proceed quickly, so that the display panel can be easily driven at a high frequency.

In addition, the first pixel 201a receives a data voltage corresponding to a data signal transmitted through the first data line Dk in response to a gate signal transmitted through the first gate line Sj, and receives a data voltage corresponding to the data signal transmitted through the second pixel (Sj). 201b) may receive a data voltage corresponding to a data signal transmitted through the second data line Dk+1 in response to a gate signal transmitted through the second gate line Sj+1.

FIG. 3 is a plan view illustrating a first embodiment of a pixel employed in the display panel shown in FIG. 1 .

Referring to FIG. 3 , the display panel 301 may include a first pixel 310a and a second pixel 310b. The first data line Dk is disposed to the left of the first pixel 310a and the second pixel 310b, and the second data line Dk+1 is disposed between the first pixel 310a and the second pixel 310b. can be placed on the right. The first data line Dk supplies a data voltage corresponding to the data signal to the pixel column including the first pixel 310a and the second pixel 310b, and the second data line Dk+1 supplies the next pixel column ( (not shown) may be supplied with a data voltage corresponding to the data signal. In addition, in the first pixel 310a, the light emitting region 311a may be disposed on the upper side and the circuit region 340a driving the light emitting region 311a may be disposed on the lower side. In the second pixel 310b, the light emitting region 311a may be disposed on the upper part and the circuit region 340b driving the light emitting region 311b may be disposed on the lower part.

Pixel electrodes 313a and 313b and common electrodes 312a and 312b may be disposed in the emission regions 311a and 311b of the first pixel 310a and the second pixel 310b, respectively. The pixel electrodes 313a and 313b and the common electrodes 312a and 312b may be arranged at regular intervals on the same layer within the light emitting regions 311a and 311b and correspond to the voltage applied to the pixel electrodes 313a and 313b. Thus, voltages applied to the liquid crystal cells 330 respectively corresponding to the first pixel 3 (10a) and the second pixel 310b may be determined. In addition, in the circuit region 340a of the first pixel 310a, a first gate line Sj and a common electrode line Vcom crossing the first data line Dk and the second data line Dk+1, respectively, are provided. is disposed, and in the circuit area 340b of the second pixel 310b, the second gate line Sj+1 intersecting the first data line Dk and the second data line Dk+1 and the common electrode line ( Vcom) can be placed. In addition, a switching transistor turned on in response to a gate signal transmitted to the gate lines Sj and Sj+1 and a storage capacitor holding the data voltage are disposed in the circuit regions 312a and 312b of the pixels 310a and 310b, respectively. It can be.

Accordingly, the first pixel 310a and the second pixel 310b may include light emitting regions 311a and 311b and circuit regions 312a and 312b corresponding to the light emitting regions 311a and 311b, respectively. Also, a common electrode 320 may be disposed above the first data line Dk and the second data line Dk+1. The data lines Dk and Dk+1 may be shielded by the common electrode 320 .

FIG. 4 is a plan view illustrating a second embodiment of a pixel employed in the display panel shown in FIG. 1 .

Referring to FIG. 4 , the display panel 401 may include a first pixel 410a and a second pixel 410b. The first data line Dk may be disposed on the left side of the first pixel 410a and the second pixel 410b, and the second data line may be disposed on the right side of the first pixel 410a and the second pixel 410b. there is. The first data line Dk supplies the data voltage corresponding to the data signal to the first pixel 410a, and the second data line Dk+1 supplies the data voltage corresponding to the data signal to the second pixel 410b. can supply In addition, the circuit area 440 may be disposed between the light emitting area of the first pixel 410a and the light emitting areas 411a and 411b of the second pixel 410b. Also, the first pixel 410a and the second pixel 410b may share the circuit area 440 . By sharing circuit areas, the number and area of circuit areas disposed on the display panel 101 can be reduced, and the aperture ratio of the display panel 101 can be increased by reducing the number and area of circuit areas.

Pixel electrodes 413a and 413b and common electrodes 412a and 412b may be disposed in the emission regions 411a and 411b of the first pixel 410a and the second pixel 410b, respectively. The pixel electrodes 413a and 413b and the common electrodes 412a and 412b may be disposed at regular intervals on the same layer within the light emitting region, and in response to the voltage applied to the pixel electrodes 413a and 413b, the first pixel ( Voltages applied to liquid crystal cells respectively corresponding to 410a) and the second pixel 410b may be determined. In addition, a first gate line Sj corresponding to the first pixel 410a is provided in the circuit region 440 disposed between the light emitting regions 411a and 411b of the first pixel 410a and the second pixel 410b. and the second gate line Sj+1 corresponding to the second pixel 410b and the first common electrode line Vcoma cross the first data line Dk and the second data line Dk+1, respectively. can be placed. Also, the first common electrode line Vcoma may be disposed between the first gate line Sj and the second gate line Sj+1.

In the first pixel 410a, the second common electrode line Vcomb1 is connected to the upper portion of the light emitting region 411a, and in the second pixel 410b, the third common electrode line Vcomb2 is connected to the lower portion of the light emitting region 411b. ) can be further connected. The second common electrode line Vcomb2 may be connected to the common electrode 412a in the light emitting region 411a of the first pixel 410a, and the third common electrode line Vcomb2 may be connected to the light emitting region of the second pixel 410b ( 411b) may be connected to the common electrode 412b.

In addition, the circuit area 440 is an area in which no light is emitted. As shown in FIG. 3 , if the circuit areas 340a and 340b have the same width, they may not be recognized by the eyes. However, the circuit area 440, the second common electrode line Vcomb1, and the third common electrode line Vcomb2 shown in FIG. 4 are also areas in which no light is emitted, and if the thicknesses are different, they can be recognized by the eyes. However, if the difference between the width (B) of the circuit region 440 and the width (C) of the second common electrode line Vcomb1 or the third common electrode line Vcomb2 is very large, it may not be recognized by eyes. When the width (C) of the second common electrode line (Vcomb1) or the third common electrode line (Vcomb2) has a thickness at least 1/8 times the width (B) of the circuit area 440, the difference is very large and noticeable. may not be recognized. Further, the width B of the circuit area 440 and the width C of the third common electrode line Vcomb2 are the distance between the first pixel 410a and the second pixel 410b and the second pixel ( 410b) and a third pixel (not shown). The distance between the second pixel 410b and the third pixel may be about 1/8 times thinner than the distance between the first pixel 410a and the second pixel 410b. The third pixel may be a pixel disposed under the second pixel 410b, and a gate signal generated after a gate signal transmitted to the second gate line Sj+1 through a third gate line (not shown) It is possible to receive the data voltage corresponding to the data signal. Also, preferably, the distance between the second pixel 410b and the third pixel may be 1/10 times smaller than the distance between the first pixel 410a and the second pixel 410b.

Unlike the two pixels 310a and 310b shown in FIG. 3 , the two pixels shown in FIG. 4 share one first common electrode line Vcoma disposed in one circuit area. Also, unlike the two pixels shown in FIG. 3 , the two pixels 410a and 410b shown in FIG. 4 have a first gate line Sj and a second gate line Sj+ in one circuit area 440 . 1) is placed. Therefore, the width B of the circuit area 440 shown in FIG. 4 may be implemented thinner than the sum 2A of the widths of the respective circuit areas 340a and 340b shown in FIG. 3 .

In addition, although the first pixel 410a and the second pixel 410b shown in FIG. 4 further require a second common electrode line Vcomb1 or a third common electrode line Vcomb2, respectively, the second common electrode By reducing the thickness of the line Vcomb1 or the third common electrode line Vcomb2, the width B of the circuit area 440 shown in FIG. 4 and the second common electrode line Vcomb1 or the third common electrode line ( The sum (B+2C) of the widths (C) of Vcomb2 may be implemented thinner than the sum (2A) of the widths of the circuit regions 340a and 340b shown in FIG. 3 . Accordingly, the aperture ratio of the display panel 401 can be increased.

Also, a common electrode 420 may be disposed above the first data line Dk and the second data line Dk+1. The data lines Dk and Dk+1 may be shielded by the common electrode 420 . The common electrode 420 shielding the data lines Dk and Dk+1 receives common power from the first common electrode line Vcoma shared by the first pixel 410a and the second pixel 410b, and The cell may receive common power from the second common electrode line Vcomb1 or the third common electrode line Vcomb2. That is, since the liquid crystal cell receives common power from the second common electrode line Vcomb1 or the third common electrode line Vcomb2 separated from the first common electrode line Vcoma, the data lines Dk and DK+1 are connected. It is possible to suppress the occurrence of crosstalk between the data voltage transmitted through and the common power supply.

FIG. 5A is an enlarged plan view of the circuit area shown in FIG. 4 .

Referring to FIG. 5A , the first gate line Sj and the second gate line are disposed at regular intervals, and the first common electrode line Vcoma is disposed between the first gate line Sj and the second gate line. It can be.

A source electrode 415a and a drain electrode 414a connected to the first data line Dk may be disposed above the first gate line Sj. A switching transistor for applying a data signal to the first pixel 410a may be formed by the source electrode 415a, the drain electrode 414a, and the first gate line Sj. In addition, the source electrode 415a and the drain electrode 414a may respectively cross the first gate line Sj. That is, the source electrode 415a contacts the first contact hole Ch1a on the first gate line Sj and intersects the first gate line Sj, and the drain electrode 414a has the first contact hole Ch1a It may extend in the pixel direction from and intersect the first gate line Sj.

In addition, a source electrode 415b and a drain electrode 414b connected to the second data line Dk+1 may be disposed on the second gate line Sj+1. A switching transistor for applying a data signal to the second pixel 410b may be formed by the source electrode 415b, the drain electrode 414b, and the second gate line Sj+1. In addition, the source electrode 415b and the drain electrode 414b may respectively cross the second gate line Sj+1. That is, the source electrode 415b contacts the second contact hole Ch1b on the second gate line Sj+1 and intersects the second gate line Sj+1, and the drain electrode 414b contacts the second contact hole Ch1b. It may extend from the hole ch1b in the pixel direction and intersect the second gate line Sj+1.

In this way, the source electrodes 415a and 415b and the drain electrodes 414a and 414b cross the first gate line Sj and the second gate line Sj+1, respectively, thereby forming the source electrodes 415a and 415b and the drain electrodes 415a and 415b. Since the electrodes 414a and 414b do not intersect with other gate lines other than the corresponding gate lines, distortion of the gate signal may not occur.

Also, the first common electrode line Vcoma may be connected to the common electrode 420 formed on the first data line Dk and the second data line Dk through the third contact hole Ch2. . In addition, the first contact hole Ch1a and the second contact hole Ch1b may be connected to the first common electrode line Vcoma, so that the pixel electrodes 413a and 413b may be connected to the first common electrode line Vcoma. . Therefore, the first common electrode line Vcoma can be the second electrode of the storage capacitor, so that the storage capacitors of the first pixel 410a and the second pixel 410b are connected in series as shown in FIG. The charging and discharging time can be reduced. Thus, high-speed driving can be easily performed.

FIG. 5B is an enlarged plan view of a portion where the third common electrode line shown in FIG. 4 is disposed.

Referring to FIG. 5B, the third common electrode line Vcomb2 is connected to the common electrode line 412b for applying common power to the liquid crystal 430 through the fourth contact hole ch3b to apply power in a lateral electric field method. can

FIG. 6 is a cross-sectional view showing one embodiment of the cross-section lined Ⅰ-I′ shown in FIG. 4 .

Referring to FIG. 6 , a common electrode Vcom may be disposed on the substrate 600 . When the common electrode Vcom is disposed, the gate lines Sj and Sj+1 of FIG. 2 and the first common electrode line Vcom may be disposed. And, a first insulating layer 601 may be disposed on the upper portion. Data lines Dk and Dk+1 may be disposed on the first insulating layer 601 . And, a second insulating layer 602 may be disposed on the upper portion. Also, a common electrode line 412a and a pixel electrode line 412a may be disposed on the second insulating layer 602 . That is, the common electrode line 412a and the pixel electrode line 412a may be arranged in a horizontal direction. In addition, a common electrode 420 may be disposed on the second insulating layer 602 to shield the data lines Dk and Dk+1. In this case, since the common electrode 420 and the common electrode line 412a are not electrically connected, generation of crosstalk between the common electrode line 412a and the data lines Dk and Dk+1 can be suppressed.

The above description and accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the scope not departing from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: liquid crystal display
101: display panel
110: pixel
120: data driver
130: gate driver
140: control unit

Claims (10)

a first pixel having a first pixel electrode receiving a gate signal from a first gate line and a data voltage corresponding to the data signal through a first data line;
A second pixel having a second pixel electrode receiving a gate signal from a second gate line adjacent to the first gate line and receiving a data voltage corresponding to the data signal through a second data line adjacent to the first data line. ;
a first common electrode line disposed between the first gate line and the second gate line and supplied with a common power supply; and
It is disposed on the layer where the first pixel electrode and the second pixel electrode are disposed, is disposed in the same direction as the direction in which the first data line and the second data line are disposed, and is disposed on the first common electrode line. A liquid crystal display device comprising a common electrode disposed to overlap an upper portion of at least one data line among an upper portion of one data line and an upper portion of the second data line.
According to claim 1,
The first pixel is further connected to a second common electrode line separated from the first common electrode line, and the second pixel is further connected to a third common electrode line separated from the first common electrode line. . According to claim 1,
The first pixel includes a switching transistor that performs a switching operation in response to a gate signal transmitted through the first gate line, and a source electrode and a drain electrode of the switching transistor intersect the first gate line, respectively. Device. According to claim 1,
a third pixel receiving a gate signal from a third gate line adjacent to the second gate line and receiving a data voltage corresponding to the data signal through the first data line;
A distance between the second pixel and the third pixel is smaller than 1/8 times a distance between the first pixel and the second pixel.
According to claim 1,
The first common electrode line is a first electrode of a storage capacitor. a display panel including a plurality of pixels in which a plurality of data lines and a plurality of gate lines intersect;
a data driver for applying a data signal to the display panel; and
A gate driver supplying a gate signal to the display panel,
Each of the plurality of pixels includes a light emitting area and a circuit area, and among the plurality of pixels, a first pixel on which a first pixel electrode is disposed and a second pixel on which a second pixel electrode is disposed share the circuit area;
A first common electrode line receiving a common power is disposed in the circuit area,
It is disposed on a layer where the first pixel electrode and the second pixel electrode are disposed, is disposed in the same direction as the direction in which the first data line and the second data line are disposed, and the first data line is disposed on the first common electrode line. A liquid crystal display device comprising a common electrode disposed to overlap an upper portion of at least one data line among an upper portion of the data line and an upper portion of the second data line.
According to claim 6,
The circuit area includes a first gate line supplying a gate signal to the first pixel;
a second gate line supplying a gate signal to the second pixel;
a first common electrode line disposed between the first gate line and the second gate line to supply common power to the first pixel and the second pixel;
A first transistor for transferring a data voltage corresponding to a data signal transmitted to the first data line in response to the gate signal to the first pixel, and a data voltage corresponding to the data signal transmitted to the second data line in response to the gate signal. A liquid crystal display device comprising a second transistor for transmitting a voltage to the second pixel. According to claim 7,
a third pixel receiving a gate signal from a third gate line adjacent to the second gate line and receiving a data voltage corresponding to the data signal through the first data line;
A distance between the second pixel and the third pixel is smaller than 1/8 times a distance between the first pixel and the second pixel.
According to claim 7,
A liquid crystal display device in which a common electrode disposed to overlap an upper portion of at least one of an upper portion of the first data line and an upper portion of the second data line is connected to the first common electrode line. According to claim 7,
At least one of the first transistor and the second transistor has a source electrode and a drain electrode crossing the first gate line or the second gate line, respectively.

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