KR102412111B1 - Display device - Google Patents

Abstract

A display device capable of preventing luminance unevenness from occurring in a display panel according to a delay of a gate signal is provided. The display device includes a gate driver and a compensator that generates compensation image data that is increased in proportion to a distance between each pixel of the display panel or compensation image data that is decreased in inverse proportion.

Description

Display device

The present invention relates to a display device, and more particularly, to a display device capable of preventing luminance non-uniformity in each pixel of a display panel due to a delay of a gate signal.

In a liquid crystal display (LCD), a liquid crystal layer having an anisotropic dielectric constant is formed between two insulating substrates that are opposed to each other, and the arrangement direction of liquid crystal molecules is varied according to the magnitude of an electric field formed in the liquid crystal layer. The image is displayed by adjusting the light transmittance. Such a liquid crystal display device includes a liquid crystal panel on which an image is displayed and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, regions are divided by a plurality of gate lines and data lines crossing each other, and a plurality of pixels are arranged in a matrix form. Then, when a gate signal is sequentially applied to a plurality of gate lines of the liquid crystal panel, one image frame is displayed on the liquid crystal panel while the data signal is applied to each data line in response to the gate signal.

1 is a diagram schematically showing the configuration of a conventional liquid crystal display device, and FIG. 2 is a diagram showing a waveform of a gate signal according to an operation of the liquid crystal display device.

As shown in FIG. 1 , a plurality of data lines DL1 to DLm are disposed on the liquid crystal panel 10 to intersect the gate lines GL disposed in one direction to define a plurality of pixel areas.

In each pixel area, a liquid crystal capacitor (Clc) from which a data signal is supplied, a thin film transistor (TFT) for driving the liquid crystal capacitor (Clc), and a storage capacitor (Cst) for maintaining the voltage charged in the liquid crystal capacitor (Clc) for a certain period of time The pixels P1, P(m/2), Pm including ) are formed.

The thin film transistor TFT of each of the pixels P1, P(m/2), and Pm is switched in response to a gate signal applied to the gate line GL. The liquid crystal capacitor Clc charges the data signal applied through the data lines DL1 to DLm while the thin film transistor TFT is turned on. And, the storage capacitor Cst maintains the voltage charged in the liquid crystal capacitor Clc until the thin film transistor TFT is turned on again.

Recently, in order to increase the size of the display screen of the liquid crystal display, a liquid crystal display having a narrow bezel in which the width of the bezel of the liquid crystal display is reduced has been developed. Accordingly, a gate driving circuit for applying a gate signal to the plurality of gate lines GL of the liquid crystal panel 10 is disposed on one side of the display area of the liquid crystal panel 10 .

Accordingly, when the gate signal output from the gate driving circuit is transmitted from one side of the gate line GL of the liquid crystal panel 10 to the other side, a signal delay occurs. Due to the delay of the gate signal, a charging failure of the data signal occurs in each of the pixels P1, P(m/2), and Pm of the liquid crystal panel 10, and the delay of the gate signal causes the area of the liquid crystal panel 10 to decrease. The bigger it gets, the worse it gets.

1 and 2 , among the three pixels P1 , P(m/2), and Pm disposed in the display area of the liquid crystal panel 10 , the first pixel P1 closest to the gate driving circuit is In , there is almost no delay of the gate signal applied from the gate driving circuit through the gate line GL. Accordingly, since the turn-on time T1 of the thin film transistor TFT of the first pixel P1 is relatively long, the amount of charge of the data signal charged in the liquid crystal capacitor Clc is also relatively large.

However, in the liquid crystal panel 10 , the (m/2)th pixel P(m/2) and the mth pixel Pm disposed farther from the gate driving circuit than the first pixel P1 are the gate lines GL ), a signal delay occurs in the gate signal applied through the Accordingly, the (m/2)th pixel (P(m/2)) and the thin film transistor TFT of each of the mth pixel (Pm) are turned-on times T2 and T3 are the first pixel P1 is shorter than the turn-on time T1 of the thin film transistor TFT. Accordingly, the amount of charge of the data signal charged in the liquid crystal capacitor Clc of each of the (m/2)th pixel P(m/2) and the mth pixel Pm is also increased in the liquid crystal capacitor Clc of the first pixel P1. ) is smaller than the charge amount of the data signal charged in

That is, in the conventional liquid crystal display device in which one gate driving circuit is disposed on one side of the liquid crystal panel 10 , the distance between the gate driving circuit and the pixels P1 , P(m/2), Pm of the liquid crystal panel 10 . Accordingly, the amount of charge of the data signal charged in each of the pixels P1, P(m/2), and Pm varies.

This difference in the amount of charge for each pixel appears as a luminance non-uniformity in the liquid crystal panel 10, which deteriorates the display quality of an image in the liquid crystal display device.

An object of the present invention is to provide a display device capable of improving luminance non-uniformity by compensating for a difference in the amount of charge for each pixel of a display panel according to a delay of a gate signal.

In order to achieve the above object, a display device of the present invention includes a gate driver and a compensator that generates compensation image data that is increased in proportion to a distance between each pixel of a display panel or compensation image data that is decreased in inverse proportion.

The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels.

The gate driver generates a plurality of gate signals and outputs them to a plurality of gate lines of the display panel.

The compensator generates a plurality of compensation image data from a plurality of original image data corresponding to each of the plurality of data lines according to the stored delay compensation value. The compensation unit generates the compensation image data by adjusting the level of the remaining compensation image data based on one compensation image data among the plurality of compensation image data.

The data driver generates a data signal according to a plurality of compensation image data and outputs the data signal to a plurality of data lines of the display panel.

In the display device of the present invention, the level of the data signal generated by the data driver is changed according to the compensation image data proportionally increased according to the distance between the gate driver and each pixel of the display panel or the compensation image data decreased in inverse proportion to the distance between the gate driver and each pixel of the display panel. It is possible to prevent a defective charging of the data signal in the pixel according to the delay of the signal.

Accordingly, in the display device of the present invention, it is possible to improve the luminance unevenness of the display panel caused by the luminance level being lowered according to the distance between the gate driver and the pixel.

1 is a diagram schematically showing the configuration of a conventional liquid crystal display device.
2 is a diagram illustrating a signal delay of a gate signal according to an operation of a liquid crystal display device.
3 is a diagram illustrating a configuration of a display device according to an embodiment of the present invention.
FIG. 4 is a view showing the configuration of the compensator shown in FIG. 3 .
5, 6A, and 6B are diagrams illustrating an operation example of the compensator.
7 is a diagram illustrating a luminance level of a display device according to the present invention.

Hereinafter, a display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a configuration of a display device according to an embodiment of the present invention.

The display device 100 of the present embodiment may be a liquid crystal display device in which the display panel 110 is a liquid crystal panel, but is not limited thereto. The display device 100 may be a display device including various flat panel display panels, for example, an organic light emitting display device, an electrophoretic display device, a plasma display panel, or the like.

Referring to FIG. 3 , the display device 100 may include a display panel 110 and driving circuits for driving the same, for example, a timing controller 140 , a gate driver 120 , and a data driver 130 .

The display panel 110 may be a liquid crystal panel in which a liquid crystal layer (not shown) is interposed between two substrates (not shown). In the display panel 110 , a pixel region may be defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm formed to cross each other. A pixel P including a thin film transistor T, a liquid crystal capacitor Clc, and a storage capacitor Cst may be formed in each pixel area.

The display panel 110 may display an image in each pixel P according to a gate signal applied through the plurality of gate lines GL1 to GLn and a data signal applied through the plurality of data lines DL1 to DLm. have. The gate signal may have a pulse shape in which a gate high voltage supplied during one horizontal period 1H of the display panel 110 and a gate low voltage supplied during the remaining period of the display panel 110 are alternated.

When a gate high voltage is applied through the plurality of gate lines GL1 to GLn, the thin film transistor T of each pixel P of the display panel 110 is turned on to connect the plurality of data lines DL1 to DLm. The data signal applied through the is supplied to the liquid crystal capacitor Clc. Then, the thin film transistor T is turned off when the gate low voltage is applied through the plurality of gate lines GL1 to GLn, and thus the voltage charged in the liquid crystal capacitor Clc may be maintained for a predetermined time.

The gate driver 120 may generate a gate signal according to the gate control signal GCS applied from the timing controller 140 . The gate driver 120 may sequentially output the generated gate signal to the plurality of gate lines GL1 to GLn of the display panel 110 .

The gate driver 120 may be disposed on only one side of the display panel 110 to implement the narrow bezel of the display device 100 . The gate driver 120 is configured in the form of a Chip On Film (COF) and attached to one side of the display panel 110 , or is configured in the form of a Gate In Panel (GIP) to form one side of the display panel 110 . It can be configured internally.

The data driver 130 samples image data, for example, compensation image data RGB′ output from the compensator 150 to be described later, according to the data control signal DCS applied from the timing controller 140 , and latches the parallel data can be converted to The data driver 130 may generate an analog data signal from the converted parallel data using a plurality of positive/negative gamma reference voltages provided from the gamma reference voltage generator (not shown). The data signal may be output to the plurality of data lines DL1 to DLm of the display panel 110 .

The data driver 130 may include a plurality of driving chips 130_a to 130_c. Each of the driving chips 130_a to 130_c may be connected to a predetermined number of data lines among the plurality of data lines DL1 to DLm.

For example, the data driver 130 may include a first driving chip 130_a , a second driving chip 130_b , and a third driving chip 130_c . The first driving chip 130_a is disposed adjacent to the gate driving unit 120 , and may be connected to a predetermined number of data lines including the first data line DL1 among the plurality of data lines DL1 to DLm. The second driving chip 130_b is disposed to be spaced apart from the gate driver 120 compared to the first driving chip 130_a, and among the plurality of data lines DL1 to DLm, the (m/2)th data line DL(m) /2)) and may be connected to a predetermined number of data lines. The third driving chip 130_c is disposed to be spaced apart from the gate driving unit 120 compared to the first and second driving chips 130_a and 130_b, and an mth data line DLm among the plurality of data lines DL1 to DLm. may be connected to a predetermined number of data lines including Each of the driving chips 130_a to 130_c may generate a data signal from the compensation image data RGB′ output from the compensation unit 150 and output it to a corresponding data line.

The timing controller 140 controls the gate from timing signals such as a control signal CNT applied from an external system (not shown), for example, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE. A signal GCS and a data control signal DCS may be generated. The gate control signal GCS may be output to the gate driver 120 , and the data control signal DCS may be output to the data driver 130 .

The gate control signal GCS may include a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable signal GOE. In addition, the data control signal DCS includes a source clock pulse signal SCLK, a source start pulse signal SSP, a carry signal CR, a source output enable signal SOE, a scan direction control signal UP, and a bit inversion. It may include a control signal REV and a polarity inversion control signal POL.

The timing controller 140 generates image data, for example, initial image data, that can be processed by the plurality of driving chips 130_a to 130_c of the data driver 130 from the image signals R, G, and B applied from an external system. can do. In addition, the timing controller 140 may generate and output the compensation image data RGB' from the original image data in order to compensate for the signal delay of the gate signal.

To this end, the timing controller 140 may further include a compensator 150 . The compensating unit 150 compensates the initial image data according to the signal delay of the gate signal output from the gate driving unit 120 to generate compensation image data RGB', which is then generated by a plurality of driving chips ( 130_a~130_c) can be output to each.

In this way, the compensating unit 150 generates compensation image data RGB′ capable of compensating for the signal delay of the gate signal and outputs it to the data driving unit 130 , so that the data driving unit 130 displays the display panel 110 . The level of the data signal output to the plurality of data lines DL1 to DLm can be adjusted. Accordingly, in the display device 100 of the present embodiment, the data signal in each pixel P is delayed due to the signal delay of the gate signal generated according to the distance between the gate driver 120 and the pixel P of the display panel 110 . It is possible to improve the luminance unevenness of the display panel 110 by preventing a charging failure from occurring.

Hereinafter, the configuration and operation of the above-described compensation unit 150 will be described in detail with reference to the drawings.

FIG. 4 is a view showing the configuration of the compensator shown in FIG. 3 .

3 and 4 , the compensator 150 may include a memory 151 and a data modulator 155 .

A delay compensation value Δr for the pixel P of the display panel 110 may be stored in the memory 151 . The memory 151 may select and output a corresponding delay compensation value Δr according to image data input to the data modulator 155 , for example, the original image data RGB.

As described above, the compensator 150 generates compensation image data 150 capable of compensating for the delay of the gate signal, and outputs it to the data driver 130 . Accordingly, the delay compensation value Δr stored in the memory 151 may have a different value for each data line DL1 to DLm of the display panel 110 . For example, the delay compensation value Δr may be stored as the same value for the pixel P connected to one data line, but may be stored to have different values for the pixel P connected to different data lines. have.

In addition, the delay compensation value Δr may have different values depending on the horizontal separation distance between the gate driver 120 and each pixel P of the display panel 110 . For example, the delay compensation value Δr for the pixel P connected to the first data line DL1 closest to the gate driver 120 is the mth data line DLm most spaced apart from the gate driver 120 . It may be stored to have a relatively small size compared to the delay compensation value Δr for the pixel P connected to .

Accordingly, the memory 151 sets the delay compensation values Δ of different sizes for each of the plurality of data lines DL1 to DLm according to the distance between the gate driver 120 and each pixel P of the display panel 110 . r) may be stored in the form of one lookup table (LUT).

Also, the delay compensation value Δr may have different values depending on the operation time of the display panel 110 . For example, as the operation time of the display panel 110 increases, a characteristic change of the thin film transistor T occurs in each pixel P, which may increase the delay of the gate signal. Accordingly, the delay compensation value Δr may be stored to have a relatively large size as the operation time of the display panel 110 increases. In this case, the delay compensation value Δr may have different sizes for each of the plurality of data lines DL1 to DLm of the display panel 110 . Accordingly, the memory 151 has different sizes for each of the plurality of data lines DL1 to DLm of the display panel 110 , and the respective delay compensation values having different sizes for each operating time of the display panel 110 . It may be configured in the form of a plurality of lookup tables in which (Δr) is stored.

The delay compensation value Δr may be determined through luminance measurement of the display panel 110 and stored in the memory 151 . As shown in FIG. 5 , when the display panel 110 is operated by a data signal having a specific grayscale in the memory 151 , the luminance of the pixel P of the display panel 110 is measured at at least one point. The delay compensation value Δr determined through ?r may be stored.

In FIG. 5 , as an example, three points in the display panel 110 , that is, the first point A and the (m/2)th data line DL for the pixel P connected to the first data line DL1 . A luminance measurement is performed on each of the second point (B) for the pixel (P) connected to (m/2)) and the third point (C) for the pixel (P) connected to the m-th data line (DLm), , determining the delay compensation value (Δr) accordingly is illustrated, but is not limited thereto. For example, luminance measurement is performed on the pixels P connected to each of the data lines DL1 to DLm of the display panel 110 to determine the delay compensation value Δr or connected to the mth data line DLm The delay compensation value Δr may be determined by performing luminance measurement only on the pixel P.

3 and 4 again, the data modulator 155 generates compensation image data RGB' from the original image data RGB according to the delay compensation value Δr output from the memory 151. can The compensation image data RGB' may be output to each of the driving chips 130_a to 130_c of the data driver 130 together with the data control signal DCS.

The data modulator 155 may generate a data compensation value ΔV according to the following [Equation].

[Equation]

Here, RGB is the original image data, DLt is the target data line, and Δr is the delay compensation value.

Previously, in the memory 151 , for each data line DL1 to DLm of the display panel 110 , the delay compensation increases proportionally according to the separation distance between the gate driver 120 and each pixel P of the display panel 110 . It is stated that the value (Δr) is stored. Accordingly, the level of the data compensation value ΔV generated by the data modulator 155 may also be increased in proportion to the separation distance between the gate driver 120 and each pixel P of the display panel 110 . For example, the data compensation value ΔV corresponding to the pixel P at the third point C shown in FIG. 5 is the data compensation value ΔV corresponding to the pixel P at the first point A Alternatively, it may have a higher level than the data compensation value ΔV corresponding to the pixel P of the second point B.

The data modulator 155 may generate the compensation image data RGB' from the original image data RGB according to the data compensation value ΔV. The data modulator 155 may generate the compensation image data RGB' by adding or subtracting the data compensation value ΔV from the original image data RGB.

In this case, the data modulator 155 may generate the remaining compensation image data RGB' according to the data compensation value ΔV based on one compensation image data RGB'. Here, one compensation image data RGB' serving as a reference may have the same level as the corresponding original image data RGB, and the remaining compensation image data RGB' is each corresponding original image data RGB. It can be created to have a smaller level or a larger level.

For example, the data modulator 155 may be configured to use the second data compensation value ΔV based on the compensation image data RGB′ corresponding to the pixel P of the first point A shown in FIG. 5 . Compensation image data RGB' corresponding to each of the pixel P of the point B and the pixel P of the third point C may be generated at a level higher than that of the original image data RGB. At this time, the compensation image data RGB' corresponding to the pixel P of the third point C has a higher level than the compensation image data RGB' corresponding to the pixel P of the second point B. can have

In addition, the data modulator 155 controls the first point A according to the data compensation value ΔV based on the compensation image data RGB′ corresponding to the pixel P of the third point C. Compensation image data RGB' corresponding to each of the pixel P and the pixel P of the second point B may be generated at a reduced level than the original image data RGB. At this time, the compensation image data RGB' corresponding to the pixel P of the first point A has a smaller level than the compensation image data RGB' corresponding to the pixel P of the second point B. can have

As described above, the data modulator 155 generates a data compensation value ΔV according to the delay compensation value Δr stored in the memory 151, and uses it to have a higher level than the original image data RGB. The increased or decreased compensation image data RGB' may be generated and output. In addition, the data driver 130 is a data signal having different levels in each of the plurality of data lines DL1 to DLm of the display panel 110 according to the compensation image data RGB′ output from the data modulator 155 . can be printed out.

Accordingly, in the display device 110 of the present embodiment, even if the gate signal is delayed, the data driver 130 through the data lines DL1 to DLm by the compensation image data RGB′ output from the compensation unit 150 . By increasing or decreasing the level of the data signal output to the pixel P, it is possible to prevent a charging failure of the data signal in each pixel P of the display panel 110 from occurring, thereby improving luminance unevenness.

6A and 6B are diagrams illustrating an embodiment in which the compensation unit generates compensation image data.

First, in the memory 151 of the compensator 150, the first delay compensation value ( Δr1), the second delay compensation value Δr2, and the third delay compensation value Δr3 may be stored. Here, the first delay compensation value Δr1 may be 0, the second delay compensation value Δr2 may be 0.07, and the third delay compensation value Δr3 may be 1.2.

In addition, all pixels P of the display panel 110 display the same grayscale, and accordingly, the timing controller 140 performs the first first image data RGB_A, the second first image data RGB_B, and the third at the same level. The initial image data RGB_C can be generated. The first first image data RGB_A corresponds to the pixel P at the first point A, the second initial image data RGB_B corresponds to the pixel P at the second point B, and the third The initial image data RGB_C is image data corresponding to the pixel P of the third point C. Here, it is assumed that each of the first to third initial image data RGB_A to RGB_C has a level of 10.

In addition, the number of the plurality of data lines DL1 to DLm of the display panel 110 is 1920 in total, the pixel P of the first point A is connected to the first data line, and the pixel P of the second point B is P) may be connected to the 960 th data line, and the pixel P of the third point C may be connected to the 1920 th pixel P.

4 and 6A , the data modulator 155 of the compensation unit 150 performs first to third delay compensation values Δr1 to Δr3 stored in the memory 151 according to the first to third delay compensation values Δr1 to Δr3. Data compensation values ΔV1 to ΔV3 can be generated, respectively.

For example, the data modulator 155 may generate the first data compensation value ΔV1 0 according to the first delay compensation value Δr1. In addition, the data modulator 155 generates a second data compensation value ΔV2 of 0.35 according to the second delay compensation value Δr2, and a third data compensation value according to the third delay compensation value Δr3 (ΔV3) 1.2 can be generated.

The data modulator 155 receives the first to third compensation image data RGB_A from the first to third first image data RGB_A to RGB_C according to the generated first to third data compensation values ΔV1 to ΔV3. '~RGB_C') can be created.

In this case, the data modulator 155 is configured to increase the level of the first image data RGB_A to RGB_C according to the data compensation values ΔV1 to ΔV3 based on the first compensated image data RGB_A′, the second compensated image Data RGB_B' and third compensation image data RGB_C' may be generated.

Specifically, the data modulator 155 may generate the first compensated image data RGB_A' from the first first image data RGB_A according to the first data compensation value ΔV1. Here, since the first data compensation value ΔV1 is 0, the data modulator 155 may output the first first image data RGB_A 10 as the first compensation image data RGB_A′.

Next, the data modulator 155 generates the second compensation image data RGB_B' and the third compensation image data RGB_C from the second data compensation value ΔV2 and the third data compensation value ΔV3, respectively. can do. Here, the data modulator 155 may generate the second compensated image data RGB_B' and the third compensated image data RGB_C whose level is increased based on the first compensated image data RGB_A'.

That is, the data modulator 155 may generate the second compensated image data RGB_B' 10.35 by adding the second data compensation value ΔV2 of 0.35 to the second first image data RGB_B 10 . Also, the data modulator 155 may generate the third compensated image data RGB_C 11.2 by adding the third data compensation value ΔV3 1.2 to the third first image data RGB_C 10 .

In this way, the data modulator 155 may generate the second compensated image data RGB_B' and the third compensated image data RGB_C whose level is gradually increased based on the first compensated image data RGB_A'. . In addition, each of the plurality of driving chips 130_a to 130_c of the data driver 130 has different levels according to the first to third compensation image data RGB_A′ to RGB_C′ output from the data modulator 155 . A data signal may be generated and outputted to the corresponding data lines DL1 to DLm.

In other words, the first driving chip 130_a of the data driver 130 may generate a data signal according to the first compensation image data RGB_A' and output it through the first data line DL1. In addition, the second driving chip 130_b outputs a data signal generated according to the second compensation image data RGB_B' through the (m/2)-th data line DL(m/2), and the third driving chip 130_b. The chip 130_c may output a data signal generated according to the third compensation image data RGB_C through the m-th data line DLm. Here, since the third compensated image data RGB_C is at a level greater than that of the first and second compensated image data RGB_A' and RGB_B', the data signals generated by the third driving chip 130_c are also first and second driving It may have a level greater than a data signal generated by each of the chips 130_a and 130_b.

As described above, the compensator 150 generates compensation image data RGB_A′ to RGB_C′ whose level is increased in proportion to the distance between the gate driver 120 and each pixel P of the display panel 110 . can be printed out. At this time, the compensation image data RGB_A' to RGB_C' output from the compensator 150 is based on the first compensation image data RGB_A' corresponding to the first data line DL1 of the display panel 110 . Levels of the remaining compensation image data RGB_B' to RGB_C' may be gradually increased. Accordingly, the data signal output from the data driver 130 may also gradually increase the level of the data signal output to the remaining data lines DL2 to DLm based on the data signal output to the first data line DL1. .

That is, in the display device 100 of the present embodiment, the data signal output from the data driver 130 has a level proportionally increased according to the distance between the gate driver 120 and the pixel P, so that the delay of the gate signal is reduced. Accordingly, it is possible to improve the charging failure of the data signal of the pixel (P).

Accordingly, as shown in FIG. 7 , in the display device 100 of the present invention, the display panel 110 can have a uniform luminance level L2, and thus, the display device 100 of the present invention can be It is possible to improve the phenomenon L1 in which the luminance level is lowered according to the distance between the gate driver and the pixel in the display device of , and the luminance non-uniformity occurs.

On the other hand, in the display device 100 of the present embodiment, the data signal output from the data driver 130 to the first data line DL1 is generated from original image data, and the data signal increases toward the mth data line DLm. The level gradually increases. Accordingly, the power consumed by the data driver 130 may increase, and this needs to be improved.

Accordingly, referring to FIGS. 4 and 6B , as described above, the data modulator 155 of the compensation unit 150 includes the first to third delay compensation values Δr1 to Δr3 stored in the memory 151 . Accordingly, the first to third data compensation values ΔV1 to ΔV3 each having sizes of 0, 0.35, and 1.2 may be generated.

In addition, the data modulator 155 receives the first to third compensation image data RGB_A from the first to third first image data RGB_A to RGB_C according to the first to third data compensation values ΔV1 to ΔV3. '~RGB_C') can be created.

At this time, the data modulator 155 is a first compensated image whose level is lower than that of the original image data RGB_A to RGB_C according to the data compensation values ΔV1 to ΔV3 based on the third compensated image data RGB_C'. Data RGB_A' and second compensation image data RGB_B' may be generated.

Specifically, the data modulator 155 may generate the third compensated image data RGB_C' from the third first image data RGB_C according to the first data compensation value ΔV1. Here, since the first data compensation value ΔV1 is 0, the data modulator 155 may output the third first image data RGB_C 10 as the third compensation image data RGB_C′.

Next, the data modulator 155 converts the second compensation image data RGB_B' and the first compensation image data RGB_A' from the second data compensation value ΔV2 and the third data compensation value ΔV3, respectively. can create Here, the data modulator 155 may generate the second compensated image data RGB_B' and the first compensated image data RGB_A' whose level is reduced based on the third compensated image data RGB_C'.

That is, the data modulator 155 may generate the second compensated image data RGB_B' of 9.65 by subtracting the second data compensation value ΔV2 of 0.35 from the second first image data RGB_B 10 . In addition, the data modulator 155 may generate the first compensated image data RGB_A' 8.8 by subtracting the third data compensation value ΔV3 1.2 from the first first image data RGB_A 10 .

In this way, the data modulator 155 may generate the first compensated image data RGB_A' and the second compensated image data RGB_B' whose level is reduced based on the third compensated image data RGB_C'. . In addition, each of the plurality of driving chips 130_a to 130_c of the data driver 130 has different levels of data according to the first to third compensation image data RGB_A′ to RGB_C′ output from the data modulator 155 . Signals can be generated and output to the corresponding data lines DL1 to DLm.

Here, the first driving chip 130_a of the data driver 130 may generate a data signal according to the first compensation image data RGB_A' and output it through the first data line DL1. In addition, the second driving chip 130_b outputs a data signal generated according to the second compensation image data RGB_B' through the (m/2)-th data line DL(m/2), and the third driving chip 130_b. The chip 130_c may output a data signal generated according to the third compensation image data RGB_C through the m-th data line DLm. Here, since the third compensated image data RGB_C is at a level greater than that of the first and second compensated image data RGB_A' and RGB_B', the data signals generated by the third driving chip 130_c are also first and second driving It may have a level greater than a data signal generated by each of the chips 130_a and 130_b.

As described above, the compensator 150 generates and outputs compensation image data RGB_A' to RGB_C' according to the distance between the gate driver 120 and each pixel P of the display panel 110, but the display panel Based on the third compensation image data RGB_C' corresponding to the m-th data line DLm of 110, the level gradually increases toward the first compensation image data RGB_A' corresponding to the first data line DL1. can be created to be reduced. Accordingly, the data signal output from the data driver 130 has a level of the data signal output to the remaining data lines DL1 to DL(m-1) based on the data signal output to the m-th data line DLm. may gradually decrease.

That is, in the display device 100 of the present embodiment, the data signal output from the data driver 130 has a reduced level in inverse proportion to the distance between the gate driver 120 and the pixel P, so that the delay of the gate signal is reduced. Accordingly, it is possible to improve the charging failure of the data signal of the pixel (P).

Accordingly, as shown in FIG. 7 , in the display device 100 of the present invention, the display panel 110 can have a uniform luminance level L2, and thus, the display device 100 of the present invention can be It is possible to improve the phenomenon L1 in which the luminance level is lowered according to the distance between the gate driver and the pixel in the display device of , and the luminance non-uniformity occurs.

In addition, in the display device 100 of the present embodiment, the data signal output from the data driver 130 to the m-th data line DLm is generated from original image data, and the data signal increases toward the first data line DL1. Since the level is gradually decreased, it is possible to prevent an increase in power consumption in the data driver 130 .

Although many matters are specifically described in the above description, these should be construed as examples of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and equivalents to the claims.

100: display device 110: display panel
120: gate driving unit 130: data driving unit
140: timing control unit 150: compensation unit
151: memory 155: data modulator

Claims (10)

a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels;
a gate driver generating a plurality of gate signals and outputting them to the plurality of gate lines;
A plurality of compensation image data is generated from a plurality of original image data corresponding to each of the plurality of data lines according to the delay compensation value, and the level of the remaining compensation image data is adjusted based on one of the plurality of compensation image data. compensation department; and
and a data driver for generating data signals according to the plurality of compensation image data and outputting them to the plurality of data lines;
The compensation unit,
Compensation image data having the same level as the corresponding original image data is generated for the pixel connected to the data line most spaced apart from the gate driver, and the level of the compensation image data is reduced compared to the corresponding original image data for the remaining pixels. creates,
The compensation image data for the remaining pixels has a reduced level based on the compensation image data having the same level as the original image data. delete delete According to claim 1,
The compensation unit,
a memory storing the delay compensation values of different sizes; and
and a data modulator to generate a data compensation value for each of the plurality of original image data according to the delay compensation value, and to generate the plurality of compensation image data according to the data compensation value. delete delete 5. The method of claim 4,
The data modulator,
A display device for generating the remaining compensation image data having a reduced level than the one compensation image data by subtracting the data compensation value from each of the plurality of original image data based on one compensation image data. 8. The method of claim 7,
The one compensation image data is image data corresponding to an mth data line among the plurality of data lines. 5. The method of claim 4,
The delay compensation value corresponds to each of the plurality of data lines and has different sizes. delete

Images