KR102375963B1 - Method and apparatus for detecting - Google Patents

Abstract

The present embodiments relate to a method and apparatus for detecting a sequence and data in a direct sequence spread band system, and an embodiment provides an efficient method for simultaneously detecting the two pieces of information without knowing the spreading sequence and the data bit in the direct sequence spread band communication system at the same time. provide a way This is detected by replacing the received signals for several bits in the form of a matrix and repeating decoding on the chip sequence and data bits. In addition, there is provided a method for simultaneously detecting time synchronization, chip sequence, and data bit of a chip sequence in a state in which time synchronization with respect to the chip sequence is not secured.

Description

DETECTION METHOD AND APPARATUS FOR DETECTING

The present embodiments relate to a method for detecting a chip sequence and a data bit in a direct sequence spread band communication system.

The direct-sequence spread-band system is a system for communicating data by multiplying data by a chip sequence of several bits and spreading the bandwidth. In this direct sequence spread band communication method, when it is necessary to simultaneously detect a chip sequence and a data bit or to secure time synchronization when time synchronization of a chip sequence is not secured, an effective method is required.

The present embodiments may provide an efficient method for simultaneously detecting a chip sequence and a data bit in a direct sequence spread band communication scheme.

Also, the present embodiments may provide a method of simultaneously securing time synchronization when time synchronization of a chip sequence is not secured.

In one aspect, the present embodiments provide a receiver for receiving a communication signal in which each data bit is directly sequence-spreaded by N chip sequences, and an initial value of each LLR (Log Likelihood Ratio) for the data bit and the chip sequence. The initialization unit that sets, calculates the LLR value for at least one data bit and at least one chip sequence and updates the prior probability value, and repeats the LLR value calculation and the prior probability value update until a preset termination condition is satisfied It is possible to provide a detection device comprising: an iterative update unit and an output unit for outputting at least one of a data bit, a chip of a sequence, and time synchronization information based on a final LLR value that satisfies a preset termination condition .

In another aspect, the present embodiments provide a reception step of receiving a communication signal in which each data bit is directly sequence-spreaded by N chip sequences, and an initial value of each LLR (Log Likelihood Ratio) for the data bit and the chip sequence. In the initialization step of setting the LLR value for at least one data bit and at least one chip sequence, the LLR value is calculated and the prior probability value is updated, and the LLR value calculation and the prior probability value update are repeated until a preset termination condition is satisfied. It is possible to provide a detection method comprising: an iterative update step, outputting at least one of a data bit, a chip of a sequence, and time synchronization information based on a final LLR value that satisfies a preset termination condition there is.

Through this embodiment, data bits and chip sequences can be simultaneously detected with high performance in a direct-sequence spread-band communication system. In addition, it is possible to simultaneously secure time synchronization for the chip sequence. In this way, it is easy to collect information about a communication system using the direct-sequence spread-band technology.

1 is a diagram illustrating a configuration of a detection apparatus according to an embodiment of the present disclosure.
2 is a diagram illustrating a signal received by a detection apparatus according to an embodiment of the present disclosure.
3 is a diagram illustrating that a signal received by the detection apparatus according to an embodiment of the present disclosure may be interpreted as one product code.
4 is a flowchart illustrating an operation of simultaneously detecting a chip sequence and a data bit according to an embodiment of the present disclosure.
5 is a flowchart illustrating an operation of simultaneously detecting a time offset, a chip sequence, and a data bit when there is no time synchronization information according to an embodiment of the present disclosure.
6 is a flowchart of a detection method according to an embodiment of the present disclosure.

The present disclosure relates to a detection apparatus and method.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present embodiments, if it is determined that a detailed description of a related well-known configuration or function may obscure the gist of the present technical idea, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when it is described that two or more components are "connected", "coupled" or "connected", two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relationship related to the components, the operation method or the production method, for example, the temporal precedence relationship such as "after", "after", "after", "before", etc. Alternatively, when a flow precedence relationship is described, it may include a case where it is not continuous unless "immediately" or "directly" is used.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no separate explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

The direct-sequence spread-band system to which the detection apparatus and method of the present specification are applied uses a spread-band modulation scheme in which a data signal is multiplied by a digital code having a high frequency and spread. Specifically, the direct-sequence spread-band system modulates each bit of the binary data signal to be transmitted into several bits in the form of a chip constituting the chip sequence, spreads it over the frequency used, and transmits it again, in units of the original data bit. It may refer to a technology for restoring data after being converted to .

In addition, the turbo decoding technique in the present specification may refer to a technique for detecting data bits as an efficient decoding method for a product code. Specifically, the turbo decoding technique calculates the log likelihood ratio (LLR) for each information, converges to a constant value while repeatedly updating the LLR value, and then detects the transmitted data based on the final LLR. It could be technology.

Also, in the present specification, the time offset is a time point at which the start time of the chip sequence multiplied by the data bit coincides with the start time of the chip sequence, and may be time synchronization of the chip sequence.

Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a detection apparatus according to an embodiment of the present disclosure.

Referring to FIG. 1 , the detection apparatus 100 according to an embodiment of the present disclosure includes a receiving unit 110 for receiving a communication signal transmitted by having each data bit directly sequence spread by an N chip sequence, a data bit and An initialization unit 120 that sets an initial value of each LLR (Log Likelihood Ratio) for a chip sequence, calculates an LLR value for at least one data bit and at least one chip sequence, and updates a prior probability value, The iterative update unit 130 repeats calculating the LLR value and updating the prior probability value until the end condition is satisfied. Based on the final LLR value that satisfies the preset end condition, among the data bits, chips of the sequence, and time synchronization information The detection apparatus 100 including the output unit 140 for outputting at least one may be provided.

The receiver 110 may receive a communication signal in which each data bit is directly sequence-spreaded by a sequence of N chips and transmitted. For example, when the receiving unit 110 receives data corresponding to M data bits, since each data bit is transmitted by being spread by N chips, it is to be received as a communication signal represented by a matrix of M×N size. can Details of the received signal will be described later with reference to FIGS. 2 and 3 .

The initialization unit 120 may set each LLR initial value for the data bit and the chip sequence. For example, the initialization unit 120 may set an absolute value of an LLR initial value for a data bit or one bit of chip sequences.

As another example, the initialization unit 120 may set the absolute value of the LLR initial value corresponding to a specific bit among the data bits and the chip sequence to be larger than the absolute value of other bits. Alternatively, the initialization unit 120 may set the absolute value of the data bit and the LLR value of the chip sequence within a predetermined range from 0 or 0.

The iterative updater 130 may calculate an LLR value for at least one data bit and at least one chip sequence and update the prior probability value. Also, the iterative update unit 130 may repeat calculating the LLR value and updating the prior probability value until a preset termination condition is satisfied. For example, the iterative update unit 130 calculates an LLR value for a data bit and a chip sequence, converges to a constant value while repeatedly updating the LLR value, and then transmits data based on the final LLR value. bit can be detected. In addition, the iterative updater 130 may select an update order from among the data bits and the chip sequence, calculate the LLR values in order, calculate the prior probability value, and update it.

The output unit 140 may detect and output at least one of a data bit, a chip sequence, and time synchronization information based on a final LLR value that satisfies a preset termination condition. For example, the output unit 140 may detect and output at least one of a data bit, a chip sequence, and time synchronization information based on a final LLR value calculated from the selected time offset. In this case, the termination condition may be set as a case in which the number of repetitions of the iterative updater 130 is repeated a preset number of times or a case in which the amount of change in the LLR value is equal to or less than a specific value.

2 is a diagram illustrating a signal received by a detection apparatus according to an embodiment of the present disclosure.

Referring to FIG. 2 , the receiver 110 of the detection apparatus 100 according to an embodiment of the present disclosure may receive a signal transmitted by a spread band communication system. For example, the receiver 110 may receive data corresponding to M data bits, and since each data bit is spread by N chips, the total received signal may be M×N.

The signal received by the receiver 110 may be displayed in a two-dimensional array. In this case, each row of the received signal may be a signal received for different data bits, and each column may be a signal received by using different chips. For example, as for the signal received by the receiver 110 , M-bit data bits serve as inputs on the vertical axis, and N-bit chip sequences operate as inputs on the horizontal axis 320 to generate a total of M×N signals. can do. Therefore, in the present specification, it is described as receiving a signal in the form of an M×N matrix, but this may mean converting the received signal into an M×N matrix.

More specifically, according to an example, the direct-sequence spread-band system may transmit data by multiplying data by a chip sequence of several bits and spreading the band. In addition, processing gain of the spread-band communication system may mean G=Tb/Tc when one data bit has a length Tb and one chip has a length Tc. Accordingly, the signal s(t) for transmitting one data bit can be expressed as in Equation 1 when one data bit is multiplied by N chip sequences and transmitted.

where c1,… ,cN may indicate a chip sequence, a may indicate a data bit to be transmitted, and h(t) may indicate a waveform through which one chip is transmitted.

Also, the receiver 110 may collect spread-band signals for several bits using several data bits transmitted using the same spreading sequence. For example, if a transmission signal composed of M bits is multiplied and transmitted using the same certainty sequence, it can be expressed as in Equation (2).

The receiver 110 may receive a signal of each chip represented by an M×N matrix, and the received signal may be expressed as Equation (3).

Here, cN may mean a chip sequence, aM may mean a data bit to be transmitted, and ni,j may mean noise added to each received signal.

Details of simultaneously detecting the chip sequence and data based on the received signal as in Equation 3 in a state in which the detection apparatus 100 does not know the chip sequence will be described later with reference to FIGS. 4 and 5 .

3 is a diagram illustrating that a signal received by the detection device according to an embodiment of the present disclosure may be interpreted as one product code.

Referring to FIG. 3 , a signal received by the receiving unit 110 of the detection apparatus 100 according to an embodiment of the present disclosure may be interpreted in the form of one product code. For example, the signal received by the receiving unit 110 may be in the form of one product code generated by the chip sequence and the data bit when time synchronization for the chip sequence is secured. In addition, the received signal may be in the form of a product code of one data bit and one chip, and may be in a form in which noise is added. The iterative update unit 130 may simultaneously detect a data bit and a chip sequence through multiple repetitions of the received signal interpreted in the form of a product code using turbo decoding technology.

The iterative update unit 130 may select an update order from among data bits and chip sequences based on the received matrix signal and update the LLR value calculation and the prior probability value calculation in order. For example, the iterative update unit 130 consists of a process of updating the LLR 310 for one or more horizontal axis data bits and a process of updating the LLR 320 for one or more vertical axis chip sequences in one iteration. do. For example, the iterative updater 130 may update the LLR 310 for a data bit once, and then update the LLR 320 for a chip sequence. Alternatively, the iterative updater 130 may be implemented to first update the LLR 320 for the chip sequence, and then update the LLR 310 for the data bit.

As another example, the iterative updater 130 may first update the LLR of information having a larger size among rows or columns of the M×N matrix signal to increase the convergence speed. On the other hand, the iterative updater 130 may first update the LLR of information having a smaller size among rows or columns of the M×N matrix signal.

4 is a flowchart illustrating an operation of simultaneously detecting a chip sequence and a data bit according to an embodiment of the present disclosure.

Referring to FIG. 4 , the detection apparatus 100 according to an embodiment of the present disclosure may detect a chip sequence and a data bit under the assumption that time synchronization with respect to the chip sequence is secured. That is, the detection apparatus 100 may detect an N-bit chip sequence and an M-bit data bit on the assumption that information on the time boundary of each bit is known in advance.

The initialization unit 120 may set an initial value of the LLR of each chip sequence and data bits (S410). For example, the initializer 120 may set the absolute value of the LLR initial values of specific bits among the chip sequence and data bits to be larger than the absolute value of the LLR initial values of the remaining bits. This can have the same effect as fixing one chip or one data bit of a chip sequence and performing detection.

For another example, the initialization unit 120 may set absolute values of LLR values of chips or data bits of all chip sequences within a predetermined range from 0 or 0, and may induce convergence to a stable value by repeatedly proceeding. In this case, setting the absolute value of the LLR value within a predetermined range from 0 or 0 may mean setting the absolute value of the LLR value to 0 or a value converging to 0. This may mean that the initialization unit 120 sets the probability that the bit of the chip and the data bit of the corresponding chip sequence is 1 or -1, respectively, to 1/2. Accordingly, although the convergence speed is slower than when the absolute value of the initial values of one bit is set to be large, the final detection performance may be improved.

The iterative updater 130 may calculate LLR values for each data bit ( S420 ). The iterative updater 130 may update the LLR values of rows that are data bits of one or more horizontal axes. For example, the iterative updater 130 may calculate the LLR for each data bit as the LLR value for d under the condition that x is received as shown in Equation (4).

Here, the transmitted signal may be d (d is +1 or -1), and the received signal may be x.

When the LLR for each data bit is calculated, the iterative update unit 130 may also calculate a prior probability of each data bit ( S430 ). For example, the iterative updater 130 may estimate the prior probability by dividing the number of samples corresponding to each data bit by the total number of samples. For example, the iterative updater 130 may estimate a prior probability, which is a probability that d has been transmitted under the condition that x is received, by using the LLR 310 for the data bit. The iterative updater 130 may detect a value close to the actual data value by using the LLR value for the data bit and the prior probability value.

The iterative updater 130 may calculate LLR values for each chip sequence ( S440 ). The iterative updater 130 may update an LLR value for a column that is a chip sequence of one or more vertical axes. For example, the iterative updater 130 may calculate an LLR value for each chip sequence as in Equation (4).

When the LLR for each chip sequence is calculated, the iterative update unit 130 may also calculate a prior probability of each data bit ( S450 ). Also, the iterative updater 130 may calculate the LLR value and the prior probability value of the chip sequence first, and then calculate the LLR value and the prior probability value of the data bit later. .

If the preset termination condition is not satisfied, the iterative update unit 130 may continuously update by repeating the process of calculating the LLR values and prior probability values for the data bit and the chip sequence ( S460 ). For example, the iterative updater 130 may set the number of repetitions of the iterative updater 130 to a predetermined number in advance. The iteration updater 130 may compare the preset number of repetitions with the actual number of repetitions of the iteration updater 130 , and when the same number of repetitions is reached, the repetition of the iteration updater 130 may be terminated.

As another example, the iterative updater 130 may set the reference value of the change amount of the LLR values as a specific value in advance. When it is determined that the amount of change in the LLR values falls below a predetermined specific value, the iterative updater 130 may terminate the iteration of the iterative updater 130 . Also, the iterative updater 130 may set the reference value of the change amount as a percentage of the previous change amount. For example, when it is determined that the amount of change from the LLR(a1) before the update to the LLR(a1) after the update is less than or equal to a preset specific percentage than the average of the overall change amount, the iterative update unit 130 may terminate the iteration.

If a preset termination condition is satisfied, the output unit 140 may output a chip sequence and data bits based on the finally obtained LLR value (S470). For example, the final LLR value can be calculated in such a way that the iterative updater 130 separates the intrinsic information and the extrinsic information of the LLR value, and updates it through multiple iterations to converge to a constant value.

Also, the output unit 140 may output the detected chip sequence and the data bit as two pairs, respectively. This is because two detected chip sequences and data bits may exist in each pair. For example, if the chip sequence is C = (c1...cn) and the data is A = (a1...am), the chip sequence is -C, the data is -A, and the signal transmitted from the transmitter are perfectly identical, so it may be impossible to distinguish them. Accordingly, if the finally detected chip sequence C and data are A, the output unit 140 may also output -C and -A.

5 is a flowchart illustrating an operation of simultaneously detecting a time offset, a chip sequence, and a data bit when there is no time synchronization information according to an embodiment of the present disclosure.

Referring to FIG. 5 , in the detection apparatus 100 according to an embodiment of the present disclosure, when there is no time synchronization information of the chip sequence, the time offset corresponding to the time synchronization information for the chip sequence is also simultaneously with the chip sequence and the data bit. can be detected. The offset determiner 150 may perform a process of detecting the chip sequence and the data bit under the assumption that the time synchronization of the chip sequence is correct for each time offset ( S510 ). In this case, each time offset may be a candidate for time synchronization of the chip sequence.

Even when there is no time synchronization information of the chip sequence, the detection apparatus 100 may perform the operation of FIG. 4 to detect the chip sequence and the data bit for each time offset Δi ( S520 ).

The offset determiner 150 may select an optimal time offset value for each time offset using LLR values of the chip sequence and data bits ( S530 ). In this case, the offset determiner 150 may set various selection criteria for selecting a time offset for time synchronization of the chip sequence.

When there is no time synchronization information of the chip sequence, the offset determiner 150 may calculate a predetermined metric for each time offset and acquire the time synchronization of the chip sequence based on the metric. Also, when there is no time synchronization information of the chip sequence, the offset determiner 150 may calculate an LLR value for each time offset or a predetermined metric for each time offset based on the detected data bit and the chip sequence.

For example, the offset determiner 150 determines the size of the final LLR value detected when the time offset is correct among the final LLR value of the chip sequence detected for each time offset and the absolute value of the final LLR value of the data bit. can be the maximum. Accordingly, after each iterative update process is completed, the offset determiner 150 may select a time offset having the final LLR value of the largest absolute value and obtain it as the time synchronization of the chip sequence.

In addition, the offset determining unit 150 selects a specific time offset in which the value obtained by summing the absolute values of the final LLR values of the chip sequence calculated for each time offset becomes the maximum value and acquires the time synchronization of the chip sequence can do. For example, the offset determiner 150 may calculate the sum of absolute values of the LLR values of the chip sequence, select a time offset at which the value is the maximum, and acquire it as time synchronization. Alternatively, the offset determiner 150 may calculate the sum of the absolute values of the LLR values of the data bits, select a time offset at which the value becomes the maximum, and obtain the time synchronously. In addition, the offset determining unit 150 is a specific time offset in which a value obtained by adding the absolute value of the final LLR value of the data bit calculated for each time offset and the absolute value of the final LLR value of the chip sequence becomes the maximum value. can be obtained as the time synchronization of the chip sequence by selecting . For example, the offset determiner 150 combines the absolute value of the LLR value of the data bit with respect to each time offset and the absolute value of the LLR value of the chip sequence for each time offset as in Equation 5 to determine when the value becomes the maximum. It can be obtained by selecting it with time synchronization.

where k1 and k2 are positive constants.

In addition, the offset determining unit 150 selects a specific time offset at which the difference or correlation value between the output data bit and the signal regenerated from the chip sequence and the received signal is the minimum value or the maximum value, and obtains the time synchronization of the chip sequence can do. For example, after the iterative update process for each time offset is finished, the offset determining unit 150 may determine the difference between the output data bit and the signal regenerated from the chip sequence and the received signal, or between the regenerated signal and the average. By selecting a specific time offset at which the ratio of the difference within the total deviation is the minimum, it can be obtained as time synchronization of the chip sequence.

The offset determining unit 150 selects a specific time offset at which the Euclidean distance between the signal obtained by encoding the output data bit and the chip sequence for each time offset and the received signal is the minimum, and the time of the chip sequence It can be obtained by motive. For example, the offset determiner 150 may restore the chip sequence and data bits after the iterative update process for each time offset is completed, and re-encode them. At this time, the offset determination unit 150 calculates the Euclidean distance between the signal obtained by encoding and the received signal as in Equation 6, and selects the time offset at which the calculation result is the smallest to obtain time synchronization. can

where D(Δi) is the judgment metric for the time offset Δi. ri, k, ai, and ck may mean a received signal, a detected data bit, and a detected chip sequence, respectively. For example, as shown in Equation 6, the decision metric may be calculated based on a distance between a signal regenerated from a detected data bit and a chip sequence and a received signal. Also, the decision metric may be calculated in various ways as shown in Equation (7).

For example, the offset determination unit 150 does not calculate the metric for each time offset as the distance between the regenerated signal and the received signal, but calculates a correlation value between the regenerated signal and the received signal, and this value is You can select a specific time offset that is maximized or minimized.

The output unit 140 may output the detected chip sequence and data bits by using the selected time offset as the time synchronization of the chip sequence ( S540 ).

Hereinafter, a detection method that can be performed by the detection apparatus described with reference to FIGS. 1 to 5 will be described.

6 is a flowchart of a detection method according to an embodiment of the present disclosure.

Referring to FIG. 6 , the detection method of the present disclosure may include a receiving step of receiving a signal ( S610 ). The detection device may receive a communication signal in which each data bit is directly sequence spread by a sequence of N chips and transmitted. As a specific example, when the detection apparatus receives a communication signal in which M data bits are spread-spread by N chip sequences and transmitted, the received signal may be represented by an M×N matrix. In this case, the signal in the form of an M×N matrix may mean that a transmitted signal is received and converted into a two-dimensional array of an M×N matrix.

The detection method may include an initialization step of setting each LLR initial value for the data bit and the chip sequence (S620). For example, the detection apparatus may set the absolute value of the LLR initial value corresponding to a specific bit among the data bits and the chip sequence to be larger than the absolute value of other bits. Alternatively, the detection apparatus may set the absolute value of the LLR value of the data bit and the chip sequence within a predetermined range from 0 or 0.

The detection method calculates the LLR value for at least one data bit and at least one chip sequence and updates the prior probability value, and repeats the LLR value calculation and the prior probability value update until a preset termination condition is satisfied. It may include a step (S630). For example, the detection apparatus may select an update order from among the data bits and the chip sequence to sequentially update the LLR value calculation and the prior probability value calculation. In this case, the detection apparatus may set the number of repetitions of the iterative update unit in advance, and may set a case in which the actual iterative update unit is repeated the preset number of times as an end condition. Alternatively, the detection apparatus may preset a reference value of the amount of change in the LLR value to a specific value, and use a case in which the amount of change in the detected LLR value is equal to or less than the specific value as an end condition.

The detection method may further include an offset determination step of calculating a predetermined metric for each time offset when there is no time synchronization information of the chip sequence, and obtaining the time synchronization of the chip sequence based on the metric (S640) . For example, when there is no time synchronization information of the chip sequence, the detection apparatus may calculate the metric for each time offset based on the LLR value for each time offset or the detected data bit and the chip sequence.

In addition, the detection apparatus may select a specific time offset at which a value obtained by summing the absolute values of the final LLR values of the chip sequence calculated for each time offset becomes the maximum value and obtain it as time synchronization of the chip sequence. Alternatively, the detection device selects a specific time offset at which a value obtained by summing the absolute value of the final LLR value of the data bit calculated for each time offset and the absolute value of the final LLR value of the chip sequence becomes the maximum value, It can be obtained by time synchronization of the sequence.

For another example, the detection device selects the difference between the output data bit and the signal regenerated from the chip sequence and the received signal, or selects a specific time offset at which the steel pipe value becomes the minimum value or the maximum value to obtain as time synchronization of the chip sequence. can Alternatively, the detection device selects a specific time offset at which the Euclidean distance between the signal obtained by encoding the output data bit and the chip sequence for each time offset and the received signal is minimized to obtain the time synchronization of the chip sequence can do.

The detection method may include an output step of outputting at least one of a data bit, a chip sequence, and time synchronization information based on a final LLR value that satisfies a preset termination condition ( S620 ). For example, when there is no time synchronization information of the chip sequence, the detection apparatus may output the detected chip sequence and data bit by using a time offset selected from each time offset as the time synchronization of the chip sequence.

As described above, according to the present disclosure, it is possible to provide a detection apparatus and method. In particular, it is possible to provide a detection apparatus and method for simultaneously detecting a chip sequence and a data bit in a state where the chip sequence and the data bit are not known at the same time in a direct sequence spread band communication system. In addition, when time synchronization with respect to the chip sequence is not secured, it is possible to provide a detection apparatus and method capable of detecting the time synchronization of the chip sequence simultaneously with the data bit and the chip sequence.

The above description is merely illustrative of the technical spirit of the present disclosure, and various modifications and variations will be possible without departing from the essential characteristics of the present disclosure by those skilled in the art to which the present disclosure pertains. In addition, the present embodiments are not intended to limit the technical spirit of the present disclosure, but rather to explain, so the scope of the present technical spirit is not limited by these embodiments. The protection scope of the present disclosure should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present disclosure.

Claims (16)

a receiving unit for receiving a communication signal in which each data bit is directly sequence-spreaded by a sequence of N chips;
an initializer for setting an initial value of each LLR (Log Likelihood Ratio) for the data bit and the chip sequence;
Calculate an LLR value for at least one or more of the data bits and at least one or more of the chip sequence and update a prior probability value,
an iterative update unit that repeats calculating the LLR value and updating the prior probability value until a preset termination condition is satisfied;
and an output unit configured to output at least one of the data bit, the chip sequence, and time synchronization information based on a final LLR value that satisfies the preset termination condition. The method of claim 1,
The initialization unit,
and setting an absolute value of the LLR initial value corresponding to a specific bit among the data bit and the chip sequence to be larger than the absolute value of other bits. The method of claim 1,
The initialization unit,
and setting an absolute value of the LLR value of the data bit and the chip sequence within a predetermined range from 0 or 0. The method of claim 1,
The iterative update unit,
and selecting an update order from among the data bits and the chip sequence to sequentially update the LLR value calculation and the prior probability value calculation. The method of claim 1,
The termination condition is
The detection apparatus according to claim 1, wherein the number of repetitions of the iterative update unit is repeated as many as a preset number of times or when the amount of change in the LLR value is equal to or less than a specific value. The method of claim 1,
If there is no time synchronization information of the chip sequence,
The detection apparatus according to claim 1, further comprising: an offset determiner configured to calculate a predetermined metric for each time offset and obtain time synchronization of the chip sequence based on the metric. 7. The method of claim 6,
If there is no time synchronization information of the chip sequence,
and calculating the metric for each time offset based on the LLR value or the data bit and the chip sequence for each time offset. 7. The method of claim 6,
The offset determining unit,
Selecting a specific time offset at which a value obtained by summing some or all of the absolute values of the final LLR values of the chip sequence calculated for each time offset becomes a maximum value is selected and acquired as time synchronization of the chip sequence detection device with 7. The method of claim 6,
The offset determining unit,
Selecting a specific time offset at which a difference or correlation value between the outputted data bit and the signal regenerated from the chip sequence and the received signal is a minimum value or a maximum value is selected and acquired as time synchronization of the chip sequence detection device. 7. The method of claim 6,
The offset determining unit,
Selecting a specific time offset at which the Euclidean distance between the signal obtained by encoding the outputted data bit and the chip sequence for each time offset and the received signal is minimized and obtained as time synchronization of the chip sequence A detection device, characterized in that. a receiving step of receiving a communication signal in which each data bit is directly sequence-spreaded by a sequence of N chips;
an initialization step of setting an initial value of each LLR (Log Likelihood Ratio) for the data bit and the chip sequence;
Calculate an LLR value for at least one or more of the data bits and at least one or more of the chip sequence and update a prior probability value,
an iterative update step of repeating calculating the LLR value and updating the prior probability value until a preset termination condition is satisfied;
and an output step of outputting at least one of the data bit, the chip sequence, and time synchronization information based on a final LLR value that satisfies the preset termination condition. 12. The method of claim 11,
The initialization step is
and setting the absolute value of the LLR initial value corresponding to a specific bit among the data bit and the chip sequence to be larger than the absolute value of other bits. 12. The method of claim 11,
The iterative update step is
and selecting an update order from among the data bits and the chip sequence to sequentially update the LLR value calculation and the prior probability value calculation. 12. The method of claim 11,
The termination condition is
The detection method according to claim 1, wherein the number of repetitions of the iterative update step is repeated a preset number of times or the amount of change in the LLR value is less than or equal to a specific value. 12. The method of claim 11,
If there is no time synchronization information of the chip sequence,
The method of claim 1, further comprising: an offset determining step of calculating a predetermined metric for each time offset, and obtaining time synchronization of the chip sequence based on the metric. 16. The method of claim 15,
In the step of determining the offset,
Selecting a specific time offset at which a difference or correlation value between the outputted data bit and the signal regenerated from the chip sequence and the received signal is a minimum value or a maximum value is selected and acquired as time synchronization of the chip sequence detection method.

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