KR102045764B1 - Sram cell for generating true random number and sram cell arry driving circuit using the same - Google Patents

Abstract

The present invention relates to a technique for generating a true random number using a static noise margin (SRAM) characteristics and a read noise margin (Read Noise Margin) characteristics of the SRAM.
The first aspect of the present invention is to reduce the noise margin by forming the first and second NMOS transistors constituting the latch smaller than or equal to the size of each of the first and second access NMOS transistors.
According to a second aspect of the present invention, a noise margin is reduced by setting a voltage between a first node of a first inverter and a second node of a second inverter constituting a latch to an intermediate level between an internal power supply voltage and a ground voltage.

Description

SRAM cell for real-time water generation and SRAM cell array driving circuit having same {SRAM CELL FOR GENERATING TRUE RANDOM NUMBER AND SRAM CELL ARRY DRIVING CIRCUIT USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for generating a true random number, and in particular, using a static noise margin and a read noise margin characteristic of SRAM. The present invention relates to an SRAM cell for generating a true random number and an SRAM cell array driving circuit including the same.

In recent years, the spread of mobile devices has been widely expanded, and research and development for the 4th industry (AI, IoT, electric vehicles, big data) is being actively performed. In this regard, the damage caused by hacking is rapidly increasing. Accordingly, the problem of communication security is seriously emerging. As part of solving the problem of communication security, a security code using a random number generator has been proposed. However, such a security code is generated by using a predetermined algorithm or a table, so there is a problem of inferior safety.

In particular, the development of AI and deep learning technologies is a serious threat to communication security. In order to solve this problem, a random number generator using randomness of light has been proposed. (Korean Patent No. 10-1729663, US Patent No. 9335973 B2) However, such a random number generator uses a light source unit using LEDs and a CIS (CMOS Image). Since a light collecting unit and a measuring unit such as a sensor must be provided, there is a problem in that the cost is high. In addition, a random number generator using radioisotopes may cause safety problems due to radiation leakage in addition to cost problems.

In addition, a random number generator using static random access memory (SRAM) has been proposed, which is mainly used as a physically unclonable function (PUF) (US Patent Publication No. US 2014/0040338). PUF generates random numbers according to the randomness of the process in which each device is made, so unlike a random number generator that generates a new random number every new operation, there is a limit that only one random number is generated in one device.

In addition, PUF technology includes random number generation technology that generates random numbers using oxide breakdown voltage of transistors, and random number generation technology that uses randomness of semiconductor contact process. There is a limit that can provide only.

Domestic Patent 10-1729663 United States Patent US 9335973 B2 United States Patent Publication No. US 2014/0040338

The first problem to be solved by the present invention is generated by using the static noise margin characteristics and lead noise margin characteristics of the SRAM in the intelligent communication required for the security authentication between devices or between devices and systems in IoT communication, It is implemented at cost and can generate random number in stable state.

The second problem to be solved by the present invention is generated by using the static noise margin characteristics and lead noise margin characteristics of the SRAM, the random number required for security authentication between devices or between devices and systems in the IoT communication, SoC (System on Chip) It is to make IP (Intellecture Property) so that it can be embedded and used in the product.

A third problem to be solved by the present invention is to generate a random number required for security authentication between devices or between devices and systems in IoT communication using the static noise margin characteristics and lead noise margin characteristics of the SRAM, A random number generator is included in the SRAM compiler to enable design automation.

According to an embodiment of the present invention for achieving the above technical problem, the SRAM cell for generating a random number comprises: a first PMOS transistor and a first NMOS transistor, a second PMOS transistor, and a second NMOS constituting each inverter. A latch having a transistor to perform a latch function; A first access terminal having one terminal connected to a bit line, the other terminal connected to a first node connected to the other terminal of the first PMOS transistor and one terminal of the first NMOS transistor, and the gate connected to a word line. MOS transistor; And a second terminal having one terminal connected to a bit bar line, the other terminal connected to a second node connected with the other terminal of the second PMOS transistor and one terminal of the second NMOS transistor, and a gate connected to the word line. And an access NMOS transistor, wherein the size of each of the first and second NMOS transistors is smaller than or equal to the size of each of the first and second access NMOS transistors, thereby reducing noise margin.

According to another aspect of the present invention, an SRAM cell array driving circuit including an SRAM cell for generating a random number includes: a first PMOS transistor and a first NMOS transistor constituting each inverter; A latch having a second PMOS transistor and a second NMOS transistor to perform a latch function, one terminal of which is connected to a bit line, and the other terminal of the other terminal of the first PMOS transistor and the first NMOS transistor A first access NMOS transistor connected to a first node having one terminal connected thereto and a gate connected to a word line, and one terminal connected to a bit bar line, and the other terminal connected to the other terminal and the second terminal of the second PMOS transistor. A second access NMOS transistor connected to a second node connected to one terminal of the NMOS transistor and a gate connected to the word line SRAM cell array having a random number generating SRAM cells having an array form; A word line driver supplying word line signals to the SRAM cell array; And a power driver for supplying an internal power supply voltage to the SRAM cell array, wherein the size of each of the first and second NMOS transistors is smaller than or equal to the size of each of the first and second access NMOS transistors. It is characterized by reducing the noise margin.

The present invention can generate a natural random number by using the static noise margin and read noise margin characteristics of SRAM, so that devices can communicate with each other or Safe security authentication between device and system is possible.

In addition, since the use of commonly used SRAM cell memory can be reused devices or programs that have already been verified, there is an effect that can be configured in a relatively cheap and secure security authentication system.

In addition, since the random number generation SRAM cell array, the word line driver and the power driver can be designed in a module form, it can be easily applied to the existing SRAM compiler, thereby realizing design automation.

1 is a circuit diagram of an SRAM cell for generating a genuine water according to the present invention.
FIG. 2 is a circuit diagram of an SRAM cell for generating random water according to another embodiment of the present invention. FIG.
3 is a static noise margin characteristic graph of an SRAM cell.
4 is a graph of lead noise margin characteristics of an SRAM cell.
5 is a graph of lead noise margin characteristics of an SRAM cell having an unstable state according to the present invention.
FIG. 6 is a block diagram of an SRAM cell array driving circuit having an SRAM cell for generating a random number according to another embodiment of the present disclosure. FIG.
Figure 7 is a block diagram of an SRAM drive circuit having a true water generator according to the present invention.
Figure 8 is a cross-sectional view of the SRAM cell for generating a genuine water in accordance with the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a static random number access memory (SARM) cell according to the present invention.

Referring to FIG. 1, the SRAM cell 100 for generating a random number according to the present invention includes a PMOS transistor and an NMOS transistor MP1, MN1, and MP2, MN2 constituting each inverter, and have a latch function. Latch 110, one terminal (drain) is connected to the bit line BL, and the other terminal (source) is connected to the node n1 of the PMOS transistor and the NMOS transistors MP1 and MN1. And an access NMOS transistor MN3 having a gate connected to the word line WL, and one terminal (drain) connected to the bit bar line / BL, and the other terminal (source) connected to the PMOS transistor and the NMOS. It is connected to the node n2 of the transistors MP2 and MN2, and the gate includes an access NMOS transistor MN4 connected to the word line WL.

According to a first aspect of the present invention, a read noise margin (RNM) becomes unstable by adjusting a size ratio between a transistor constituting a latch and an access transistor in the SRAM cell 100 for generating a random number. To generate a random number.

In general, the SRAM cell has one of a static state and an operating state, but the random number generating SRAM cell 100 according to the present invention is in an unstable state or an unstable state. Unknown State). The static state is a state in which 'low' is supplied to the word line WL so that the access NMOS transistor (N-channel MOS transistor) MN3 and the access NMOS transistor MN4 are turned off. The operating state is a state in which 'high' is supplied to the word line WL so that the access NMOS transistors MN3 and MN4 are turned on.

3 illustrates a static noise margin (SNM) characteristic of the SRAM cell 100A, and FIG. 4 illustrates a read noise margin (RNM) characteristic of the SRAM cell 100A.

The size of the NMOS transistors MN1 and MN2 constituting the latch 110 (the value obtained by dividing the width of the transistor by the length) is the access NMOS transistor MN3 and the access NMOS transistor. If they are formed to be smaller than or equal to the size of MN4, the lead noise margin characteristic of the SRAM cell 100 for generating a random number is not fixed to a stable state as shown in FIG. 4 and is unstable as shown in FIG. It becomes

Accordingly, random data may be generated through the random number generation SRAM cell 100 in an operation state of the random number generation SRAM cell 100.

Since the random number generation SRAM cell 100 can be designed in the form of a module (block), it can be easily applied to an existing SRAM compiler, thereby realizing design automation. .

On the other hand, Figure 2 shows a circuit diagram of an SRAM cell for generating a random number according to another embodiment of the present invention. 2 is compared with FIG. 1, FIG. 1 shows that the SRAM cell 100 for generating a random number has a single port, while FIG. 2 shows that the SRAM cell 200 for generating a random number is dual. The difference is that it has a dual port.

The random number generation SRAM cell 200 has NMOS transistors MN21 and MN22 serving as transfer gates for connecting the bit lines BLA and BLB to the latch 210. And NMOS transistors MN23 and MN24 serving as transfer gates for connecting the BLA and / BLB to the latch 210.

In the SRAM cell 200 for generating a random number, the sizes of the NMOS transistors MN1 and MN2 constituting the latch 210 are smaller than the sizes of the NMOS transistors MN21 and MN22 and MN23 and MN24. In this case, the lead noise margin characteristic of the SRAM cell 200 for generating the random number water is not stabilized as shown in FIG. 4, but becomes unstable as shown in FIG. 5.

Accordingly, in the operating state of the true random number generating SRAM cell 200, the true random number may be generated through the true random number generating SRAM cell 200.

The second feature of the present invention is that the level of the node voltage of the random number generating SRAM cell 100 does not bias the level of the power supply voltage or the ground voltage, but has their intermediate level so that the random number generating SRAM cell 100 A true random number is generated in such a way that the read data value is determined by the difference in the offset value of the parasitic capacitor, the resistor, or the sense amplifier.

When the high voltage is supplied to the word line WL and the access NMOS transistors MN3 and MN4 are turned on, when the level of the power supply voltage VDD is raised from the ground level of 0V to the target level, it is unstable. The voltages of the nodes n1 and n2 in the random number generation SRAM cell 100 having the lead noise margin (RNM) characteristic of the parasitic resistance are not biased by the level of the internal power supply voltage VDDI or the ground voltage. In addition, the capacitance of the parasitic capacitor is set to a voltage of an intermediate level between the internal power supply voltage VDDI and the ground voltage. That is, the voltages of the nodes n1 and n2 are not fixed to any one of the zones P1, P2, and P3 in FIG. 4, and are arbitrarily selected among them according to the value of the parasitic resistance or the capacitance of the parasitic capacitor. Is set to the zone of. The internal power supply voltage VDDI is a voltage divided by the power supply voltage VDD.

In this state, when the data of the random number generation SRAM cell 100 is read, the voltage difference between the bit line BL and the bit bar line / BL is not consistently read as '0' or '1'. Is so small that the difference between the offset values of the PMOS and NMOS transistors MP1 and MN1 and MP2 and MN2 constituting the latch 110 or the difference between parasitic capacitors and parasitic resistances, or the bit line BL and the bit bar line. It is unstable as '0' or '1' due to the difference in the offset value of the sense amplifier connected to (/ BL).

Accordingly, random data may be generated through the random number generation SRAM cell 100 in a read mode in which data is read from the random number generation SRAM cell 100. .

In this state, when the 'high' supplied to the word line WL is shifted to 'low', the access NMOS transistors MN3 and MN4 are turned off to generate the SRAM cell 100 for generating the random number. ) Exhibits static noise margin characteristics as shown in FIG. 3, and thus the random number generating operation of the random number generating SRAM cell 100 is terminated.

Meanwhile, FIG. 6 illustrates an SRAM cell array driving circuit having an SRAM cell for generating random water according to another embodiment of the present invention.

Referring to FIG. 6, the SRAM cell array driving circuit 300 according to the present invention includes an SRAM cell array 310, a word line driver 320, and a power driver 330.

The SRAM cell array 310 includes a random number generating SRAM cell 311 as shown in FIG. 1 or 2 arranged in an array to generate a true random number according to the first or second features.

The word line driver 320 supplies word line signals WL [0] -WL [n] to the SRAM cell array 310.

The power driver 330 supplies an internal power supply voltage VDDI to the SRAM cell array 310.

At this time, the slope of the word line signals WL [0] -WL [n] output from the word line driver 320 is properly adjusted, or the slope of the internal power supply voltage VDDI output from the power driver 330 is appropriately adjusted. When adjusted, some of the random number generating SRAM cells 311 of the SRAM cell array 310 are placed in a static state and others are placed in an operation state.

Here, the slopes of the word line signals WL [0] -WL [n] output from the word line driver 320 or the slopes of the internal power voltage VDDI output from the power driver 330 are thermal noise. It is also affected by the flicker noise (1 / f noise) or power noise (power noise), the cell data (cell data) is also affected by the alpha particles (alpha particles).

As a result, since the random number generating SRAM cells 311 are placed in a static state or in an operation state, it is determined by noise, and thus, each time the SRAM cell array 310 is operated. It is possible to generate random data.

In addition, the slope of the word line signals WL [0] -WL [n] output from the word line driver 320 or the slope of the internal power supply voltage VDDI output from the power driver 330 are changed at predetermined intervals. In addition, if the delay time at which the voltage between the bit line BL and the bit bar line / BL is developed is also changed at regular intervals, a more random random number can be generated.

The SRAM cell array 310, the word line driver 320, and the power driver 330 may be manufactured in a module form and may be easily applied to an SRAM compiler, thereby enabling design automation.

On the other hand, Figure 7 shows a block diagram of an SRAM driving circuit having a true random number generator (TRNG) according to the present invention.

Referring to FIG. 7, the SRAM driving circuit 700 according to the present invention includes a cell array 723 for a random number generator, a word line driver 721 for a random number generator, a power driver 722 for a random number generator, and a binary. The random number generator includes a precharge circuit 720, a general cell array 710, a word line driver 730, a precharge circuit 741, a Y-decoder 742, and a sense amplifier and write driver 743.

The random number generator precharge circuit 720 is disposed in an N-Well such as a cell array that generates a random number, and uses an internal power supply voltage VDDI such as a cell array that generates a random number. The enwell is separated from an enwell including a cell array and a precharge circuit which do not generate a random number.

On the other hand, Figure 8 is a cross-sectional view of the SRAM cell for generating a random number according to the present invention, when compared with the conventional SRAM cell, in the case of the conventional SRAM cell, the power supply voltage ( Compared to the VDD), the internal power supply voltage divided by the PMOS transistor MP and the NMOS transistor MN of the power driver in the power supply voltage VDD in the SRAM cell for generating a random number according to the present invention. There is a difference in supplying (VDDI) to the latch of the SRAM cell.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and may be implemented in various embodiments based on the basic concept of the present invention defined in the following claims. Such embodiments are also within the scope of the present invention.

100,200: SRAM cell 110 for generating a random number of water: latch
300: SRAM cell array driving circuit 310: SRAM cell array
320: Wordline driver 330: Power driver

Claims (8)

A latch including a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor constituting each inverter to perform a latch function;
A first access terminal having one terminal connected to a bit line, the other terminal connected to a first node connected to the other terminal of the first PMOS transistor and one terminal of the first NMOS transistor, and the gate connected to a word line. MOS transistor; And
A second access having one terminal connected to a bit bar line, the other terminal connected to a second node connected to the other terminal of the second PMOS transistor and the one terminal of the second NMOS transistor, and a gate connected to the word line Including; for NMOS transistor,
The voltage of the first node and the second node is
It is set to the middle level between the internal power supply voltage and the ground voltage.
The size of each of the first and second NMOS transistors is smaller than or equal to the size of each of the first and second access NMOS transistors, so that the noise margin is reduced.
delete The method of claim 1, wherein the internal power supply voltage
An SRAM cell for generating genuine water, characterized in that a voltage divided by a power supply voltage.
A latch having a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor constituting each inverter to perform a latch function, and one terminal thereof is connected to the bit line, and the other terminal thereof. Is connected to a first node connected to the other terminal of the first PMOS transistor and one terminal of the first NMOS transistor, and the first access NMOS transistor and one terminal of which the gate is connected to the word line are connected to the bit bar line. And a second terminal having a second access NMOS transistor connected to a second node connected to the other terminal of the second PMOS transistor and one terminal of the second NMOS transistor, and having a gate connected to the word line. An SRAM cell array in which random number generation SRAM cells are arranged in an array form;
A word line driver supplying word line signals to the SRAM cell array; And
Including a power driver for supplying an internal power supply voltage to the SRAM cell array,
The voltage of the first node and the second node is
It is set to the middle level between the internal power supply voltage and the ground voltage.
The first and second NMOS transistors each have a size smaller than or equal to the size of each of the first and second access NMOS transistors, thereby reducing noise margin. SRAM cell array driving circuit.
delete The method of claim 4, wherein the wordline driver
The slope of the word line signals is adjusted so that some of the random number generating SRAM cells of the SRAM cell array are placed in a static state and others are placed in an operation state. An SRAM cell array driving circuit having a random number generation SRAM cell.
The method of claim 4, wherein the power driver
Adjusting the slope of the internal power supply voltage so that some of the random number generation SRAM cells of the SRAM cell array is placed in a static (static) state, the rest is in an operation (operation) state An SRAM cell array driving circuit having a random number generation SRAM cell.
5. The method of claim 4, wherein the SRAM cell array, the word line driver, and the power driver are manufactured in a module form, and thus applied to an SRAM compiler to enable design automation. An SRAM cell array driving circuit having an SRAM cell.

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