KR102007832B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a gate electrode formed on a substrate on which a plurality of pixel regions are defined, and having a plurality of gate fingers spaced apart from each other with a predetermined width and spacing; A gate insulating film formed over the gate electrode over the substrate; An oxide semiconductor layer formed in an island shape on the gate insulating layer to correspond to the gate fingers; An etch stopper formed on the oxide semiconductor layer and the gate insulating layer and overlapping each of the plurality of gate fingers and having the same planar shape; A source electrode having a plurality of source fingers spaced apart from each other and having a predetermined width on the oxide semiconductor layer exposed to the etch stopper and the spaced apart region thereof; The present invention provides an array substrate including a drain electrode having a plurality of drain fingers alternately spaced from the source finger and spaced apart from each other.

Description

Array substrate and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to an array substrate having an oxide semiconductor layer excellent in device characteristic stability and capable of simplifying a process and a method of manufacturing the same.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling voltage on and off, is realized in each pixel. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is configured to remove each pixel area on / off.

1 is a cross-sectional view of a portion of one pixel area in a conventional array substrate.

As shown in the drawing, a gate electrode may be formed in the switching region TrA in the plurality of pixel regions P defined by crossing a plurality of gate lines (not shown) and a plurality of data lines 33 on the array substrate 11. 15) is formed.

In addition, a gate insulating film 18 is formed on the entire surface of the gate electrode 15, and a semiconductor layer including an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon is sequentially formed thereon. 28 is formed.

In addition, the ohmic contact layer 26 is spaced apart from each other to correspond to the gate electrode 15, and a source electrode 36 and a drain electrode 38 are formed. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26.

The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, the thickness difference (t1 ≠ t2) of the active layer 22, more precisely the source and drain in which the channel layer is formed therein. As the thickness of the thin film transistor Tr is reduced in the portions exposed between the electrodes, deterioration of the characteristics of the thin film transistor Tr occurs.

Therefore, recently, as shown in FIG. 2 (sectional view of a part of one pixel region of an array substrate having a thin film transistor having an oxide semiconductor layer), an oxide semiconductor material is used without requiring an ohmic contact layer. Thus, a thin film transistor having a single layer oxide semiconductor layer 77 has been developed.

Since the oxide semiconductor layer 77 does not need to form an ohmic contact layer, spaced apart ohmic layers made of impurity amorphous silicon of a similar material as in the array substrate (11 of FIG. 1) having a semiconductor layer made of conventional amorphous silicon. Since it is not necessary to be exposed to the dry etching that proceeds to form the contact layer, it is possible to prevent deterioration of the characteristics of the thin film transistor Tr.

However, when the oxide semiconductor layer 77 is exposed to an etchant for patterning a metal layer made of a metal material, the oxide semiconductor layer 77 has no selectivity with the metal layer and is etched away, or its internal structure is damaged by exposure to the etchant, thereby thin film transistors. May affect the properties of (Tr).

Accordingly, the oxide semiconductor layer 77 disposed below the oxide semiconductor layer 77 reacts with the metal material forming the source and drain electrodes 81 and 83 during patterning for forming the source and drain electrodes 81 and 83 made of the metal material. In order to prevent exposure to the etchant, an etch stopper 79 formed of an inorganic insulating material is disposed on the center portion of the oxide semiconductor layer 77 at an upper portion thereof.

However, in manufacturing the conventional array substrate 71 including the oxide semiconductor layer 77 and the thin film transistor Tr having the etch stopper 79 thereon, the etch stopper 79 may be formed. A mask process including a single exposure process using an exposure mask (not shown) provided with a transmission region or a blocking region at a position corresponding to the etch stopper 79 is added, and a total of six mask processes are performed.

The mask process includes five unit processes of photoresist application, exposure using an exposure mask, development of exposed photoresist, etching, and strip, so the process is complicated and many chemicals are used. Increasing the production time, the productivity per unit time is lowered, the frequency of occurrence of defects is higher, the manufacturing cost is increased.

Therefore, in the case of the conventional array substrate 71 having the oxide semiconductor layer 77 and the etch stopper 79 shown in FIG. 2, it is required to simplify the process and reduce the manufacturing cost.

Further, when manufacturing the conventional array substrate 71 including the oxide semiconductor layer 77 and the etch stopper 79, the process margin of the etch stopper 79, the etch stopper 79, the oxide semiconductor layer 77, and the source The channel length of the thin film transistor Tr is increased because the exposure misalignment margin must be taken into account when patterning the drain electrodes 81 and 83.

The source and drain electrodes 81 and 83 may be etched to prevent the oxide semiconductor layer 77 disposed outside the etch stopper 79 from being exposed to the etchant for patterning the source and drain electrodes 81 and 83. The source and drain electrodes 81 and 83 should be formed to have a relatively large area in consideration of misalignment during exposure using the exposure mask. The overlapping area between the gate electrode 73 and the gate electrode 73 increases to increase the parasitic capacitances Cgs and Cgd, thereby adversely affecting the characteristics of the thin film transistor Tr.

The present invention is to solve the above-described problem, an array having an oxide semiconductor layer that can reduce the manufacturing cost by reducing the number of times the exposure mask used while preventing the oxide semiconductor layer from being damaged by the etching liquid for patterning the metal material It is an object of the present invention to provide a substrate and a method of manufacturing the same.

Furthermore, the present invention provides an array substrate having an oxide semiconductor layer capable of improving the characteristics and display quality of a thin film transistor by reducing the area where the source and drain electrodes overlap with the gate electrode, thereby reducing parasitic capacitance. Another purpose.

According to one or more exemplary embodiments, an array substrate includes: a gate electrode having a plurality of gate fingers spaced apart from each other and having a predetermined width and a spacing formed on a substrate on which a plurality of pixel regions are defined; A gate insulating film formed over the gate electrode over the substrate; An oxide semiconductor layer formed in an island shape on the gate insulating layer to correspond to the gate fingers; An etch stopper formed on the oxide semiconductor layer and the gate insulating layer and overlapping each of the plurality of gate fingers and having the same planar shape; A source electrode having a plurality of source fingers spaced apart from each other and having a predetermined width on the oxide semiconductor layer exposed to the etch stopper and the spaced apart region thereof; And a drain electrode having a plurality of drain fingers alternate with the source finger and spaced apart from each other.

In this case, each of the plurality of source and drain fingers is located in a spaced area between the gate fingers and contacts the oxide semiconductor layer, and the adjacent source and drain fingers are spaced apart from each other on the etch stopper and face each other. It is characteristic to achieve.

And a plurality of the gate fingers provided in each pixel region form a state in which one end thereof is all connected, and a plurality of the source fingers provided in the pixel region form a state in which all one end thereof is connected to each other. A plurality of the drain fingers provided in the region is characterized in that the one end is all connected.

In addition, two or more gate fingers, source fingers, and drain fingers formed in each pixel area may be formed.

A gate line extending in one direction is formed on the substrate, and the pixel area is defined on the gate insulating layer to cross the gate line, and a data line is formed on the substrate. A passivation layer exposing the drain electrode is formed, and a pixel electrode in contact with the drain electrode is formed in each pixel area over the passivation layer.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a gate electrode having a plurality of gate fingers spaced apart from each other and having a predetermined width and a gap on a substrate on which a plurality of pixel regions are defined; Forming a gate insulating film over the gate electrode over the substrate; Forming an oxide semiconductor layer having an island shape on the gate insulating layer to correspond to the gate fingers; Forming an etch stopper over the oxide semiconductor layer and the gate insulating layer and overlapping each of the plurality of gate fingers and having the same planar shape; A source electrode having a plurality of source fingers having a predetermined width and spaced apart from the etch stopper and the oxide semiconductor layer exposed to the spaced apart region thereof, and a plurality of drain fingers alternate with the source finger and having a predetermined width and spaced apart from each other; Forming a drain electrode.

In this case, the forming of the etch stopper having the same planar shape and overlapping the plurality of gate fingers over the oxide semiconductor layer and the gate insulating layer may include forming an etch stopper material layer on the entire surface of the substrate over the oxide semiconductor layer. Steps; Forming a photoresist layer having positive photosensitive properties over the substrate above the etch stopper material layer; Irradiating UV light on the photoresist layer using a plurality of the gate fingers as an exposure mask on the rear surface of the substrate on which the photoresist layer is formed; Developing the photoresist layer irradiated with the UV light to form a photoresist pattern completely overlapping the plurality of gate fingers; Removing the etch stopper material layer exposed outside the photoresist pattern to form the etch stopper corresponding to each of the plurality of gate fingers; Advancing the strip to remove the photoresist pattern.

In addition, a plurality of the gate fingers provided in the pixel areas may be connected to all one ends thereof, and a plurality of the source fingers provided in the pixel areas may be connected to all one ends thereof. The plurality of drain fingers provided therein is characterized in that the one end is formed to be connected to all.

And forming the gate electrode includes forming a gate wiring extending in one direction on the substrate, and forming the source electrode and the drain electrode by crossing the gate wiring on the gate insulating film. Forming a data line defining the pixel region, and forming a protective layer on the entire surface of the substrate over the source electrode and the drain electrode and exposing the drain electrode on the protective layer; Forming a pixel electrode in contact with the drain electrode.

The present invention has the effect of improving the characteristics of the thin film transistor by suppressing the parasitic capacitance change caused by the overlap of the gate electrode, the source electrode and the drain electrode angle, and further suppressing the display quality deterioration caused by the parasitic capacitance change.

Furthermore, according to the present invention, the size of the parasitic capacitance of each thin film transistor itself is reduced, so that the signal quality of the data wiring due to the parasitic capacitance and the deterioration of display quality such as flicker can be suppressed.

Further, by performing the back exposure using the gate electrode as the exposure mask without the exposure mask and patterning the etching stopper, an exposure mask is not required at the time of etch stopper patterning, thereby reducing the manufacturing cost.

In addition, since the etch stopper is formed by the back exposure, it is not necessary to consider the alignment margin generated during the exposure using the exposure mask, thereby reducing the etch stopper area and finally reducing the parasitic capacitance of the thin film transistor itself.

Furthermore, when the light shielding pattern made of red pigment is further provided on the thin film transistor, the light leakage current is suppressed to prevent malfunction of the thin film transistor and to improve characteristics.

1 is a cross-sectional view of a portion of one pixel area in a conventional array substrate constituting a liquid crystal display device.
2 is a cross-sectional view of a portion of one pixel region of an array substrate with a thin film transistor having a conventional oxide semiconductor layer.
3 is a plan view illustrating a device region in which a thin film transistor in one pixel region is formed and an edge thereof in an array substrate including a thin film transistor having an oxide semiconductor layer according to an exemplary embodiment of the present invention.
4 is a cross-sectional view of a portion cut along the cutting line IV-IV of FIG.
5 is a cross-sectional view of a portion of a pixel region of an array substrate according to a modification of the embodiment of the present invention.
6A to 6K are cross-sectional views of manufacturing steps of the portion cut along the cutting line IV-IV of FIG. 3;

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

3 is a plan view illustrating a device region in which a thin film transistor Tr in one pixel region P is formed and an edge thereof in an array substrate including a thin film transistor having an oxide semiconductor layer according to an exemplary embodiment of the present invention. .

As shown, the array substrate 101 according to the embodiment of the present invention is a lower portion and the upper portion of the array insulating film 101 as a base on a transparent insulating substrate 101 of a glass or plastic material between A plurality of gate lines 103 and data lines 130 defining a plurality of pixel regions P are formed by extending vertically and intersecting with each other.

In the pixel area P, the gate line 103 and the data line 130 intersect with each other and are connected to the gate line 103 and the data line 130 to form a thin film transistor Tr. It is.

In this case, in the drawing, the array substrate 101 shows an example of an array substrate for a liquid crystal display device, so that the thin film transistor Tr is connected to the gate wiring 103 and the data wiring 130 as an example. When the array substrate 101 constitutes an array substrate for an organic light emitting device, a switching thin film transistor, a driving thin film transistor, and an auxiliary thin film transistor for current compensation are provided in one pixel area, and a double switching thin film transistor is provided with the gate wiring. And the driving and auxiliary thin film transistors are not connected to the gate lines 103 and the data lines 130 but are internally connected to the electrodes or power lines of the switching or auxiliary thin film transistors.

The thin film transistor Tr may include a gate electrode 105, a gate insulating film (not shown), an oxide semiconductor layer 120, an etch stopper 123, and the oxide sequentially stacked on the substrate 101. The source electrode 133 and the drain electrode 136 are in contact with the semiconductor layer 120 and spaced apart from each other.

At this time, as one of the most characteristic configuration in the array substrate 101 according to an embodiment of the present invention, one end of the gate electrode 105 is connected and the other end is spaced apart at a predetermined interval (bar) ), That is, the planar structure is characterized by forming a fork (fork). For convenience of description, a plurality of bars arranged at regular intervals constituting the gate electrode 105 are referred to as gate fingers 105a, 105b, 105c, and 105d.

In the drawing, four gate fingers 105a, 105b, 105c, and 105d of the gate electrode 105 are formed as an example, but three or more may be formed.

In addition, as another characteristic configuration of the array substrate 101 according to the embodiment of the present invention, the etch stopper 123 is formed in a separated form corresponding to the gate electrode 105, and the source electrode 133 and The drain electrode 136 is also similar to the gate electrode 105 in the form of a fork (plank) fork (bar) finger (133a, 133b, 136a, 136b, 136c) in the form of a plurality of bars (angle) The gate fingers 105a, 105b, 105c, and 105d may be formed to be spaced apart from each other on the etch stopper.

In this case, the etch stopper is formed after the exposure process using the gate electrode 105 having the fork shape as the exposure mask without the exposure mask, so that the etch stopper is formed only corresponding to the gate fingers 105a, 105b, 105c, and 105d. And is not formed in a spaced area between the gate fingers 105a, 105b, 105c, and 105d.

These structural features will be described later in the description of the manufacturing method.

On the other hand, the thin film transistor having the configuration in which the gate electrode 105, the source electrode 133, and the drain electrode 136 as described above all have a plurality of fingers (133a, 133b, 136a, 136b, 136c). (Tr) is the source electrode 133 and the drain electrode 136 has at least two bars (bar) shape, respectively, left or right due to the patterning error when forming the source and drain electrodes 133, 136 Even if a shift occurs, the overlapping area of the source electrode 133 and the gate electrode 105 or the drain electrode 136 and the gate electrode 105 is always kept constant.

Therefore, the signal delay of the data line 130 due to the parasitic capacitance change between the source electrode 133 and the gate electrode 105 or between the drain electrode 136 and the gate electrode 105 when a shift occurs due to a patterning error or There is an effect of suppressing the occurrence of flicker and the like.

In the case of the conventional array substrate (71 of FIG. 2), referring to FIG. 2, one source electrode 81 and a drain electrode 83 are provided so that the source electrode 81 and the drain electrode 83 are changed due to a patterning error. Is shifted to the left, the overlapping area between the source electrode 81 and the gate electrode 73 becomes small, and the overlapping area between the drain electrode 83 and the gate electrode 73 increases.

In addition, when the source electrode 81 and the drain electrode 83 are shifted to the right, the overlapping area between the source electrode 81 and the gate electrode 73 increases and the gap between the drain electrode 83 and the gate electrode 73 is increased. The overlap area is reduced.

Therefore, in the case of the conventional array substrate, the display quality is reduced due to the overlapping area between the gate electrode 73 and the source electrode 81, the gate electrode 73 and the drain electrode 83 due to the patterning error. It can be seen that it works.

However, referring to FIG. 3, in the case of the array substrate 101 according to an exemplary embodiment of the present invention, even if the source electrode 133 and the drain electrode 136 are shifted in either the left or right direction, the source electrode 133 or the drain One of the fingers 133a, 133b, 136a, 136b, and 136c of the electrode 136 has an overlapped area with the gate electrode 105, but the other fingers 133a, 133b, 136a, and 136b 136c) has an overlapping area with the gate electrode 105, so that the overlapping area between the source electrode 133 and the gate electrode 105, the drain electrode 136, and the gate electrode 105 is always kept constant.

Accordingly, display quality degradation due to a change in parasitic capacitance due to the overlapping area of the source and drain electrodes 133 and 136 with the gate electrode 105 may be prevented.

On the other hand, a protective layer (not shown) is provided on the entire surface of the substrate 101 to cover the thin film transistor (Tr) having the above-described configuration.

The protective layer (not shown) is provided with a drain contact hole 143 exposing the drain electrode 136 of the thin film transistor Tr.

The drain contact hole 143 may be omitted when the thin film transistor Tr is an auxiliary thin film transistor for switching or current compensation provided in the pixel area of the organic light emitting diode.

The pixel electrode 150 is formed on the passivation layer by contacting the drain electrode 136 through the drain contact hole 143 for each pixel region P.

Next, a cross-sectional configuration of the array substrate 101 according to the embodiment of the present invention having the above-described planar configuration will be described.

4 is a cross-sectional view of a portion taken along the cutting line IV-IV of FIG. 3. In this case, for convenience of description, a portion in which the thin film transistor Tr is formed in each pixel region P is defined as an element region TrA.

As shown, the array substrate 101 according to an embodiment of the present invention is a low-resistance metallic material such as aluminum (Al) on a transparent insulating substrate 101, for example, glass or a plastic substrate having a flexible characteristic. ), Made of any one of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and molybdenum (MoTi) to have a single layer structure, or made of two or more materials to have a multi-layer structure and one direction Gate wiring (not shown) is formed to extend.

Each of the device regions TrA includes a plurality of gate fingers 105a formed of the same material constituting the gate line (not shown), branched from the gate line (not shown), or having a predetermined width and a spacing interval as a single type. The gate electrode 105 provided with 105b, 105c, and 105d is provided.

A gate insulating layer 110 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 over the gate wiring and the gate electrode 105. .

In addition, the gate insulating layer 110 is made of a low-resistance metal material, such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and molybdenum (MoTi) single A data line (not shown) having a layer structure or made of two or more materials and having a multi-layer structure and defining a pixel area P intersecting with the gate line (not shown) is provided.

On the other hand, in each device region TrA above the gate insulating layer 110, the gate electrode 105 more precisely overlaps the plurality of gate fingers 105a, 105b, 105c, and 105d and forms an island semiconductor material, for example, in an island form. An oxide semiconductor layer 120 made of any one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO) is provided.

In addition, in the device regions TrA, the gate semiconductors 105a, 105b, 105c, and 105d overlap the gate semiconductor layers 120a and 105d, and are spaced apart from the gate fingers 105a, 105b, 105c, and 105d. An etching stopper 123 having an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is provided with a spaced interval equal to the spaced distance.

The etch stopper 123 having such a configuration is characterized in that the number of gate fingers 105a, 105b, 105c, and 105d is formed in each device region TrA.

Further, although not illustrated, the etch stopper 123 overlaps the gate wiring (not shown) and is formed on the gate insulating layer 110.

 Therefore, the etch stopper 123 has the same configuration as the gate wiring (not shown) and the gate electrode 105 in a planar manner, and is formed to overlap completely.

Thus, the etch stopper 123 having the same planar shape as the gate electrode 105 and the gate wiring (not shown) is a back exposure using the gate electrode 105 and the gate wiring (not shown) as an exposure mask without an exposure mask. This is due to the fact that it was patterned by proceeding.

Next, a plurality of source and drain fingers 133a, 133b, 136a, 136b, and 136c are disposed on the oxide semiconductor layer 120 exposed between the etch stopper 123 and the etch stopper 123. The source electrode 133 and the drain electrode 136 are formed in contact with the oxide semiconductor layer 120 and spaced apart from each other.

More precisely, the plurality of source fingers 133a and 133b and the plurality of drain fingers 136a, 136b and 136c are spaced apart and alternately formed.

In this case, in the drawing, the source electrode 133 includes two source fingers 133a and 133b, and the drain electrode 136 includes three drain fingers 136a, 136b, and 136c. However, two or more source and drain fingers 133a, 133b, 136a, 136b, and 136c may be formed.

The source fingers 133a and 133b and the drain fingers 136a, 136b, and 136c having such a configuration face each other on the upper portions of the etch stoppers 123.

On the other hand, the gate electrode 105 having the plurality of gate fingers 105a, 105b, 105c, and 105d sequentially stacked in each device region TrA, the gate insulating film 110, the oxide semiconductor layer 120, , The etch stopper 123, the source electrode 133 having a plurality of source fingers 133a and 133b spaced apart from each other, and the drain electrode 136 having the plurality of drain fingers 136a, 136b, and 136c. A transistor Tr is formed.

Next, over the thin film transistor Tr and the data line (not shown), an organic insulating material such as photoacrylic or an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be used. Layer 140 is provided.

In this case, the protective layer 140 is provided with a drain contact hole 143 exposing the drain electrode 136 of the thin film transistor Tr.

The pixel electrode is formed on the passivation layer 140 by contacting the drain electrode 136 through the drain contact hole 143 for each pixel region.

The array substrate 101 according to the embodiment of the present invention having such a configuration suppresses the parasitic capacitance change due to the overlap of the gate electrode 105, the source electrode 133, and the drain electrode 136, thereby reducing the thin film transistor Tr. ), And further, the display quality deterioration caused by the parasitic capacitance change is suppressed.

Furthermore, since the size of the parasitic capacitance of each thin film transistor Tr itself is reduced, there is an effect of further suppressing the signal delay of the data line (not shown) and the display quality deterioration such as flicker due to the parasitic capacitance.

Table 1 shows an array substrate according to an embodiment of the present invention and a comparative example, in which the gate electrode 105 and the source electrode 133 are turned on in an on cap and an off cap in a conventional array substrate. The parasitic capacitance Cgs and the parasitic capacitance Cgd of the gate electrode 105 and the drain electrode 136 are measured. At this time, the unit of the parasitic capacitance is fF.

Parasitic capacity Mask exposure (comparative example (conventional)) Back Exposure (Example) Parasitic Capacity Reduction
(Reduction amount of the Example compared to the comparative example) Off-State Parasitic Capacity Cgd 127 98 22.8% ↓ 42.8% ↓
Cgs 275 131 52.4% ↓ On-state parasitic capacity Cgd 416 253 39.2% ↓ 39.0% ↓
Cgs 420 257 38.8% ↓

Referring to Table 1, in Comparative Examples and Examples, when each thin film transistor is turned off, the parasitic capacitances of the gate electrode and the drain electrode are 127fF and 98fF, respectively, and the parasitic capacitances of the gate electrode and the source electrode are 275fF and 131fF, respectively.

Therefore, when the thin film transistor is in the off state, it can be seen that the parasitic capacitance generated in the thin film transistor itself is about 42.8% lower than that of the comparative example.

In Comparative Examples and Examples, when each thin film transistor was in an on state, parasitic capacitances of the gate electrode and the drain electrode were 416fF and 253fF, respectively, and parasitic capacitances of the gate electrode and the source electrode were 420fF and 257fF, respectively. It can be seen that.

Therefore, when the thin film transistor is in the on state, the parasitic capacitance generated in the thin film transistor itself can be seen that the embodiment is reduced by about 39.0% compared to the comparative example.

On the other hand, as a modified example according to an embodiment of the present invention, Figure 5 (a cross-sectional view of a portion of the pixel region of the array substrate according to a modification of the embodiment of the present invention in the portion cut along the cutting line IV-IV shown in FIG. For example, the light blocking pattern 139 overlapping the thin film transistor Tr and blocking the penetration of light may be further provided in each device region TrA.

In this case, the light blocking pattern 139 may be formed of a red pigment representing a red color having the broadest wavelength band among the black organic material or visible light.

As such, the reason why the light blocking pattern 139 is provided on the thin film transistor Tr as in the array substrate 101 according to the modified example of the present invention is that the oxide semiconductor layer 120 is sensitive to light. This is to prevent the light from being irradiated onto the oxide semiconductor layer 120 because the thin film transistor Tr may cause a malfunction when the light is irradiated.

In the case of the array substrate 101 according to the modified example of the embodiment of the present invention, since the components other than the light shielding pattern 139 have the same configuration as the array substrate 101 according to the above-described embodiment, a detailed description thereof will be omitted. .

Hereinafter, a method of manufacturing the array substrate 101 according to the embodiment of the present invention having the above-described configuration will be described.

6A to 6K are cross-sectional views of manufacturing steps of a portion cut along the cutting line IV-IV of FIG. 3. In this case, for convenience of description, a portion where the thin film transistor Tr in each pixel region P is to be formed is defined as an element region TrA.

First, as shown in FIG. 6A, a low-resistance metal material such as copper (Cu), a copper alloy (AlNd), aluminum (eg, a transparent insulating substrate 101), for example, is formed on a substrate 101 made of glass or plastic. Al), aluminum alloy (AlNd), molybdenum (Mo), and molybdenum alloy (MoTi) by depositing one or two or more materials selected to form a first metal layer (not shown) having a single layer or double layer structure.

Thereafter, the first metal layer (not shown) is patterned by performing a mask process including a series of unit processes such as application of a photoresist, exposure using an exposure mask, development and etching of the exposed photoresist, and the pixel region P. A gate line (not shown) extending in one direction at a boundary of the gate, and at the same time, a gate having a plurality of gate fingers 105a, 105b, 105c, and 105d spaced at a predetermined width and a predetermined interval in each device region TrA. The electrode 105 is formed.

In this case, the plurality of gate fingers 105a, 105b, 105c, and 105d constituting the gate electrode 105 may be connected to one end thereof.

Next, as shown in FIG. 6B, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the gate wiring (not shown) and the gate electrode 105. 110).

Then, as shown in Figure 6c, by depositing any one of a cargo semiconductor material, for example, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium oxide (ZIO) on the gate insulating film 110 An oxide semiconductor material layer (not shown) is formed on the entire surface, and a mask process is performed to pattern the oxide semiconductor material layer, thereby patterning the island semiconductor oxide layer 120 corresponding to the gate electrode 105 in each device region TrA. To form.

In this case, the oxide semiconductor layer 120 is formed to cross the central portion of the gate fingers 105a, 105b, 105c, and 105d of the gate electrode 105, and thus the gate fingers 105a, 105b, 105c, and 105d. The overlapping areas and non-overlapping areas are alternated.

Next, as illustrated in FIG. 6D, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the island-type oxide semiconductor layer 120 to etch the entire surface of the substrate 101. A stopper material layer 122 is formed.

 Thereafter, as shown in FIG. 6E, the photoresist is coated on the entire surface of the etch stopper material layer 122 to form the photoresist layer 180.

In this case, the photoresist layer 180 is characterized in that it has a positive type photosensitive characteristic that the light-received portion is removed during later development.

Next, back exposure is performed on the substrate 101 on which the photoresist layer 180 is formed.

That is, by irradiating UV light on the entire surface of the substrate 101 from the outer surface of the substrate 101 where no component is formed without the exposure mask toward the inner surface where the gate electrode 105 is formed, the gate wiring ( All regions other than the portion of the photoresist layer 180 overlapping the gate electrode 105 are exposed to the UV light.

In the case of the back exposure, the gate wiring (not shown) made of a metal material and the gate electrode 105 may act as an exposure mask selectively blocking light.

Thereafter, as shown in FIG. 6F, the photoresist layer (180 of FIG. 6E) subjected to the back exposure is exposed to a developing solution to develop the etch stopper corresponding to the gate electrode 105 and the gate wiring (not shown). The first photoresist pattern 181 is formed on the material layer 122.

Since the photoresist layer (180 of FIG. 6E) has a positive characteristic, a portion irradiated with light, that is, UV light, is removed in response to the developer, and light is transmitted by the gate electrode 105 and the gate wiring (not shown). Is blocked so that only the part not exposed to UV light remains.

Next, as shown in FIG. 6G, the gate electrode 105 and the data line are removed by removing the etch stopper material layer 122 (FIG. 6F) exposed to the outside thereof using the first photoresist pattern 181. The etch stopper 123 is formed in correspondence with (not shown).

The etch stopper 123 is removed in the spaced area between the gate fingers 105a, 105b, 105c, and 105d in the gate electrode 105 and is formed only corresponding to the gate fingers 105a, 105b, 105c, and 105d. The number of gate fingers 105a, 105b, 105c, and 105d may be formed in each device region TrA.

The etch stopper 123 formed by this method does not require an alignment margin, etc., compared to the etch stopper (79 of FIG. 2) formed by using a general exposure mask, and thus has a relatively small area and is located at a more accurate position. Has the advantage of being formed.

Furthermore, since the separate exposure mask for forming the etch stopper 123 is not required, the manufacturing cost can be reduced by the cost of the expensive exposure mask.

Next, as shown in FIG. 6H, the etch stopper 123 is exposed by stripping the first photoresist pattern (181 of FIG. 6G) remaining on the etch stopper 123.

Next, as illustrated in FIG. 6I, a low resistance metal material such as copper (Cu), a copper alloy (AlNd), aluminum (Al), an aluminum alloy (AlNd), and molybdenum (Mo) is placed on the etch stopper 123. And forming a second metal layer (not shown) having a single layer or double layer structure by depositing one or more materials selected from the group consisting of molybdenum alloys (MoTi), and patterning the patterned layer on the gate insulating layer 110. A data line (not shown) defining the pixel area P may be formed to cross the gate line (not shown), and at the same time, each element area TrA may be spaced apart from each other above the etch stopper 123. The electrode 133 and the drain electrode 136 are formed.

At this time, the source electrode 133 and the drain electrode 136 is also made of a bar-shaped fingers (133a, 133b, 136a, 136b, 136c) having a predetermined width and spacing, respectively, The plurality of source fingers 133a and 133b and the plurality of drain fingers 136a, 136b, and 136c provided in the device region TrA each have one end connected to each other, and the source fingers 133a and 133b and the drain are connected. Fingers 136a, 136b, 136c are characterized in that they are formed so as to be spaced apart from each other and alternately.

In this case, each of the source fingers 133a and 133b and the drain fingers 136a, 136b, and 136c is disposed in a spaced area between the gate fingers 105a, 105b, 105c, and 105d to contact the oxide semiconductor layer 120. The source fingers 133a and 133b and the drain fingers 136a, 136b, and 136c which are adjacent to each other are formed to be spaced apart from each other and face each other on the etch stopper 123.

On the other hand, in this step, the gate electrode 105 having the plurality of gate fingers 105a, 105b, 105c, and 105d sequentially stacked on each device region TrA, the gate insulating film 110, and the oxide semiconductor layer A source electrode having a plurality of source fingers 133a and 133b spaced apart from each other and having an etch stopper 123 formed to correspond to the gate fingers 105a, 105b, 105c, and 105d and being spaced apart from each other. The drain electrode 136 having the plurality of drain fingers 136a, 136b, and 136c forms a thin film transistor Tr.

Next, as illustrated in FIG. 6J, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the data line (not shown) and the thin film transistor Tr on the front surface. The protective layer 140 is formed by coating an organic insulating material, for example, photoacrylic.

Thereafter, a mask process is performed on the protective layer 140 to form a drain contact hole 143 exposing the drain electrode 136.

Next, as shown in FIG. 6J, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the protective layer 140 to form a first transparent conductive material. By forming a layer (not shown) and patterning the same by performing a mask process, the pixel electrode 150 in contact with the drain electrode 136 through the drain contact hole 143 in each pixel region P is formed. By forming, the array substrate 101 according to the embodiment of the present invention is completed.

On the other hand, in the case of the array substrate 101 according to a modification of the embodiment of the present invention, referring to Figure 5, after forming the thin film transistor (Tr), before forming the protective layer 140, the thin film By applying a black organic material or a red pigment over the transistor Tr and patterning the same, a masking process is performed to form the light blocking pattern 139 on the thin film transistor Tr, and then the protective layer 140. And the pixel electrode 150 can be completed.

The array substrate 101 according to the embodiment of the present invention manufactured according to the aforementioned method is completed by a total of six mask processes including the thin film transistor Tr having the oxide semiconductor layer 120, but the etch stopper ( In the case of 123, the exposure mask cost can be reduced by performing the back exposure without the exposure mask, thereby reducing the manufacturing cost.

Furthermore, since the etch stopper 123 is formed by the back exposure without the exposure mask, alignment margins of the exposure mask are not required, and therefore, the etching stopper 123 may have a relatively small area compared to the exposure using the exposure mask.

Therefore, there is an effect of reducing the parasitic capacitance between the gate electrode 105 and the source and drain electrodes 133 and 136 due to the area of the etch stopper 123.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications can be made without departing from the spirit of the present invention.

101: substrate
103: gate wiring
105: gate electrode
105a, 105b, 105c, 105d: gate finger
120: oxide semiconductor layer
123: etch stopper
130: data wiring
133: source electrode
133a, 133b: source finger
136: drain electrode
136a, 136b, 136c: drain finger
143: drain contact hole
150 pixel electrode
Tr: Thin Film Transistor

Claims (9)

A gate electrode formed on a substrate having a plurality of pixel regions defined therein, the gate electrode having a plurality of gate fingers spaced apart from each other with a predetermined width and a distance therebetween;
A gate insulating film formed over the gate electrode over the substrate;
An oxide semiconductor layer formed in an island shape on the gate insulating layer to correspond to the gate fingers;
An etch stopper formed on the oxide semiconductor layer and the gate insulating layer and overlapping each of the plurality of gate fingers and having the same planar shape;
A source electrode having a plurality of source fingers spaced apart from each other and having a predetermined width on the oxide semiconductor layer exposed to the etch stopper and the spaced apart region thereof;
A drain electrode having a plurality of drain fingers alternate with the source finger and spaced apart from each other;
Array substrate comprising a.
The method of claim 1,
Each of the plurality of source and drain fingers is located in a spaced area between the gate fingers and contacts the oxide semiconductor layer, and the source and drain fingers adjacent to each other are spaced apart from each other on the etch stopper to face each other. Characteristic array substrate.
The method of claim 1,
A plurality of the gate fingers provided in each pixel area form a state in which one end thereof is all connected,
A plurality of the source fingers provided in each pixel area form a state in which one end thereof is all connected,
And a plurality of the drain fingers provided in the pixel regions form one end of each of the plurality of drain fingers.
The method of claim 1,
And at least two gate fingers, a plurality of source fingers, and a plurality of drain fingers formed in the pixel areas, respectively.
The method of claim 1,
A gate wiring extending in one direction is formed on the substrate,
A data line is formed on the gate insulating layer to cross the gate line to define the pixel area;
A protective layer is formed over the source electrode and the drain electrode to expose the drain electrode on the entire surface of the substrate.
And a pixel electrode in contact with the drain electrode in each pixel area over the passivation layer.
Forming a gate electrode having a plurality of gate fingers spaced apart from each other at a predetermined width and space on a substrate on which a plurality of pixel regions are defined;
Forming a gate insulating film over the gate electrode over the substrate;
Forming an oxide semiconductor layer having an island shape on the gate insulating layer to correspond to the gate fingers;
Forming an etch stopper over the oxide semiconductor layer and the gate insulating layer and overlapping each of the plurality of gate fingers and having the same planar shape;
A source electrode having a plurality of source fingers having a predetermined width and spaced apart from the etch stopper and the oxide semiconductor layer exposed to the spaced apart region thereof, and a plurality of drain fingers alternate with the source finger and having a predetermined width and spaced apart from each other; Forming one drain electrode
Method of manufacturing an array substrate comprising a.
The method of claim 6,
Forming the etch stopper over the oxide semiconductor layer and the gate insulating film and overlapping each of the plurality of gate fingers and having the same planar shape,
Forming an etch stopper material layer over the oxide semiconductor layer over the substrate;
Forming a photoresist layer having a positive photosensitive property on the entire surface of the substrate over the etch stopper material layer;
Irradiating UV light on the photoresist layer using a plurality of the gate fingers as an exposure mask on the rear surface of the substrate on which the photoresist layer is formed;
Developing the photoresist layer irradiated with the UV light to form a photoresist pattern completely overlapping the plurality of gate fingers;
Removing the etch stopper material layer exposed outside the photoresist pattern to form the etch stopper corresponding to each of the plurality of gate fingers;
Proceeding to strip the photoresist pattern
Method of manufacturing an array substrate comprising a.
The method of claim 6,
A plurality of the gate fingers provided in each pixel area so that one end thereof is all connected,
One end of each of the plurality of source fingers provided in the pixel areas is connected to each other.
And a plurality of the drain fingers provided in the pixel areas are formed so that one end thereof is connected to each other.
The method of claim 6,
Forming the gate electrode includes forming a gate wiring extending in one direction on the substrate,
The forming of the source electrode and the drain electrode includes forming a data line on the gate insulating layer to cross the gate line and define a data line to define the pixel area.
Forming a protective layer exposing the drain electrode on the entire surface of the substrate over the source electrode and the drain electrode;
Forming a pixel electrode in contact with the drain electrode in each pixel region over the passivation layer.

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