KR101803566B1 - Image display device and driving method thereof - Google Patents

Abstract

The image display apparatus according to the present invention includes a plurality of subpixels each having a main display unit, an auxiliary gate line, and an auxiliary display unit disposed between the main gate line and the data line and an auxiliary display unit disposed between the data lines, A display panel for displaying; A data voltage for image display is generated and supplied to the data line during a first output period within one horizontal period, and a charge sharing voltage for black display is generated to generate a second output A data driver for supplying the data line during a period; A gate driver for generating a main gate pulse to supply the main gate pulse to the main gate line and generating an auxiliary gate pulse to supply the auxiliary gate pulse to the auxiliary gate line; And a pattern reliader for dividing the light from the display panel into first and second polarized light beams; In the 2D mode for 2D image display, the main gate pulse and the assist gate pulse have the same phase and are generated so as to overlap in the first output period; In the 3D mode for 3D image display, the main gate pulse overlaps the first output period, and the auxiliary gate pulse has a phase different from that of the main gate pulse and is generated to overlap the second output period.

Description

TECHNICAL FIELD [0001] The present invention relates to a video display device and a driving method thereof.

The present invention relates to an image display apparatus and a driving method thereof that can selectively implement a two-dimensional plane image (hereinafter, referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').

Due to the development of various contents and circuit technology, the recent image display device can selectively implement the 2D image and the 3D image. The image display device implements a 3D image using a binocular stereoscopic technique or an autostereoscopic technique.

The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. In the spectacle method, left and right parallax images having different polarization directions are displayed on a display panel, and stereoscopic images are implemented using polarized glasses or liquid crystal shutter glasses.

In the liquid crystal shutter glasses system, a left-eye image and a right-eye image are alternately displayed on a display unit in frame units, and a left-eye and right-eye shutter of the liquid crystal shutter glasses is opened and closed in synchronization with the display timing. The liquid crystal shutter glasses open the left eye shutter only during the odd frame period in which the left eye image is displayed and only the right eye shutter is opened during the excellent frame period in which the right eye image is displayed to produce binocular parallax in a time division manner. In such a liquid crystal shutter glasses system, the data on time of the liquid crystal shutter glasses is short, and the brightness of the 3D image is low, and the 3D crosstalk is very likely to occur depending on the synchronization of the display element and the liquid crystal shutter glasses and on / off switching response characteristics.

The polarizing glasses system includes a patterned retarder 2 attached on the display panel 1 as shown in Fig. The polarizing glasses system alternately displays the left eye image data L and the right eye image data R on a horizontal line basis in the display panel 1 and displays the polarized light 3 incident on the polarized glasses 3 through the patterned retarder 1. [ Switch the characteristics. As a result, the polarizing glasses system can realize a 3D image by spatially dividing the left eye image and the right eye image.

In this polarizing glasses system, since the left eye image and the right eye image are displayed adjacent to each other in a line unit, the vertical viewing angle at which no crosstalk occurs is narrow. Crosstalk occurs when the left eye and right eye images are superimposed on each other at the upper and lower viewing angles. 2, a method of forming a black stripe (BS) on the pattern reliader 2 to widen the vertical angle of view of a 3D image has been proposed in Japanese Laid-Open Patent Publication No. 2002-185983. However, the black stripe (BS) used to improve the viewing angle causes a side effect which greatly reduces the luminance of the 2D image.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a polarizing glasses type image display apparatus and a method of driving the same, which can broaden the vertical viewing angle of a 3D image without lowering the brightness of the 2D image.

In order to achieve the above object, an image display apparatus according to an embodiment of the present invention includes a main display unit, an auxiliary gate line, and an auxiliary display unit disposed between the main gate line and the data line, A display panel for displaying a 2D image and a 3D image including pixels; A data voltage for image display is generated and supplied to the data line during a first output period within one horizontal period, and a charge sharing voltage for black display is generated to generate a second output A data driver for supplying the data line during a period; A gate driver for generating a main gate pulse to supply the main gate pulse to the main gate line and generating an auxiliary gate pulse to supply the auxiliary gate pulse to the auxiliary gate line; And a pattern reliader for dividing the light from the display panel into first and second polarized light beams; In the 2D mode for 2D image display, the main gate pulse and the assist gate pulse have the same phase and are generated so as to overlap in the first output period; In the 3D mode for 3D image display, the main gate pulse overlaps the first output period, and the auxiliary gate pulse has a phase different from that of the main gate pulse and is generated to overlap the second output period.

The image display apparatus and the driving method thereof according to the present invention divides and drives the subpixel into the main display unit and the sub display unit and displays the same 2D image in the main display unit and the sub display unit in the 2D mode, And a black image is displayed on the auxiliary display unit. Accordingly, the present invention can secure a wide viewing angle of the 3D image without lowering the luminance of the 2D image.

In particular, since the present invention utilizes the charge sharing voltage generated in the data driver, it is possible to easily implement a black image to be displayed on the auxiliary display unit without increasing the driving frequency of the data driver. According to the present invention, the 3D crosstalk can be reduced to 240 Hz while driving at 120 Hz.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
2 is a view for explaining a decrease in brightness of a 2D image due to a black stripe used for improving the viewing angle in the polarizing glasses system;
FIG. 3 and FIG. 4 are views showing a polarizing glasses type video display device according to an embodiment of the present invention. FIG.
Figure 5 schematically shows one subpixel disposed in a pixel array;
FIGS. 6 and 7 are views showing any one of the source ICs constituting the data driver. FIG.
8 is a diagram showing charge-sharing operation in a data driver;
9 is a view showing a gate driver;
10A is a view showing clock signals applied to the gate driver in the 2D mode and gate pulses outputted from the gate driver.
10B is a view showing clock signals applied to the gate driver in the 3D mode and gate pulses output from the gate driver.
11 is a view showing another example of gate start signals and clock signals applied to the gate driver in the 3D mode.
12A and 12B are diagrams showing display states of subpixels under the 2D mode and the 3D mode, respectively.
13 is a view showing a principle in which the vertical viewing angle becomes wider under the 3D mode.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 3 to 13. FIG.

FIG. 3 and FIG. 4 show a polarizing glasses type image display apparatus according to an embodiment of the present invention.

3 and 4, the image display apparatus includes a display device 10, a pattern drifting device 20, a control unit 30, a panel driving unit 40, and polarizing glasses 50.

The display device 10 may include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device, A flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED), and an electrophoresis (EPD) device. Hereinafter, the display element 10 will be described mainly with reference to a liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizing film 11a, and a lower polarizing film 11b.

The display panel 11 includes two glass substrates and a liquid crystal layer formed therebetween. The lower glass substrate of the display panel 11 is provided with a plurality of data lines DL and a plurality of gate line pairs PGL which intersect with the data lines DL. Each of the gate line pairs PGL consists of a main gate line GLa and an auxiliary gate line GLb. A plurality of unit pixels P each including a liquid crystal cell are arranged in a matrix form in the effective display area AA of the display panel 11 by the intersection structure of the signal lines DL and PGL, . Each of the unit pixels P includes a red subpixel, a green subpixel, and a blue subpixel. On the upper glass substrate of the display panel 11, a black matrix, a color filter, and a common electrode are formed.

The upper and lower polarizing films 11a and 11b are attached to the upper glass substrate and the lower glass substrate of the display panel 11 to form an alignment film for setting a pre-tilt angle of the liquid crystal. The common electrode to which the common voltage Vcom is supplied is formed on the upper glass substrate in a vertical electric field driving mode such as TN (Twisted Nematic) mode and VA (Vertical Alignment) Field switching mode) is formed on the lower glass substrate together with the pixel electrode. A column spacer for maintaining a cell gap of the liquid crystal cell may be formed between the glass substrates.

The display device 10 of the present invention can be implemented in any form such as a transmissive display device, a transflective display device, and a reflective display device. In the transmissive display element and the semi-transmissive display element, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

The patterned retarder 20 is attached to the upper polarizing film 11a of the display panel 11. [ A first retarder RT1 is formed on the odd number lines of the pattern reliader 20 and a second retarder RT2 is formed on the even lines of the pattern writer 20. [ The light absorption axis of the first retarder RT1 and the light absorption axis of the second retarder RT2 are orthogonal to each other. The first retarder RT1 of the patterned retarder 20 transmits the first polarized light (e.g., left circularly polarized light) of the light incident from the pixel array. The second retarder RT2 of the patterned retarder 20 transmits a second polarized light (e.g., right circularly polarized light) of light incident from the pixel array. The first retractor RT1 of the patterned retarder 20 can be realized as a polarizing filter transmitting the left circularly polarized light and the second retarder RT2 of the patterned retarder 20 can transmit the right circularly polarized light And can be implemented with a polarization filter.

The controller 30 controls the operation of the panel driver 40 in a 2D mode or a 3D mode according to a mode selection signal. The control unit 30 receives a mode selection signal through a user interface such as a touch screen, an on-screen display (OSD), a keyboard, a mouse, and a remote controller, Can be switched. The control unit 30 receives a 2D / 3D identification code, for example, an EPG (Electronic Program Guide) of a digital broadcast standard or an ESG (Electronic Service Guide) To distinguish the 2D mode from the 3D mode.

The controller 30 separates the RGB data of the 3D image input from the video source into the RGB data of the left eye image and the RGB data of the right eye image in the 3D mode and outputs the RGB data of the left eye image and the RGB data of the right eye image to one horizontal line To the data driver 40A of the panel driver 40 in turn. The control unit 30 supplies the RGB data of the 2D image input from the video source under the 2D mode to the data driver 40A of the panel driving unit 40. [

The control unit 30 controls the operation timing of the panel driving unit 40 using the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the dot clock DCLK, Lt; / RTI >

A data control signal for controlling the operation timing of the data driver 40A includes a source start pulse (SSP), a rising start signal A source sampling clock (SSC) for controlling the latch operation of the data on the basis of the falling edge of the data, a source output enable signal SOE for controlling the output of the data driver 40A, And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells of the liquid crystal cells 11,

The gate control signal for controlling the operation timing of the gate driver 40B includes a gate start pulse (GSP) indicating a start horizontal line from which a scan starts in one vertical period in which one screen is displayed, a gate driver 40B A gate shift clock signal GSC for sequentially shifting the gate start pulse GSP and a gate output enable signal Gate OUT for controlling the output of the gate driver 40B, Enable: GOE). The gate start pulse GSP includes a first gate start signal VSTA and a second gate start signal VSTB. The gate shift clock signal GSC includes a first group of clock signals CLKA and a second group of clock signals CLKB.

The control unit 30 multiplies the timing signals (Vsync, Hsync, DE, DCLK) synchronized with the input frame frequency to generate a frame signal having a frame frequency of Nxf (where N is a positive integer of 2 or more and f is an input frame frequency) The operation of the driving unit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The panel driver 40 includes a data driver 40A for driving the data lines DL of the display panel 11 and a gate driver 40B for driving the gate line pairs PGL of the display panel 11 ).

The data driver 40A latches the RGB data of the 2D / 3D image according to the data control signals SSP, SSC and SOE. The data driver 40A converts the RGB data of the 2D / 3D image into an analog positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal POL to reverse the polarity of the data voltage. The data driver 40A short-circuits the channels from which the positive data voltages are output and the channels from which the negative data voltages are output to generate the charge sharing voltage of the black gradation level. The data driver 40A supplies the data voltage for 2D / 3D image display to the data line DL during a first output period within one horizontal period, and supplies the charge-sharing voltage for black display to the data line DL within a horizontal period And supplies the data to the data line DL during the second output period excluding the first output period. The source drive ICs of the data driver 40A can be bonded to the lower glass substrate of the display panel 11 by a TAB (Tape Automated Bonding) process.

The gate driver 40B includes a shift register array and the like. The shift register array of the gate driver 40B may be formed in the GIP (Gate In Panel) method in the non-display area NA outside the effective display area AA where the pixel array is formed in the display panel 11. [ With the GIP scheme, the gate shift registers are formed together with the pixel array in the TFT process of the pixel array.

The gate driver 40B drives the gate line pairs PGL in accordance with the gate control signal. The gate driver 40B generates a main gate pulse based on the first group of clock signals CLKA and supplies the main gate pulse to the main gate line GLa and generates the auxiliary gate pulse based on the clock signal CLKB of the second group And supplies it to the auxiliary gate line GLb. In the 2D mode, the main gate pulse and the assist gate pulse are generated so as to have the same phase with each other, and are generated so as to overlap in the first output period in which the data voltage is output. In the 3D mode, the main gate pulse and the auxiliary gate pulse are generated so as to have different phases, the main gate pulse is generated so as to overlap the first output period in which the data voltage is output, 2 output period.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter (or a first polarization filter) and a right eye 50R having a right eye polarization filter (or a second polarization filter). The left eye polarizing filter has the same optical absorption axis as the first retarder RT1 of the patterned retarder 20 and the right eye polarizing filter has the same optical absorption axis as the second retarder RT2 of the patterned retarder 20 I have. For example, the left eye polarizing filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarizing filter of the polarizing glasses 50 may be selected as a right circular polarization filter. The user can view the 3D image data displayed on the display device 10 in a space division manner through the polarized glasses 50. [

FIG. 5 schematically shows one of the red, green and blue subpixels SP arranged in the intersection area 1, 1 of the data line DL and the gate line pair PGL in the pixel array.

The subpixel SP includes a main display portion SP1 and an auxiliary display portion SP2 disposed on both sides of the gate line pair PGL.

The main display unit SP1 is disposed between the main gate line GLa and the data line DL and is connected to the main gate line GLa and the data line DL through the first switch TFT1. The first switch TFT1 is turned on when the main gate line GLa is activated by the main gate pulse VOUTA to thereby electrically connect the main display portion SP1 to the data line DL.

The auxiliary display portion SP2 is disposed between the auxiliary gate line GLb and the data line DL and is connected to the auxiliary gate line GLb and the data line DL through the second switch TFT2. The second switch TFT2 is turned on when the auxiliary gate line GLb is activated by the assist gate pulse VOUTB to thereby electrically connect the auxiliary display portion SP2 to the data line DL.

6 and 7 show details of any one of the source ICs constituting the data driver 40A. 8 shows the charge-sharing operation in the data driver 40A.

6 and 7, the source IC of the data driver 40A includes a shift unit 121, a first latch array 122, a second latch array 123, a gamma compensation voltage generation unit 124, a digital (DAC) 125, an output circuit 126, and a charge share circuit 127. The DAC 125 includes an input /

The shift unit 121 shifts the sampling signal according to the source sampling clock SSC. In addition, the shift section 121 generates the carry signal CAR when data exceeding the number of latches of the first latch array 122 is supplied.

The first latch array 122 samples the digital video data RGB from the timing controller 11 in response to a sampling signal sequentially input from the shift unit 121 and outputs the data RGB in one horizontal Latches the data in units of lines, and simultaneously outputs data for one horizontal line.

The second latch array 123 latches one horizontal line of data input from the first latch array 122 and then latches the data of the second latch array 122 of the other source ICs during the low logic period of the source output enable signal SOE. And outputs the latched digital video data RGB.

The gamma compensation voltage generator 124 further divides the plurality of gamma reference voltages by the number of gradations that can be represented by the number of bits of the digital video data RGB to generate positive gamma compensation voltages VGH and VGH corresponding to the respective gradations, To generate polarity gamma compensation voltages (VGL).

The DAC 125 includes a P-decoder to which a positive gamma compensation voltage VGH is supplied, an N-decoder to which a negative gamma compensation voltage VGL is supplied, an output of the P-decoder in response to the polarity control signals POL, And a multiplexer for selecting an output of the N-decoder. The P-decoder decodes the digital video data RGB input from the second latch array 123 and outputs a positive gamma compensation voltage VGH corresponding to the gray level of the data, Decodes the digital video data RGB inputted from the latch array 123 and outputs a negative gamma compensation voltage VGL corresponding to the gray level value of the data. The multiplexer selects the positive gamma compensation voltage VGH and the negative gamma compensation voltage VGL in response to the polarity control signal POL.

The output circuit 126 includes a plurality of buffers BUF connected one-to-one to the output channels CH1 to CHn as shown in FIG. 6 to minimize signal attenuation of the analog data voltage supplied from the DAC 125. FIG.

The charge share circuit 127 includes a plurality of first switches SW1 connected between adjacent output channels CH1 through CHn, a plurality of second switches connected between the output terminal of the buffer BUF and the output channel, (SW2), and a plurality of inverters (INV) for inverting the source output enable signal (SOE).

During the first output period T1 in which the source output enable signal SOE is held at the low logic L within one horizontal period 1H as shown in FIG. 7, the first switches SW1 are turned off, 2 switches SW2 are turned on. During this first output period T1, the charge share circuit 127 bypasses the data voltage Vdata input from the output circuit 126 to the output channels CH1 to CHn.

On the other hand, during the second output period T2 during which the source output enable signal SOE is held at the high logic H within one horizontal period 1H, the first switches SW1 are turned on, The switches SW2 are turned off. During the second output period T2, the charge sharing circuit 127 outputs the positive (+) data voltage (Vdata) and the negative data voltage (Vdata) Generates a charge sharing voltage, and applies the charge sharing voltage to all the data lines in common. The charge sharing voltage has substantially the same level as the common voltage Vcom capable of implementing the black gradation.

9 shows a gate driver 40B according to an embodiment of the present invention. The gate driver 40B of FIG. 9 is an example for implementing a vertical resolution of '1080'.

9, the gate driver 13 includes a plurality of main drivers GDA [1] to GDA [1080] for driving the main gate lines GLa of the display panel 11, And a plurality of auxiliary drivers GDB [1] to GDB [1080] for driving the auxiliary gate lines GLb.

The main drivers GDA [1] to GDA [1080] are turned on in response to the first gate start signal VSTA and the first group of clock signals CLKA, ]). The first group of clock signals CLKA is composed of first to fourth clock signals CLK [1] to CLK [4]. The main gate pulses VOUTA [1] to VOUTA [1080] are supplied to the main gate lines GLa of the display panel 11 in a line sequential manner. For this, the first to fourth clock signals CLK [1] to CLK [4] have a pulse width of 2 horizontal periods (2H), and the phases of neighboring clock signals are sequentially ≪ / RTI >

The auxiliary drivers GDB [1] to GDB [1080] supply the auxiliary gate pulses VOUTB [1] to VOUTB [1080] in response to the second gate start signal VSTB and the second group of clock signals CLKB, ]). The clock signals CLKB of the second group are composed of the fifth to eighth clock signals CLK [5] to CLK [8]. The auxiliary gate pulses VOUTB [1] to VOUTB [1080] are supplied to the auxiliary gate lines GLb of the display panel 11 in a line-sequential manner. For this purpose, the fifth to eighth clock signals CLK [5] to CLK [8] have a pulse width of two horizontal periods (2H), and the phases of neighboring clock signals are sequentially ≪ / RTI >

10A and 10B show the clock signals applied to the gate driver and the gate pulses outputted from the gate driver in the 2D mode and the 3D mode, respectively. 11 shows another example of the gate start signal and the clock signals applied to the gate driver in the 3D mode.

10A, in the 2D mode, the main gate pulses VOUTA [1] to VOUTA [1080] and the assist gate pulses VOUTB [1] to VOUTB [1080] are generated in the same phase with each other, Is generated so as to overlap the first output period T1 (see Fig. 7) in which the voltages D1, D2, D3, ... are outputted. To this end, the first and second gate start signals VSTA and VSTB are input to the gate driver 14B in phase with each other. The first group of clock signals CLKA is input to the gate driver 14B in phase with each of the second group of clock signals CLKB. The first clock signal CLK1 is the fifth clock signal CLK5, the second clock signal CLK2 is the sixth clock signal CLK6 and the third clock signal CLK3 is the seventh clock signal CLK7 And the fourth clock signal CLK4 have the same phase as the eighth clock signal CLK8, respectively.

10B, in the 3D mode, the main gate pulses VOUTA [1] to VOUTA [1080] and the assist gate pulses VOUTB [1] to VOUTB [1080] are generated in different phases, The gate pulses VOUTA [1] to VOUTA [1080] are generated so as to overlap the first output period T1 (see Fig. 7) in which the data voltages D1, D2, D3, The pulses VOUTB [1] to VOUTB [1080] are generated so as to overlap the second output period T2 (see Fig. 7) in which the charge sharing voltages B1, B2, ... are output. To this end, the second gate-start signal VSTB is input to the gate driver 14B in a phase that is faster than the first gate-start signal VSTA by a half horizontal period H / 2. Each of the second group of clock signals CLKB is input to the gate driver 14B in a phase that is 1/2 the horizontal period H / 2 compared to the first group of clock signals CLKA. The phase of the fifth clock signal CLK5 is faster than the first clock signal CLK1 by a half horizontal period H / 2 and the phase of the sixth clock signal CLK6 is higher than the second clock signal CLK2 by 1 / 2 horizontal period H / 2, the seventh clock signal CLK7 is faster than the third clock signal CLK3 by a 1/2 horizontal period H / 2, and the eighth clock signal CLK8 is (H / 2) as compared with the fourth clock signal CLK4.

11, in the 3D mode, the second gate start signal VSTB is input to the gate driver 14B in a phase delayed by 1/2 horizontal period (H / 2) as compared with the first gate start signal VSTA . Further, each of the second group of clock signals CLKB may be input to the gate driver 14B in a phase that is later than the first group of clock signals CLKA by a half horizontal period (H / 2) .

12A and 12B show display states of subpixels under the 2D mode and the 3D mode, respectively. 13 shows the principle of widening the vertical viewing angle under the 3D mode.

The display states of the sub-pixels SP in the 2D mode and the 3D mode in conjunction with FIGS. 5 to 11 will now be described.

The first and second switches TFT1 and TFT2 of the sub pixel SP are turned on by the main gate pulse VOUTA and the auxiliary gate pulse VOUTB of the same phase in the 2D mode, And the auxiliary display unit SP2 to the data line DL at the same time. The period during which the first and second switches TFT1 and TFT2 are turned on is overlapped with the first output period T1 during which the 2D data voltage is output to the data line DL, Receive the same 2D data voltage from the data line DL. Therefore, the same 2D image is implemented on the main display unit SP1 and the auxiliary display unit SP2 as shown in FIG. 12A. The auxiliary display unit SP2 displays the same 2D image as the main display unit SP1 to increase the display luminance of the 2D image.

In the 3D mode, the first and second switches TFT1 and TFT2 of the subpixel SP are connected to the main gate pulse VOUTA and the auxiliary gate pulse VOUTB having a phase difference of 1/2 horizontal period (H / 2) The timing at which the main display unit SP1 is connected to the data line DL and the timing at which the auxiliary display unit SP2 is connected to the data line DL are made different from each other. The timing at which the second switch TFT2 is turned on is earlier than the timing at which the first switch TFT1 is turned on as fast as the 1/2 horizontal period H / 2 as shown in Fig. 10B, 2 < / RTI > horizontal period (H / 2). The main display unit SP1 receives the 3D data voltage DL from the data line DL since the 3D data voltage is overlapped with the first output period T1 during which the first switch TFT1 is turned on, . The auxiliary display unit SP2 receives the charge sharing voltage Vout from the data line DL since the charge sharing voltage is overlapped with the second output period T2 during which the second switch TFT2 is turned on, . Accordingly, as shown in FIG. 12B, a 3D image is implemented in the main display unit SP1, and a black image is implemented in the auxiliary display unit SP2. The auxiliary display unit SP2 displays a black image to widen the display interval between vertically adjacent 3D images.

13, when the left-eye image L and the right-eye image R are alternately displayed on a line-by-line basis in the pixel array, the black image displayed on the sub display unit SP2 is vertically neighboring 3D images L, and R, respectively. Accordingly, a 3D vertical viewing angle in which crosstalk does not occur without a separate black stripe pattern can be ensured widely through the black image.

As described above, in the image display apparatus and the driving method thereof according to the present invention, the sub pixels are divided and driven by the main display unit and the sub display unit, and the same 2D image is displayed in the main display unit and the sub display unit in the 2D mode, A 3D image is displayed on the main display unit and a black image is displayed on the auxiliary display unit. Accordingly, the present invention can secure a wide viewing angle of the 3D image without lowering the luminance of the 2D image.

In particular, since the present invention utilizes the charge sharing voltage generated in the data driver, it is possible to easily implement a black image to be displayed on the auxiliary display unit without increasing the driving frequency of the data driver. According to the present invention, the 3D crosstalk can be reduced to 240 Hz while driving at 120 Hz.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display element 11: display panel
20: pattern-driven retarder 30: control unit
40: panel driver 40A: data driver
40B: gate driver 50: polarizing glasses

Claims (13)

A display panel including a plurality of subpixels each having a main display part arranged between a main gate line and a data line, an auxiliary gate line and an auxiliary display part arranged between the data lines, to display a 2D image and a 3D image;
A data voltage for image display is generated and supplied to the data line during a first output period within one horizontal period, and a charge sharing voltage for black display is generated to generate a second output A data driver for supplying the data line during a period;
A main driver for generating and supplying a main gate pulse having a pulse width of two horizontal periods based on a first group of clock signals having a pulse width of two horizontal periods and supplying the main gate pulse to the main gate line, A gate driver including an auxiliary driver for generating an auxiliary gate pulse having a pulse width of two horizontal periods based on a clock signal of the first group and supplying the auxiliary gate pulse to the auxiliary gate line; And
And a patterned retarder for dividing the light from the display panel into lights of a first polarization and a second polarization;
In the 2D mode for 2D image display, the same 2D data voltage for displaying the 2D image is applied to the main display unit and the auxiliary display unit, and the first group of clock signals and the second group of clock signals are in the same phase. Wherein the main gate pulse and the auxiliary gate pulse are supplied to the gate driver so that they have the same phase and overlap with each other in the first output period;
In the 3D mode for displaying the 3D image, a 3D data voltage for displaying the 3D image is applied to the main display unit, the charge sharing voltage for the black display is applied to the auxiliary display unit, And the second group of clock signals are supplied to the gate driver with a phase difference of a half horizontal period so that the main gate pulse overlaps the first output period and the auxiliary gate pulse has a phase different from the main gate pulse And is generated so as to overlap with the second output period. delete delete delete delete The method according to claim 1,
The first output period indicating a period during which the source output enable signal is held at the first logic;
And the second output period indicates a period during which the source output enable signal is maintained in the second logic. The method according to claim 6,
The data driver includes:
And a charge sharing circuit having a first switch for switching the output of the data voltage in response to the source output enable signal and a second switch for switching the output of the charge sharing voltage in response to the source output enable signal and;
Wherein the second switch is connected between the output channels and is operated in reverse to the first switch. 1. A driving method of a video display device having a display panel for displaying a 2D image and a 3D image and a patterned retarder for dividing light from the display panel into lights of first polarization and second polarization,
Providing a plurality of subpixels in the display panel, each subpixel having a main display portion disposed between a main gate line and a data line, an auxiliary gate line, and an auxiliary display portion disposed between the data lines;
A data voltage for image display is generated and supplied to the data line during a first output period within one horizontal period, and a charge sharing voltage for black display is generated to generate a second output Supplying the data line to the data line during a period; And
A main gate pulse having a pulse width of two horizontal periods based on a first group of clock signals having a pulse width of two horizontal periods is generated and supplied to the main gate line, Generating a sub-gate pulse having a pulse width of two horizontal periods based on the clock signal of the sub-gate line and supplying it to the sub-gate line;
In the 2D mode for 2D image display, the same 2D data voltage for displaying the 2D image is applied to the main display unit and the auxiliary display unit, and the first group of clock signals and the second group of clock signals have the same phase, Wherein the main gate pulse and the auxiliary gate pulse have the same phase and are generated so as to overlap with each other in the first output period,
In the 3D mode for displaying the 3D image, a 3D data voltage for displaying the 3D image is applied to the main display unit, the charge sharing voltage for the black display is applied to the auxiliary display unit, And the second group of clock signals are supplied to the gate driver with a phase difference of a half horizontal period so that the main gate pulse overlaps the first output period and the auxiliary gate pulse has a phase different from the main gate pulse And is generated so as to overlap the second output period. delete delete delete 9. The method of claim 8,
The first output period indicating a period during which the source output enable signal is held at the first logic;
Wherein the second output period indicates a period during which the source output enable signal is held in the second logic. 13. The method of claim 12,
Wherein the charge sharing voltage is generated through a short circuit between a channel from which the positive data voltage is output and a channel from which the negative data voltage is output when the source output enable signal is held at the second logic. Driving method.

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