KR101763254B1 - Dram security erase - Google Patents

Abstract

The memory includes a DRAM array and a sense amplifier including a memory cell, a word line, and a bit line coupled to the memory cell. The memory is configured to perform a method in which a word line of the DRAM array is set to an active state. While the word line is active, the signal on each bit line increases with the charge flowing between the memory cell to which the word line is connected and the respective bit line. A sense amplifier is connected to each bit line and remains inactive to not amplify the signal to a storable signal level. When the word line is again set to the inactive state, insufficient charge remains in the memory cell, and the data stored in the memory cell connected to the word line is erased. This method is repeatedly executed using each of the remaining word lines in the selected range of the DRAM array to erase the data stored in the selected range.

Description

DRAM security clearance {DRAM SECURITY ERASE}

The present disclosure relates to a dynamic random access memory ("DRAM"), a DRAM typically included in a particular DRAM chip, or included as a DRAM macro functional unit in another type of chip that further includes a sufficient amount of logic circuitry . More particularly, the present invention relates to a method of erasing data stored in a DRAM.

BACKGROUND OF THE INVENTION Microelectronic devices, such as semiconductor chips, are thin, flat devices including active semiconductor devices such as transistors, diodes, and integrated circuits including wires that provide electrical interconnection. The semiconductor chip may further include a passive device such as a capacitor, an inductor, or a resistive element, or the passive device may be included in place of the other. In certain configurations, a microelectronic device can include one or more semiconductor chips, which include an electrically conductive element that includes a sealant on one or more surfaces and is electrically connected to the contacts of one or more semiconductor chips , Which is exposed on the surface of the microelectronic device. In some cases, the microelectronic component may be a fan-out wafer level microelectronic unit comprising one or more semiconductor chips, at least the edge of which is covered by the sealant and electrically conductive The traces extend beyond the edges of one or more chips along the surface of the one or more chips to the surface of the seal.

The semiconductor chip includes dynamic random access memory (hereinafter referred to as "DRAM chip" or "DRAM") including a memory storage array and circuitry to write data to the storage array and read the stored data. In typical conventional DRAM operation, data is written to or read from the memory cells of the storage array in a manner that stores a high voltage or a low voltage on the storage capacitors of each memory cell. A high voltage typically represents a "1" stored in a binary data format, and a low voltage typically represents a stored "0 ". DRAM is a volatile memory that holds data stored in a storage capacitor as long as the DRAM has power, and is refreshed at each requested interval. When power is removed from the DRAM, the refresh is no longer performed and the voltage level stored in the storage capacitor begins to decrease. However, the data stored in the storage capacitor does not immediately disappear. To ensure that the data stored in the DRAM is erased, the DRAM must remain powered off for a few minutes.

In a typical computing system, such as a desktop, laptop, tablet computer, and smart phone, one or more DRAM chips are used to provide active system memory, which includes sound and display processes and application programs (& (For example, a myriad of built-in application programs and user-selectable add-on application programs for Internet access, media or music access, word processing, database access, presentation, ) To enable active system operation. For security purposes, data stored in a non-volatile disk drive or a solid-state memory drive of a computing system may be encrypted. However, data used in the active operation of the computing system, such as data stored in active system memory, is not encrypted.

Because of the way the DRAM chip operates, the data in the active system memory will last for several minutes after the power of the computing system is turned off. Thus, if the computing system of the laptop or smartphone is left powered off, then left behind, or if someone else is present, such as when the user goes past an airport search, There is a risk of accessing critical data that is still in system memory and obtaining this data.

Therefore, it is desirable to quickly erase the data stored in the DRAM chip. This can prevent data from being stolen from the active system memory of the computing system. However, conventional DRAM chips do not provide a reliable method of rapidly erasing data. When data needs to be erased, a typical DRAM chip employs conventional write operations that overwrite data already stored at high or low voltages or high and low voltages in some patterns. As a result, in order to erase data from the entire DRAM chip, it takes a lot of time and resources to perform recording of data filling the entire DRAM chip.

Methods for erasing data from a DRAM chip are disclosed in U.S. Patent Nos. 7,751,263; U.S. Patent 7,164,611; U.S. Patent 5,255,223; U.S. Patent 4,873,672; U.S. Published Patent Application 2009/0016133; And Korean Patent Publication No. 2009-0105093.

A method is provided for erasing data stored in a dynamic random access memory (DRAM) array according to an aspect of the present invention. This method sets the word line of the DRAM array to an active state so that the word line is connected between the memory cell to which the word line is connected and each bit line according to the data stored in the memory cell to which the word line is connected Causing charge to flow, causing a charge to flow, the signal on each bit line increasing with the charge flowing between the memory cell and the bit line to which the word line is connected; And a sense amplifier connected to each of the bit lines while keeping a sense amplifier connected to each bit line in an inactive state so that a sense amplifier connected to each bit line does not amplify the signal to a storable signal level, And erasing data stored in the memory cell connected to the word line by setting the word line to an inactive state such that insufficient charge is maintained in the word line. The above steps are repeatedly executed using each of the remaining word lines in the selected range of the DRAM array to erase the data stored in the selected range.

In one embodiment, the selected range may be the entirety of the DRAM array, thus erasing the data stored throughout the DRAM array. Alternatively, the selected range may be less than the total of the DRAM array. The selected range may be continuous or non-continuous. For example, a word line may be selected for every two word lines, for every three word lines, or for every four word lines, to erase the data stored in the memory cells connected to the selected word line. At this time, the data stored in the memory cell connected to the word line between the selected word lines is not erased, but data is erased only within a specific address range. In another embodiment, three word lines are selected for every three word lanes and data stored in the memory cells connected to the three word lines is erased, so that the data of the memory cells connected to the unselected word lines for every four word lines is It is not erased.

In one embodiment, setting the word line to the active state includes selecting the word line using an address counter. The address counter may be a refresh address counter.

The method may further include precharging the bit line to a first voltage level prior to the step of setting the word line to an active state. In one embodiment, the first voltage level is an intermediate level between a high signal voltage level and a low signal voltage level, respectively, representing "1" and "0" stored in the memory cell connected to the word line. In one embodiment, precharging the bit line is performed by setting a precharge device connected to the bit line to an active state. In this case, the method may include maintaining the precharge device coupled to the bit line inactive while the sense amplifier remains inactive, and setting the selected word line back to the inactive state.

In one embodiment, the data storage element comprises a capacitor.

A method for erasing data stored in a dynamic random access memory (DRAM) array according to another aspect of the present invention is provided. The method includes maintaining a precharge device coupled to a bit line of the DRAM array in an active state to maintain the bit line at one or more predetermined voltage levels while setting the word line of the DRAM array to an active state, Wherein the voltage of the memory cell is charged to the at least one predetermined voltage level, regardless of the data stored in the associated memory cell, and maintaining the sense amplifier connected to the bit line in an inactive state, And setting the word line to an inactive state to store the charge in accordance with the voltage level, thereby erasing the data stored in the memory cell. The above steps are repeatedly performed using each of the remaining word lines in the selected range of the DRAM array to erase the data stored in the selected range.

In one embodiment, the selected range may be the entirety of the DRAM array, thus erasing the data stored throughout the DRAM array. Alternatively, the selected range may be less than the total of the DRAM array.

In one embodiment, setting the word line to an active state includes selecting the word line using an address counter. The address counter may be a refresh address counter.

The predetermined voltage level may be one predetermined voltage level for precharging all the bit lines. In another embodiment, some of the bit lines are precharged to one predetermined voltage level and the other bit lines are precharged to another predetermined voltage level. In one embodiment, the predetermined voltage level corresponds to a reference voltage level. The predetermined voltage level may be a reference voltage level such as ground or another reference voltage level used in the integrated circuit in which the memory is provided. In another embodiment, the predetermined voltage level may be an intermediate level substantially equal to the average value of the supply voltage level and the reference voltage level, or may be an intermediate voltage level corresponding to an average of the supply voltage level and the reference voltage level.

In one embodiment, the data storage element comprises a capacitor.

According to another aspect of the present invention there is provided a memory comprising a dynamic random access memory (DRAM) array. A memory array comprising a memory cell, a word line, and a bit line coupled to the memory cell; And a sense amplifier. The memory sets the word line of the DRAM array to an active state so that charge flows between the bit line and the memory cell to which the word line is connected according to data stored in the memory cell to which the word line is connected Causing a charge to flow, the signal on each bit line increasing with the charge flowing between the memory cell and the bit line to which the word line is connected; And a sense amplifier connected to each of the bit lines while keeping a sense amplifier connected to each bit line in an inactive state so that a sense amplifier connected to each bit line does not amplify the signal to a storable signal level, And erasing the data stored in the memory cell connected to the word line by setting the word line to an inactive state such that insufficient charge is maintained in the word line. Thus, a memory cell coupled to a word line in an active state stores charge corresponding to one or more predetermined voltage levels pre-charged in the bit line instead of the previously stored voltage level. The above-described steps are repeated using each of the remaining word lines in the selected range of the DRAM array to erase the data stored in the selected range.

In one embodiment, the selected range may be the entirety of the DRAM array, thus erasing the data stored throughout the DRAM array. Alternatively, the selected range may be less than the total of the DRAM array.

In one embodiment, setting the word line to an active state includes selecting the word line using an address counter. The address counter may be a refresh address counter.

The predetermined voltage level may be one predetermined voltage level for precharging all the bit lines. In another embodiment, some of the bit lines are precharged to a first predetermined voltage level and the other bit lines are precharged to a second predetermined voltage level different from the first predetermined voltage level. In one embodiment, the predetermined voltage level corresponds to a reference voltage level. The predetermined voltage level may be a reference voltage level such as ground, or may be another reference voltage level used in the integrated circuit in which the memory is provided. In another embodiment, the predetermined voltage level may be an intermediate level substantially equal to the average value of the supply voltage level and the reference voltage level, or may be an intermediate voltage level corresponding to an average of the supply voltage level and the reference voltage level.

In one embodiment, the data storage element comprises a capacitor.

A system according to one aspect of the invention includes a chip (e.g., a semiconductor chip including a memory according to one aspect of the invention described above) and one or more electrical components electrically coupled to the chip. The system may further include a housing, and the chip and the electrical component may be mounted on the housing.

1 is a schematic block diagram and circuit diagram illustrating a circuit structure of a dynamic random access memory (DRAM) according to one embodiment of the present disclosure.
2 is a timing diagram illustrating a conventional DRAM operation.
3 is a timing diagram illustrating DRAM operation in a data erase method according to one embodiment of the present application.
4 is a timing diagram illustrating DRAM operation in a data erase method according to an embodiment of the present invention.
5 is a time flow diagram illustrating DRAM operation in a data erase method according to an embodiment of the present invention.
6 is a block diagram illustrating a functional structure of a DRAM macro functional unit of a DRAM chip or chip according to an embodiment of the present invention.
7 illustrates a structure of a system including a DRAM chip or a chip including a DRAM macro according to an embodiment of the present invention.

1 illustrates the structure of a general memory 102 that includes a dynamic random access memory ("DRAM") array 100. [ The memory is typically contained in a semiconductor chip and becomes a "DRAM chip" having a main function of providing a DRAM storage array. Alternatively, the memory may be a DRAM macro, which is a functional unit included in the chip, wherein the chip containing the memory also includes other functional circuitry, such as a logic circuit included in the same semiconductor chip. 1, a memory cell 101 of a DRAM array 100 includes a transistor 102 and a data storage element 104. The transistor may be, for example, a metal oxide semiconductor field effect transistor (MOSFET), and is generally an n-type MOSFET (n-type MOSFET). The data storage element 104 is typically a capacitor which is coupled to a first plate ("cell node") coupled to the source of the NFET and to a second plate .

The DRAM array has bitlines BL <0>, / BL <0>, BL <1>, / BL <1> extending in a first direction across the array. The bit lines are connected to the electrodes, or drains, of the NFET transistors of the memory cells, which are opposite to the source electrodes to which the capacitors 104 are connected. The word lines WL <0>, WL <1>, WL <2>, WL <3> extend in a second direction across the first direction. In the DRAM array 100 shown in FIG. 1, generally only one word line at a time may be active. For example, when the word line WL <0> is activated, the transistor 104 of the memory cell 101 connected to the word line WL <0> is turned on and each bit line and data storage element Charge flows.

Figure 1 shows a sense amplifier ("SA Latch") 110 as a further circuit of the DRAM for read, write and refresh operations, a precharge device 112 and an equalization device 113 (collectively a precharge device) are further shown. The sense amplifier can be used to reduce the signal of a small swing width on the bit line to a rail-to-rail voltage of the reference voltage Vss, such as a supply voltage level Vcc and a ground voltage appearing as "1 & rail signals. In one embodiment, the sense amplifier amplifies a signal having a swing width less than 100 millivolts with a signal swinging between a reference voltage level Vss or a ground voltage of 0.0V and a supply voltage level of 1.0V.

The precharge device 112 is coupled to the precharge supply voltage BLREF and the bit line. When activated, the precharge device charges the bit line to a predetermined voltage level of BLREF. Upon deactivation, the precharge device is turned off and the BLREF voltage level is disconnected from the bit line.

One embodiment of DRAM operation used as a reference in the following description is shown in FIG. This operation, which corresponds to the prior art, does not fall under the scope of the present claims and is described below only in order to effectively show the difference between the claims of the present application and the prior art.

2 shows a state of various signals including a data signal and a control signal during an operation of reading, refreshing or restoring data in a memory cell connected to a word line of the memory array and a time It is a timing diagram. The position from the left end of each graph in this time flow diagram corresponds to the same position in time and the same distance from the left end on all other graphs. Thus, the vertical lines on the graph across all the signals from the BL, / BL graph to the lower BLREF graph above the figure represent the same time points on all graphs.

1 and 2, in the prior art operation, the precharge device 112 is set to an active state by a PRE control signal to precharge the bit lines connected to the precharge device to the bit line reference (BLRFET) voltage level Charge. After precharging the bit line, the precharge device is deactivated. That is, in an inactive state. In one embodiment, the BLREF voltage level may be Vcc / 2 as shown in FIG. 2, and Vcc / 2 is the middle level between the supply voltage level (Vcc) and the reference level or ground (Vss). In one embodiment, Vcc / 2 may be the exact intermediate value of the reference voltages Vss and Vcc.

Then, when the word line is activated, that is, when the word line is switched to the active state, as indicated at 238, the WL voltage rises to Vpp as shown. The voltage level Vpp is generally higher than the voltage level Vcc used to store "1 " in the memory cell of the transistor. The high voltage level Vpp turns on the transistor 102 with sufficient headroom so that the voltage level Vcc can pass through the data storage element (e.g., storage capacitor) of the memory cell during normal read, write and refresh operations . Once the word line is activated, the transistor 102 is turned on, causing a charge to flow between each bit line to which the transistor is connected and the data storage element 104. This flow of charge generally increases the signal on the bit line connected to the memory cell through the corresponding transistor. Point 210 in the graph of FIG. 2 shows the signal increase when "1" is stored in the memory cell. Specifically, a small swing width signal observed at the voltage level increases from the original BLREF level (in this case, Vcc / 2) on the bit line. Conversely, when "0" is stored in the memory cell, the small swing width signal as shown at point 212 becomes smaller than BLREF. That is, Vcc / 2.

As the signal on the bit line increases, the sense amplifier connected to the bit line is activated by the transition to the opposite level of the signals SENSE and / SENSE, as shown at point 220. When the sense amplifier is activated, the sense amplifier amplifies the signal on the bit line connected to the sense amplifier to either Vcc (supply voltage level) or Vss (reference level or ground). The amplified signal is then stored back into the memory cell or transferred to the data input / output bus of the DRAM. As shown in 230 of FIG. 1, the sense amplifier amplifies the signal levels on bit lines BL and / BL to Vcc and Vss. When the signal on the bit line is amplified to Vcc and Vss, the amplified signal is restored to the memory cell for later access again. When the word line is deactivated, as indicated at point 240, then the sense amplifier is deactivated, as indicated at 250. Finally, at point 260, the PRE is reactivated to pre-charge the bit line for the next read, refresh, or restore, or write operation of the DRAM array. Thus, the precharge device 112 is activated again, and the voltage on the bit line returns to Vcc / 2, as at 270. However, when "1" is stored in the memory cell as indicated by the dotted line 280 indicated by "CN ", the voltage stored in the memory cell becomes Vcc. Conversely, when "0" is stored, the voltage stored in the memory cell becomes Vss as shown at 282.

The amplification of the signals on the bit lines is performed simultaneously by each of the plurality of sense amplifiers coupled to the bit lines connected to the memory cells on the same word line of the DRAM array. Thus, the data of the memory cells on the same word line can be simultaneously read, refreshed or restored.

3 shows the operation of the method of erasing data stored in the dynamic random access memory according to the first embodiment of the present invention. This embodiment is a special mode in which the operation of erasing stored data is performed. In this special mode, the active state of the word line and the active state of the control signal PRE provided in the memory correspond to the embodiment described with reference to FIG. 2 same. However, the control signals SENSE and / SENSE provided to the sense amplifier are disabled, and the sense amplifier 110 remains inactive while the word line is activated.

Thus, when word line WL is activated at time 316, as shown in Figure 3, the sense amplifier is inactive and remains inactive for the time the word line is active. As described above, charge flows between the bit line and the memory cell coupled to the bit line, which causes the signal on the bit line to be increased as shown at time 310 if "1" is stored in the memory cell. When "0" is stored in the memory cell, the signal increases as shown at time 312.

However, since the sense amplifier is deactivated during the time the word line is active, the sense amplifier does not amplify the signal to a storable signal level. Also, when the word line is activated, the charge stored in the memory cell at the "1" or "0" pole flows to the bit line, leaving only the charge in the memory cell that is insufficient to reliably represent the data bit. Thus, once the word line is deactivated again, the charge remaining in the memory cell is not sufficient to represent "1" or "0 ", and thus the data bits stored in the memory cell are erased.

The method shown in Figure 3 may be performed in a manner that uses one word line of a memory (DRAM) array to erase data stored in memory cells connected to that word line, and the other word lines of the memory array The method may be repeated in such a way as to erase the data of the memory cells connected to the line. To delete data in a selected range of memory arrays, this method can be repeatedly performed using the remaining number of word lines within a selected range of memory arrays (e.g., a row address range). In one embodiment, the selected range may be an entire memory array, in which case the method erases the data stored throughout the memory array. That is, all data stored in all the memory cells of the memory array is erased. Alternatively, the range of the memory array may be selected to include only a few word lines, while the range of the memory array is smaller than the entire memory array, and the method may erase only the data stored within the selected range of the memory array. In a particular embodiment, the selected range includes a plurality of word lines (e.g., a range including a plurality of word lines such as 7, 8, 10, 20, 43, 56, 64, 100 or 128 word lines of a memory array) And is smaller than the total number of movable word lines corresponding to the capacity of the entire memory array. Thus, the selected range includes a subset of the active word lines, only a portion of the DRAM array smaller than the full capacity of the DRAM array is selected, and another portion of the same DRAM array corresponding to the unselected active word line of the DRAM array is selected Left untouched. In this case, the "active" word line is a word line that is capable of storing current data in a connected memory cell. The active word lines do not include the word lines currently used for other purposes, for example only the word lines or DRAM array delays available as spare spare word lines when it is necessary to replace the active word lines of the DRAM array But does not include the word line used to monitor the word line. The number of wordlines in the selected range may be a power of 2 of 2 in one embodiment, and may not be an nth power of 2 in another embodiment.

In certain embodiments, an address counter may be used to select each word line to which the erase method is applied. In some cases, this address counter may be the refresh address counter 630 described below in connection with FIG. The address counter can cycle through the row address series in the order of the starting row address to the end row address of the selected row address range. The row address 620 is provided to one or more row decoders 620 as the output of the address counter 630 and the row decoder selects the word line of the DRAM array corresponding to the current row address and selects the selected word line . Generally, the address counter cycles through a series of successive row addresses starting from the starting row address until reaching the last row address of the selected row address range. In this way, the selected range of DRAM arrays is erased.

In certain embodiments, the method may be performed using non-contiguous word lines of the memory array. For example, one word line per two word lines of a memory array or one word line per three word lines of a memory array may be selected, and the data stored in the memory cells connected to the unselected word lines may be selected A method of erasing only data stored in a memory cell connected to a line can be performed. In addition, an erase method can be performed using one word line per several word lines instead of one word line for every two or three word lines. Such an implementation method partially disposes of the data stored in the memory cells connected to one word line per each two, three or several word lines in the active system memory, thereby disabling the remaining stored data so that the speed of the erase processor Improve.

4 illustrates an operation according to another embodiment of the present application. In this embodiment, as shown in Fig. 3, the sense amplifier is kept in an inactive state while the word line is activated. However, as shown at point 460, the PRE control signal is maintained at a high voltage state during the interval 462 during which the word line is active, so that the voltage level of each of the bit lines BL and / BL is reduced to a predetermined voltage level BLREF equal to Vcc / 2 Setting. As a result, the memory cell connected to the word line stores the charge according to a predetermined voltage level (e.g., Vcc / 2) instead of the previously stored data. In this way, the data previously stored in the memory cell is erased. The techniques described above with reference to FIGS. 3 and 6 can also be applied to this embodiment to erase data stored in the entire DRAM array or erase only data within a selected range in the DRAM array.

Fig. 5 shows an operation according to a variant of the embodiment described above with respect to Fig. In the embodiment described with reference to FIG. 4, the PRE control signal remains at a high voltage state while the word line is active. However, in the modification of this embodiment, the bit lines BL and / BL are set to the reference voltage level or the ground (Vss) instead of Vcc / 2. This operation can be implemented by changing the BLREF level supplied to the precharge device 112 according to a control signal (not shown). For example, when an erase operation is performed, BLREF may be set to another level, such as Vss, as shown at time 570. [ In this case, the bit lines BL and / BL hold a predetermined voltage level BLREF such as Vss, and the memory cells connected to the word lines store charges in accordance with a predetermined voltage level (e.g., Vss) Is recorded at a predetermined voltage level. Thus, if BLREF is set to a reference voltage level (e.g., ground Vss indicating "0"), the erase operation will store a "0" in a memory cell coupled to the word line.

In the general operation described above with reference to Figures 1 and 2 in which the memory performs general read, write, and refresh operations, the BLREF of Figure 5 is at a level that is between the supply voltage level and the reference level, Vcc / 2). For example, this level may be an intermediate value between Vcc (supply voltage level) and Vss (reference level such as ground). And the memory is set to a special mode for erasing the previously stored data discussed above in connection with FIG. 5, BLREF may be set to a special level, such as a reference voltage level or ground (Vss) . Figure 5 also shows the change in BLREF at 574 returning to medium level Vcc / 2 for normal operation. The techniques described above with reference to FIGS. 3 and 6 can also be applied to this embodiment to erase data stored in the entire DRAM array or erase only data within a selected range in the DRAM array.

In another variation of the above-described operation, the BLREF level can be switched to be set to the intermediate level Vcc / 2 during normal operation, and when the memory is set to a special mode for erasing stored data, the supply voltage level or other logic level voltage Can be set.

In another embodiment of the operation shown in FIG. 5, the word line voltage WL may alternatively be raised only by the power supply voltage level Vcc, instead of rising above the power supply voltage level Vpp as in the embodiment described above with reference to FIG. . In this case, the word line voltage WL raised to voltage level Vcc is sufficient to turn on the memory cell transistor (e.g., transistor 102 of FIG. 2) such that voltage level Vss is applied to the data storage element (e.g., storage capacitor 104 ).

FIG. 6 shows a memory 600 that may be included in one semiconductor chip or part of a semiconductor chip. The memory includes at least one dynamic random access memory array 610 that includes a row decoder and a word line driver circuit ("ROW DECS") 615, the dynamic random access memory array including row address signals 620 ) To the active state. 6, the row address signal 620 is received from an address counter, e.g., one or more refresh address counters ("refresh counter") 630. A sense amplifier ) 640 includes a sense amplifier ("SA Latch") 110 as described in connection with FIG. 1 and also includes an associated precharge device 112 and an equalization device 113.

The method according to embodiments of the present invention discussed above with respect to Figures 3, 4, and 5 can be implemented using the following control logic. The logic block "SENSE & PRECHARGE CONTROL" 650 is used to change the operation of the sense amp latch and precharge device and is used to change the bit line reference voltage BLREF supplied during normal and special operating modes. do. Thus, when the sense & precharge control block 650 is activated, the erase method is performed in the manner described above in connection with one of FIGS. 3, 4, or 5. If the sense & precharge control block 650 is not activated, general read, write and refresh operations are performed on the DRAM array 610.

The erase control block 660 may control when the memory starts or ends the special mode of erasing operation of the stored data when the sense & precharge control block 650 is activated. In a specific implementation, when the erase control block receives a signal from a power-on-reset ("POR") logic 670, it initiates operation of a special erase mode, The erasing method described above in connection with one of Figs. 3, 4, or 5 is performed.

Alternatively, using one or more signals from a portion of the external system of memory 600, the POR logic may detect that the system in which the memory is installed is in a power-on reset state, The erase method is executed. The erase control block also sets the memory to the special erase mode when it detects that the system in which the memory is installed is turned off or is in an interrupted state such as sleep mode or hibernation mode. Setting the system to the sleep mode or the hibernation mode in this manner is to allow the DRAM chip to automatically perform the erase method described above with reference to Figures 3, 4,

The erase control block may also receive a signal from a DLL block (DLL block) 680 if one or more other conditions occur, thereby causing the memory to be in a special erase mode, An erasing method is performed.

The memory 600 may be included in a computer, smart phone, or other electronic device, such as a desktop, laptop, tablet computing system, and signals from other parts of the system to the memory 600, It can be an input to control whether special mode operation starts and ends.

As one example that does not limit the above-described embodiments, combinations of the following chips may be included in a microelectronic package or high-level assembly with a DRAM chip comprising the features described above: (i) Memory; (ii) a plurality of memory chips of the same type; (iii) a plurality of memory chips of various types such as DRAM and SRAM; (iv) an image processor used to process images from the image sensor and the sensor; (v) application specific integrated circuits (ASICs) and memory. The structures described above can be used to form structures of various electronic systems. For example, system 700 according to another embodiment of the present disclosure includes the new DRAM chip 706 described above with other electrical components 708 and 710. [ For example, component 708 may be a semiconductor chip, component 710 may be a display screen, and other components may be used. Although only two additional components are shown in Fig. 7 for the sake of clarity, the system may include several components. The DRAM chip 706 may be the DRAM chip of Fig. 6 that operates in accordance with the method in conjunction with Figs. 3, 4, or 5. In another variation, two or more DRAM chips may be used, two or more DRAM chips may operate according to two or more of the above methods, or a combination of two or more DRAM chips may operate in accordance with one or more of the above- have. The DRAM chip 706 and components 708 and 710 are mounted in a common housing 701 shown in solid lines in the figure and are electrically interconnected with one another as needed to form the desired circuit. In the illustrated system, the system includes a circuit panel 702, such as a flexible printed circuit panel or circuit board, which includes many conductors 707 (only one shown in Figure 7) interconnected with other components . However, this is merely exemplary and any suitable structure for forming an electrical connection can be used. The housing 701 is depicted as a portable housing that can be used, for example, in a cell phone, tablet computing system, electronic reader, or personal digital device, and the screen 710 is exposed on the surface of the housing. A light-sensing element is included at a location where the DRAM chip 706 is packaged or packaged in the housing 701 and the light-sensing element routes light to an imaging chip (not shown), a lens 711, Lt; / RTI &gt; The simplified system shown in Fig. 7 is only one example, and includes a system of generally fixed structure, such as a desktop computer, a router, and the like using the above-described structure.

Although the present invention has been described with reference to particular embodiments, these embodiments are intended to illustrate the principles and applications of the present invention only. It is therefore evident that many other modifications will be apparent to the embodiments described and that other modifications may be devised within the scope of the invention as defined in the claims herein.

Claims (20)

CLAIMS What is claimed is: 1. A method of erasing data stored in a dynamic random access memory (DRAM)
(a) setting a word line of the DRAM array to an active state, wherein the bit line is connected to the memory cell connected to the word line according to data stored in the memory cell, ), And the signal on each bit line is increased in accordance with the flow of charge between the memory cell and the bit line to which the word line is connected; And
(b) maintaining a sense amplifier connected to each bit line in an inactive state so that a sense amplifier connected to each bit line does not amplify the signal to a storable signal level, Erasing data stored in the memory cell connected to the word line by setting the word line to an inactive state such that insufficient charge is maintained in the memory cell
Lt; / RTI &gt;
The sense amplifier is kept in an inactive state by a control block operating in an erase mode in which at least one predefined event is erased,
The sense amplifier is generally operated for read, write and refresh operations by a control block operating in a normal mode in which none of the at least one predefined event is deleted,
Wherein step (a) comprises selecting the word line using a refresh address counter.
A method for erasing data stored in a DRAM array. The method according to claim 1,
Wherein setting the word line to an active state is performed by raising the voltage of the word line to a voltage level that is higher than a voltage level used to store a "1" in a memory cell of the DRAM, / RTI &gt; The method according to claim 1,
Wherein setting the word line to an active state is performed by raising the voltage of the word line to a power supply voltage level Vpp. The method according to claim 1,
Wherein setting the word line to an active state is performed by raising the voltage of the word line to a voltage level equal to a voltage level used to store a "1" in a memory cell of the DRAM, / RTI &gt; 5. The method of claim 4,
Wherein the voltage of the word line is raised to a power supply voltage level Vcc used to power the DRAM. The method according to claim 1,
Wherein steps (a) and (b) are performed using each of a plurality of word lines of an entire memory array to erase data stored in the entire memory array. The method according to claim 6,
After step (a) and step (b) are performed on a selected range of word lines smaller than the entire memory array, steps (a) and (b) are performed for each of the plurality of remaining word lines in the selected range A method for erasing data stored in a DRAM array that is repeated. delete The method according to claim 1,
Further comprising precharging the bit line to a first voltage level prior to step (a). 10. The method of claim 9,
Wherein the first voltage level is an intermediate level between a high signal voltage level and a low signal voltage level each representing "1" and "0" stored in the memory cell connected to the word line How to erase. 10. The method of claim 9,
The precharging of the bit line may be performed by setting a precharge device connected to the bit line to an active state,
A method for erasing data stored in a DRAM array,
Further comprising maintaining the precharge device coupled to the bit line in an inactive state while the sense amplifier remains inactive. A memory comprising a dynamic random access memory (DRAM) array,
A DRAM array including a memory cell, a word line, and a bit line coupled to the memory cell; And
Sense amplifier
Lt; / RTI &gt;
The memory comprising:
(a) setting a word line of the DRAM array to an active state, whereby charge is caused to flow between a memory cell and a respective bit line to which the word line is connected according to data stored in the memory cell, Setting a word line to an active state in which the signal on each bit line increases in accordance with the flow of charge between the memory cell to which the line is connected and the respective bit line; And
(b) maintaining a sense amplifier connected to each bit line in an inactive state such that a sense amplifier coupled to each bit line does not amplify the signal to a storable signal level, Erasing data stored in the memory cell connected to the word line by setting the word line to an inactive state such that one charge is maintained
Wherein the controller is configured to:
Wherein step (a) comprises selecting the word line using a refresh address counter,
The sense amplifier is kept in an inactive state by a control block operating in an erase mode in which at least one predefined event is erased,
Write and refresh operations by a control block operating in a normal mode in which the sense amplifier is in a state in which none of the at least one predefined event is deleted,
Memory. 13. The method of claim 12,
Wherein setting the word line to an active state is performed by raising the voltage of the word line to a voltage level that is higher than a voltage level used to store a "1" in a memory cell of the DRAM. 13. The method of claim 12,
Wherein the voltage of the word line is raised to a power supply voltage level equal to a voltage level used to store a "1" in a memory cell of the DRAM. 13. The method of claim 12,
Wherein steps (a) and (b) are performed using each of a plurality of word lines of an entire memory array to erase data stored in the entire memory array. 13. The method of claim 12,
Wherein steps (a) and (b) are performed using each of a plurality of word lines in a selected range of a memory array smaller than the entire memory array, thereby erasing the data stored in the selected range. 13. The method of claim 12,
Wherein the memory is configured to perform an operation further comprising precharging the bit line to a first voltage level prior to performing step (a). 18. The method of claim 17,
Wherein the first voltage level is an intermediate level between a high signal voltage level and a low signal voltage level, respectively, representing "1" and "0" stored in the memory cell connected to the word line. 18. The method of claim 17,
Wherein precharging the bit line to a first voltage level is performed by setting a precharge device coupled to the bit line to an active state,
Wherein the memory is further configured to maintain the precharge device coupled to the bit line in an inactive state while the sense amplifier remains inactive. 13. The method of claim 12,
Wherein the memory is configured to include setting the word line to an active state to raise a voltage of the word line to a power supply voltage level Vpp.

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