KR101737433B1 - 1Gbps Data Communication System - Google Patents

Abstract

A 1 Gbps data transmission / reception system of the present invention comprises a first Ethernet converter adapted to communicate with an optical network unit (ONU), and a second Ethernet converter connected to the first Ethernet converter via a UTP 2 pair, And a second Ethernet converter for matching the speed of transmission data to be transmitted to the terminal device and providing the UTP cable to the terminal device. Thus, it is possible to provide 1Gbps Internet service using two pairs of UTP cable There is an effect that the cost for constructing the service can be minimized.
Furthermore, since the present invention can easily change the degree of speed matching of transmission data, it is also possible to provide a service of 1 Gbps or more.

Description

1 Gbps data transmission / reception system {1 Gbps Data Communication System}

The present invention relates to a 1 Gbps data transmission / reception system.

Recently, with the development of multimedia technology such as UDTV (Ultra Definition TV) or IPTV (Internet Protocol TV), the Internet speed is increasing to smoothly provide the above services.

Internet service using existing telephone line has been providing ADSL and Internet service using UTP (Unshielded Twisted Pair) cable recently.

However, in order to smoothly provide the above-mentioned service, the transmission rate of the existing Internet service is insufficient and new measures should be sought.

In this method, a fiber to the home (FTTH) technology in which an optical fiber cable is directly connected to a house can be considered. Such a technique is disclosed in Korean Patent Registration No. 10-0798915 entitled " Modem matching devices and methods).

However, in the existing residential area where the UTP is installed, since it is necessary to newly install an optical cable to each house, it is not easy to wiring and it is economically costly.

Therefore, in order to solve the above problems, the above-mentioned problems must be solved by using a UTP cable installed in the past.

On the other hand, in the government building, the buildings are given 1st, 2nd and 3rd grades and grade-level certification on the basis of the construction of the lines in the building. Two pairs of UTP cables below grade 2 certification are assigned to each household have.

In order to transmit / receive data of 1 Gbps or more, four pairs of UTP cables must be used. However, only two pairs of UTP cables are allocated to the buildings of class 2 or lower certification, .

Therefore, it is an object of the present invention to provide a system capable of transmitting / receiving data at 1 Gbps using only the UTP 2 pair installed in an Ethernet connection using a UTP cable (Cat 5 / 5E Bundle, Cat 5 / 5E) .

According to another aspect of the present invention, there is provided a communication system including a first Ethernet converter configured to communicate with an ONU (Optical Network Unit), and a second Ethernet converter connected to the first Ethernet converter via a UTP 2 pair, And a second Ethernet converter for matching the speed of the first Ethernet converter to the terminal device.

The first Ethernet converter includes a first PMA (Physical Medium Attachment) block having four first hybrid circuits for transmitting and receiving data to and from the ONU, a first PCS (Scramble) transmission data and received data, And a first SerDes block (Serializer / Deserializer) for parallelizing the received data received from the second Ethernet converter or serializing transmission data to be transmitted to the second Ethernet converter.

The first PMA block modulates data using a PAM (Pulse Amplitude Modulation) technique.

And 3-bit symbol data is allocated to the four first hybrid circuits.

The first PCS block includes a first PCS transmitter for processing transmission data transmitted from the first PMA block to the first SerDes block and a second PCS transmitter for processing received data transmitted to the first PMA block in the first SerDes block The first PCS transmitter descrambles the 12-bit transmission data into 8 bits and the first PCS receiver scrambles the 8-bit reception data into 12 bits. do.

In this case, the first PCS transmitter and the first PCS receiver are operated at a clock rate of 125 MHz.

The first SerDes block includes a first serialization unit for serializing transmission data transmitted from the first PCS block to the second Ethernet converter and a second serialization unit for serializing transmission data transmitted from the second Ethernet converter to the first PCS block Wherein the first serializing unit encodes 8-bit transmission data into 10-bit data, and the first parallelizing unit decodes the 10-bit received data into 8-bit data, wherein the first parallelizing unit performs de- .

In this case, the first SerDes block operates at a clock rate of 125 MHz.

The second Ethernet converter includes a second SerDes block for parallelizing transmission data received from the first SerDes block or serializing received data to be transmitted to a first SerDes block, a second SerDes block for serializing received data to be transmitted to the first SerDes block, A second PCS for scrambling transmission and reception data, and a second PMA block having four second hybrid circuits for transmitting and receiving data to and from the terminal device, .

The second SerDes block may include a second parallelizing stage for de-serializing transmission data transmitted to the rate matching block in the first PCS block and a second parallelizing stage for de-serializing transmission data transmitted to the rate matching block in the first PCS block, The second serializing unit decodes the 10-bit transmission data into 8-bit data, and the second serializing unit encodes the 8-bit transmission data into 10-bit data.

At this time, the internal part of the second SerDes block operates at a clock speed of 125 MHz.

The speed matching block includes a transmission data processing unit for matching the speed of the transmission data transmitted in the second SerDes block and a reception data processing unit for matching the speed of the reception data transmitted in the second PCS block. do.

The transmission data processing unit operates at a clock speed of 78.125 MHz, and the received data processing unit operates at a clock speed of 125 MHz.

In this case, when four or more 8-bit transmission data are recorded in the transmission data processing unit, an empty signal (TxD_Out_Empty) is transmitted to the second PCS block. If there is more than 8-bit reception data in the reception data processing unit, And transmits an Empty signal (RxD_Out_Empty).

The second PMA block converts the transmission data transmitted from the second PCS block into a symbol using a Tomlinson-Harashima Precoder (THP).

The second PCS block may include a second PCS transmitter for processing transmission data transmitted from the second SerDes block to the second PMA block and a second PCS transmitter for processing received data transmitted to the second SerDes block in the second PMA block And the second PCS transmitting end receives the two pieces of transmission data from the rate matching block and scrambles 65 bits by inserting a 1 bit at the beginning of the auxiliary header, and the second PCS receiving end scrambles 65 bits Data is descrambled to generate two 32-bit received data and a 1-bit auxiliary header.

The second PCS block includes a frame processing unit for generating a frame for performing error detection and correction of transmission data to be transmitted to the second PMA block and for decoding the frame of the received data, And a symbol processing unit.

The frame processing unit receives 20 transmission data or 25 blocks scrambled with the 65 bits, inserts 1 bit of the board at the head, inserts a CRC8 (Cyclic Redundancy Check) at the back, and outputs 2048 bits of LDPC (Low Density Parity Check) frame.

And the frame processing unit is characterized in that the rate of forming the LDPC frame is different according to the number of blocks among the transmission data input to the frame processing unit.

In this case, the symbol processor generates two symbols using the PAM16 technique.

Accordingly, the present invention can provide a 1 Gbps-level Internet service using two pairs of UTP cable installed without installing or expanding a new cable, so that there is an effect that the cost for constructing a 1 Gbps service can be minimized.

Furthermore, since the present invention can easily change the degree of speed matching of transmission data, it is also possible to provide a service of 1 Gbps or more.

1 is a conceptual diagram showing a conventional data transmission / reception system.
2 is a conceptual diagram to which the 1 Gbps data transmission / reception system of the present invention is applied.
3 is a block diagram showing a 1 Gbps data transmission / reception system of the present invention.
4 is a block diagram illustrating a second SerDes block and rate matching block of the present invention.
5 is a flow chart illustrating a process for processing transmission data in a second PCS block of the present invention.
6 is a flow chart illustrating a process for processing received data in a second PCS block of the present invention.
Figs. 7 and 8 are flowcharts showing operational examples of the frame processing unit of the present invention.

The preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which the technical parts already known will be omitted or compressed for the sake of brevity.

FIG. 1 is a conceptual diagram illustrating a conventional data transmission / reception system using a pair of UTP cables (specifically, a system operating on a 100 Base-T basis), and can not provide a transmission rate of 100 Mbps or more at maximum.

On the other hand, as shown in FIG. 2, the 1 Gbps data transmission / reception system of the present invention is applied to an existing residential area provided with two pairs of UTP cables shown in FIG. 1, 1 Ethernet converter 100 and the second Ethernet converter 200 is disposed on the side of the terminal device 20 so that 1 Gbps data transmission and reception are performed.

Hereinafter, the flow of transmission data (downlink data, downlink data) transmitted from the ONU 10 to the terminal device 20 will be described with reference to simplicity and ease of explanation.

As shown in FIGS. 2 and 3, the 1 Gbps data transmission / reception system of the present invention includes a first Ethernet converter 100 and a second Ethernet converter 200.

The In the embodiment  accompanying 1st  Description of the Ethernet converter 100

The first Ethernet converter 100 is provided for communicating with the ONU 10 and supports a standard 1000 Base-T basis.

The first Ethernet converter 100 includes a first PMA block 110, a first PCS block 120, and a first SerDes 130.

A first PMA (Physical Medium Attachment) block 110 is a component for directly transmitting and receiving data to and from the ONU 10 via a UTP cable. The first PMA 110 transmits and receives data (not shown) Four hybrid circuits 111 are provided and one UTP cable is connected in pairs.

Here, the first PMA block is configured to perform modulation (specifically, transmission data encoding and reception data demodulation) using PAM (Pulse Amplitude Modulation) technique. In the embodiment of the present invention, a 5-level PAM technique is used .

Accordingly, data is processed by 3 bits in each of the four first hybrid circuits 111 according to the value of the 5th level PAM, and data is transmitted / received at a rate of 250 Mbps (i.e., 125 MHz X 2 bit / Symbol).

The first PCS block 120 scrambles the received data received from the first PCS transmitter 121 and the first SerDes 130 to descramble the transmission data received from the first PMA block 110 And a first PCS receiving end 122 for scrambling the first PCS.

Here, the first PCS transmitter 121 descrambles the 12-bit transmission data to 8 bits, and the first PCS receiver 122 scrambles the 8-bit reception data to 12 bits.

In addition, the first PCS transmitting terminal 121 and the first PCS receiving terminal 122 operate at a clock speed of 125 MHz.

Accordingly, the first PCS transmitter 121 transmits the transmission data to the first SerDes block 130 at a rate of 8 bits X 125 MHz = 1000 Mbps.

The first SerDes block 130 serializes transmission data to be transmitted to the second SerDes block 210 of the second Ethernet converter 200 (specifically, a symbol constituting transmission data) 2 Ethernet converter 200. The second SerDes block 210 is a component for deserializing the received data received from the second SerDes block 210 of the Ethernet converter 200. [

As described above, the first SerDes block 130 includes a first serializing unit 131 for serializing transmission data transmitted from the first PCS block 120 to the second Ethernet converter 200, And a first parallelizing stage 132 for de-serializing received data transmitted from the converter 200 to the first PCS block 120. [

Here, in the embodiment of the present invention, the first serialization stage 131 and the first parallelization stage 132 are separately described for the sake of brevity, but the present invention is not limited thereto and may be a single block for performing serialization and parallelization. Can also be considered sufficiently.

At this time, the first serializing unit 131 encodes 8-bit transmission data into 10-bit (8B / 10B Encoding) and the first parallelizing unit 132 decodes 10-bit received data into 8-bit (10B / 8B).

Thus, the transmission data encoded in 10 bits is transmitted to the second Ethernet converter 200 at a speed of 1.25 Gbps (10 bits X 125 MHz).

The In the embodiment  accompanying Second  Description of Ethernet converter 200

The second Ethernet converter 200 according to the embodiment of the present invention is a component provided to provide the terminal device 20 with transmission data transmitted from the first Ethernet converter 100. The second Ethernet converter 200 includes a second SerDes block 210, A speed matching block 220, a second PCS block 230, and a second PMA block 240.

The second SerDes block 210 is a component for parallelizing the transmission data and serializing the reception data as described above, and is connected to the first SerDes block 130 so that data can be transmitted and received.

A second parallelizing stage 211 for de-serializing the transmission data transmitted from the first PCS block 120 to the rate matching block 220 and a second parallelizing stage 211 for combining the first PCS block 120 And a second serialization unit 212 for serializing the received data to be transmitted to the second serialization unit 212.

At this time, the second parallelizing stage 211 is configured to decode (10B / 8B) 10-bit transmission data to 8-bit and the second serializing stage 212 to encode (8B / 10B) .

Here, the second SerDes block 210 operates at a clock speed of 125 MHz, so that transmission data decoded in 8 bits is transmitted to the rate matching block 220 at a speed of 1 Gbps (8 bits X 125 MHz).

The speed matching block 220 is a component that matches the speed of data transmitted and received between the first Ethernet converter 100 and the second Ethernet converter 200.

The speed matching block 220 compares the speed of the received data transmitted from the transmission data processing unit 221 and the second PCS block 230 that match the speed of the transmission data transmitted from the second SerDes block 210 And a received data processing unit 222 for matching.

Here, the transmission data processing unit 221 and the reception data processing unit 222 may be implemented using DPRAM (Dual Ported RAM) or FIFO (First In First Out). In the embodiment of the present invention, And the received data processing unit 222 are implemented as FIFOs.

In the embodiment of the present invention, the transmission data processing unit 221 operates at a clock rate of 78.125 MHz, and the reception data processing unit 221 and the reception data processing unit 222 operate at a different clock rate. The processing unit 222 operates at a clock speed of 125 MHz.

In other words, the transmission data is input to the rate matching block 220 at a transmission rate of 8 bits X 125 MHz (= 1 Gbps) and output at a transmission rate of 32 bits X 78.125 MHz (= 2.5 Gbps).

As described above, since the transmission data processing unit 221 and the reception data processing unit 222 are read and written at different clock rates, a full signal and an empty signal of the FIFO are used to prevent data loss and asynchronism .

Specifically, if the transmission data processing unit 221 is not in the Full state, it performs 8-bit transmission data write from the first SerDes block 210.

When more than four 8-bit data are recorded in the transmission data processing unit 221, the second PCS block 230 notifies the transmission data processing unit 221 of the existence of valid data by using the empty signal (TxD_Out_Empty) The PCS block 230 receives the transmission data in units of 32 bits.

On the other hand, when there is more than 8 bits of received data in the received data processing unit 222, the second SerDes block 210 informs that there is valid data using the empty signal (RxD_Out_Empty) The received data is received in units of 8 bits.

The data exchanged between the second SerDes block 210, the rate matching block 220 and the second PCS block 230 is shown in detail in FIG.

The second PCS block 230 scrambles the transmission data and the reception data, and modulates / demodulates the transmission and reception data (specifically, symbol vectors of transmission and reception data).

The second PCS block 230 includes a second PCS transmitter 231, a second PCS receiver 232, a frame processor 233, and a symbol processor 234.

The second PCS transmitting end 231 processes the transmission data transmitted from the second SerDes block 210 to the second PMA block 240 and the second PCS receiving end 232 processes the transmission data transmitted from the second PMA block 240 to the second Is a component that processes the received data transmitted to the SerDes block 210.

In contrast, the second PCS receiver 232 descrambles the 65-bit received data to generate two 32-bit received data and a 1-bit auxiliary header.

The frame processor 233 is a component that generates a frame for error detection and correction of transmission data transmitted to the second PMA block 240 and decodes a frame of reception data.

Hereinafter, the process of processing transmission data in the second PCS block 230 will be described in detail with reference to FIG. 5 to FIG.

First, the second PCS transmitter 231 receives two 32-bit transmission data (64 bits in total) from the speed matching block 220 and inserts a 1-bit first header into the auxiliary header to perform 65-bit encoding and scrambling.

Thereafter, the frame processor 233 detects an error of transmission data that may occur during the transmission through the UTP cable, and encodes (LDPC Encoding) using the LDPC (Low Density Parity Check) method to correct the error.

To this end, the frame processor 233 receives 1634 bits (1 + 65 x 25 + 8) by adding 25 bits of 65-bit data blocks and inserting an auxiliary 1 bit at the end of the data and inserting CRC8 (Cyclic Redundancy Check) And generates an LDPC data frame.

At this time, the rate at which the frame processor 233 generates the LDPC data frame is 1.5625 M frames per second (200 M symbols / sec based on the symbol).

The symbol processing unit 234 processes the symbols of the transmission data and the reception data. The symbol processing unit 234 forms symbols by using 4 bits of transmission data. The symbol processing unit 234 generates two symbols PAM16 Create a symbol. (I.e., two symbols are generated using the 2D-PAM16 technique).

Since the transmission rate of the transmission data processed by the above method is 1.25 Gbps and the transmission rate of 1.25 Gbps is higher than 1 Gbps that can be processed by the terminal device 20, the frame processing speed is reduced and the signal to noise ratio (SNR) And a frame processing unit 233 capable of improving the PER (Packet Error Rate) will be described.

In the two embodiments, since the frame processing unit 233 processes the transmission data by receiving twenty-five (65) -bit blocks or twenty-five (25) blocks, the embodiment will be described separately.

In the first embodiment of the frame processing section 233, when the frame processing section 233 receives 25 transmission data having a block of 65-bit units, the frame processing section 233 sets the rate at which the LDPC data frame is generated to 1.5625 Mega ( Megahertz (M) frame / sec to 1.25M frame / sec (160M Symbols / sec based on the symbol).

As described above, since the frame processing unit 233 reduces the rate at which the LDPC frame is generated, the occupied frequency band used through the UTP cable can be lowered by about 20%, thereby reducing the interference between the transmission data and the reception data.

In the second embodiment of the frame processing unit 233, the frame processing unit 233 receives only 20 pieces of block transmission data (1 + 65 x 20 + 1 = 1309) Decoding and encoding gain is increased (1309bit is encoded to 2048bit), and the data rate is maintained at 1Gbps and signal-to-noise ratio (SNR) is improved to improve PER.

That is, the frame processing unit 233 can improve the SNR of the transmission data by decreasing the rate of generating the LDPC frame (reducing the symbol rate) or decreasing the number of blocks of received transmission data (by reducing the block data) .

Thereafter, the symbol processing unit 234 generates two PAM 16 symbols so that one symbol can be transmitted through two UTP pairs, using 4 bits of transmission data. (I.e., two symbols are generated using the 2D-PAM16 technique).

The second PMA block 240 is a component having four second hybrid circuits 241 for transmitting and receiving data through the terminal 4 and the UTP cable 4 pair.

The second PMA block 240 converts the transmission data received from the second PCS block 230 into a symbol using a Tomlinson-Harashima Precoder (THP) and converts it into an analog signal by a DAC (Digital Analog Converter And the converted symbols are respectively assigned to the second hybrid circuit 241 to perform communication with the terminal device 20.

At this time, the second PMA block 240 processes 200M symbols per second, and the transmission rate of the transmission data finally transmitted to the terminal device 20 is 1.25 Gbps.

Accordingly, the second PMA block 240 allocates a transmission rate of 625 Mbps for each pair of UTP cables (that is, one second hybrid circuit 241), and connects the terminal device 20 to the UTP cable pair It is possible to provide a transmission rate exceeding 1 Gbps.

According to the present invention, it is possible to provide a 1Gbps-level Internet service using two pairs of UTP cables installed without installing or expanding a new cable, thereby minimizing the cost for establishing a 1Gbps service.

Furthermore, since the present invention can easily change the degree of speed matching of transmission data, it is also possible to provide a service of 1 Gbps or more.

Therefore, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the technical idea of the present invention. The scope of protection is to be construed in accordance with the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

10: ONU
20:
100: First Ethernet converter
110: first PMA block
111: first hybrid circuit
120: first PCS block
121: first PCS transmitting end 122: first PCS receiving end
130: first SerDes block
131: first serialization stage 132: first parallelization stage
200: Second Ethernet converter
210: second SerDes block
211: second parallelizing stage 212: second serializing stage
220: Speed matching block
221: Transmission data processing section 222: Reception data processing section
230: second PCS block
231: second PCS transmitting end 232: second PCS receiving end
233: Frame processing section 234: Symbol processing section
240: second PMA block
241: second hybrid circuit

Claims (20)

A first PMA (Physical Medium Attachment) block having four first hybrid circuits for transmitting and receiving data to and from an ONU (Optical Network Unit);
A first PCS (Physical Coding Sublayer) block for scrambling transmission data received from the first PMA block and received data to be received from the first SerDes block and transmitted to the first PMA block; And
A first SerDes block (Serializer / Deserializer) for serializing the transmission data to be transmitted from the first PCS block to the second Ethernet converter, or parallel received data to be transmitted to the first PCS block received from the second Ethernet converter;
A second SerDes block for parallelizing transmission data received from the first SerDes block or for serializing received data to be transmitted to the first SerDes block;
A rate matching block for matching a rate of transmission data transmitted in the second SerDes block and received data to be transmitted to the second SerDes block;
A second PCS (Physical Coding Sublayer) block scrambling the transmission data received from the rate matching block and the received data received from the second PMA block; And
A second PMA block having four second hybrid circuits for transmitting and receiving data to and from a terminal device, the second PMA block receiving transmission data from the second PCS block; / RTI >
The speed matching block includes:
A transmission data processor for outputting data of 8 bits x 125 MHz coming from the second SerDes block to 32 bits x 78.125 MHz; And
And a received data processing unit for matching data coming from the second PCS block
1 Gbps data transmission and reception system. delete The method according to claim 1,
Wherein the first PMA block modulates data using a Pulse Amplitude Modulation (PAM) technique
1 Gbps data transmission and reception system. The method according to claim 1,
And 3-bit symbol data is allocated to each of the four first hybrid circuits
1 Gbps data transmission and reception system. The method of claim 1, wherein
Wherein the first PCS block comprises:
A first PCS transmitter for processing transmission data transmitted from the first PMA block to the first SerDes block; And
And a first PCS receiver for processing received data transmitted from the first SerDes block to the first PMA block,
The first PCS transmitter descrambles the 12-bit transmission data into 8 bits, and the first PCS receiver scrambles the 8-bit reception data into 12 bits.
1 Gbps data transmission and reception system. 6. The method of claim 5,
And the first PCS transmitter and the first PCS receiver operate at a clock rate of 125 MHz.
1 Gbps data transmission and reception system. The method according to claim 1,
Wherein the first SerDes block comprises:
A first serializing unit for serializing transmission data transmitted from the first PCS block to the second Ethernet converter; And
And a first parallel processing unit for de-serializing received data transmitted from the second Ethernet converter to the first PCS block,
The first serializing stage encodes the 8-bit transmission data into 10-bit data, and the first parallelizing stage decodes the 10-bit received data into 8-bit data
1 Gbps data transmission and reception system. 8. The method of claim 7,
Wherein the first SerDes block operates at a clock rate of 125 MHz.
1 Gbps data transmission and reception system. delete The method according to claim 1,
Wherein the second SerDes block comprises:
A second parallelizing stage for de-serializing transmission data transmitted to the rate matching block in the first PCS block; And
And a second serialization unit for serializing received data transmitted from the rate matching block to the first PCS block,
The second serializing stage decodes the 10-bit transmission data into 8-bit data, and the second serializing stage encodes the 8-bit transmission data into 10-bit data
1 Gbps data transmission and reception system. 11. The method of claim 10,
And the inner part of the second SerDes block operates at a clock rate of 125 MHz.
1 Gbps data transmission and reception system. delete delete The method according to claim 1,
(TxD_Out_Empty) to the second PCS block when four or more 8-bit transmission data are recorded in the transmission data processor, and if there is more than 8-bit reception data in the reception data processor, Empty Lt; RTI ID = 0.0 > RxD_Out_Empty < / RTI >
1 Gbps data transmission and reception system. The method according to claim 1,
And the second PMA block converts the transmission data transmitted from the second PCS block into a symbol using a Tomlinson-Harashima Precoder (THP)
1 Gbps data transmission and reception system. The method according to claim 1,
Wherein the second PCS block comprises:
A second PCS transmitter for processing transmission data transmitted from the second SerDes block to the second PMA block; And
And a second PCS receiver for processing received data transmitted from the second PMA block to the second SerDes block,
The second PCS transmitter receives two pieces of transmission data from the rate matching block, inserts a 1-bit first header into the first header, and scrambles the 65 bits to 65 bits. The second PCS receiver descrambles the 65- And generates reception data and a 1-bit auxiliary header.
1 Gbps data transmission and reception system. 17. The method of claim 16,
Wherein the second PCS block comprises:
A frame processor for generating a frame for performing error detection and correction of transmission data transmitted to the second PMA block and decoding a frame of received data; And
And a symbol processing unit for processing the symbols of the transmission data and the reception data
1 Gbps data transmission and reception system. 18. The method of claim 17,
The frame processing unit receives 20 or 25 blocks of transmission data scrambled with the 65 bits, inserts 1 bit of the board at the head, inserts a CRC8 (Cyclic Redundancy Check) at the back, and outputs 2048 bits of LDPC (Low Density Parity Check) frame.
1 Gbps data transmission and reception system. 19. The method of claim 18,
And the frame processing unit is characterized in that the rate of forming the LDPC frame is different according to the number of blocks among the transmission data input to the frame processing unit
1 Gbps data transmission and reception system. 18. The method of claim 17,
Wherein the symbol processing unit generates two symbols using the PAM16 scheme
1 Gbps data transmission and reception system.

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