KR101531184B1 - A decoding method and apparatus using interworking between upper and lower layers, and a data transmission / reception system using the same - Google Patents

Abstract

The present invention relates to a decoding method and apparatus using interworking between upper and lower layers and a data transmission / reception system using the same.

According to another aspect of the present invention, there is provided an apparatus for decoding data encoded with source information, the apparatus comprising: a lower layer decoder for decoding data using a lower layer code and outputting a bit whose reliability of each bit of the decoded data is equal to or greater than a predetermined reliability threshold; ; And an upper layer decoder for decoding the bits output from the lower layer decoder using the upper layer code to recover the source information.

According to the present invention, it is possible to transmit / receive data with a smaller error rate in a given channel environment and to significantly reduce the number of bits of the total received data required to achieve the same target error rate, It can be reduced.

Wireless, channel, broadcast, data, error, correction, layer, MBMS, Rateless, Turbo, CRC

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding method and apparatus using interworking between upper and lower layers, and a data transmission /

The present invention relates to a decoding method and apparatus using interworking between upper and lower layers and a data transmission / reception system using the same. More particularly, the present invention relates to a method and apparatus for more accurately decoding encoded data using a lower layer code and an upper layer code, and a data transmission / reception system using the same.

3GPP proposes a broadcast data transmission service called a Multimedia Broadcast Multicast Service (MBMS) which can efficiently transmit the same information to a plurality of users at the same time. MBMS is an application of Forward Error Correction (FEC) technology. The FEC technique adds redundancy to the transmitted data and transmits the data together. Thus, It is possible to eliminate an error caused by fading and noise when the signal is generated. FEC is an error correction technique, which is essential in unidirectional transmission services such as transmission of broadcast data, because an error can be corrected by the receiver itself without requiring retransmission when an error is found in the data received by the receiver. In particular, when providing a broadcasting service, since the service provider provides information to all users, which is not a specifically targeted user, it is required to transmit information unidirectionally without communicating information between the service provider and the user. Therefore, FEC technology is indispensable for providing a broadcasting service.

The well known FEC algorithm (hereinafter abbreviated as FEC algorithm) includes Convolutional Code, Reed-Solomon Code, Turbo Code, Low Density Parity Check An algorithm for correcting errors using LDPC codes (Low-Density Parity-Check Code), Tornado Code, LT Code (Lombard Transform Code), Raptor Code have. Algorithms using each code generate redundancy in different ways, and redundancy is added to the original information to generate a codeword. The ratio of the length of the codeword is called a coding rate.

Among the FEC algorithms, there is an FEC algorithm suitable for unicast transmission in which a coding rate is fixed and a channel used by a receiver is known. On the other hand, if a coding rate is not fixed and continuous generation and transmission of redundancy is performed, There is an FEC algorithm that can decode information of the FEC algorithm. The code used in the FEC algorithm is called a rateless code. The rateless code can be a FEC algorithm suitable for a broadcast which the user is unclear because the transmitter can transmit whether or not the receiver can receive data with high reliability without knowing it at the transmitter. A typical rateless code is a ruby transform code, a raptor code, etc., and is actually used as a broadcast FEC algorithm.

In the next generation data transmission such as 4G, it is expected to develop a technology for a broadcasting service including an FEC algorithm that enables data to be transmitted regardless of time or place to any mobile user. However, due to an increase in transmission requirement, ) And a technology that can be transmitted to a larger range of users. The development of improved broadcasting codes in this environment is important.

In addition, it is necessary to develop a code optimized for a wireless channel environment. Currently, the code used in the 3GPP MBMS is optimized in the wired environment and uses physical layer FEC already in the physical layer to operate in a wireless environment. That is, once the decoder in the physical layer operates in accordance with the wireless situation and corrects the error and sends the corrected information to the rateless code decoder in the upper layer, the rateless code decoder can perform additional error correction from the corrected information . At this time, the reason why additional error correction is required is that if the channel environment is bad in the physical layer, the decoding fails and the decoded block is not transmitted to the rateless code decoder. If there is a block that is not transmitted in this manner, the block is erased from the state of the rateless code decoder. When the erased block is present, the rateless code decoder can recover the erased information.

In this way, in a system in which a layer to be decoded using an error correcting code is composed of a lower layer and an upper layer, an error correction is performed considering an fading environment using an error correction code in the physical layer, Additional error correction is done using the lease code. However, when error correction is performed in two steps, the decoders of the physical layer typically send only the decoded information to the upper layer rithless code decoder so that the performance degrades. That is, if there is fading in the physical layer, the block is not decoded but still useful information may be included in the block. If such information is available in the upper layer of the rateless code, there is a possibility of achieving further improved performance. Therefore, there is a need to develop a new technique that enables useful information contained in blocks that are not decoded in the physical layer to be used in an upper layer.

In order to solve the above-mentioned problems and to meet new demands, the present invention provides a method and apparatus for performing additional error correction using decoded bits in a physical layer, The main goal is to perform more accurate error correction using highly reliable bits that are not decoded correctly.

According to an aspect of the present invention, there is provided an apparatus for decoding data encoded with source information, the apparatus comprising: a decoder for decoding data using a lower layer code, wherein reliability of each bit of the decoded data is equal to or higher than a predetermined reliability threshold A lower layer decoder for outputting a bit; And an upper layer decoder for decoding the bits output from the lower layer decoder using the upper layer code to recover the source information.

According to another aspect of the present invention, there is provided a method of decoding data encoded with source information, the method comprising: a lower layer decoding step of decoding data using a lower layer code by a lower layer decoder; A cyclic redundancy check step of performing a cyclic redundancy check on each bit of data decoded by a lower layer decoder; A reliability evaluation step of evaluating a reliability of a bit for which the lower layer decoder has not passed the cyclic redundancy check; A bit output step of outputting a bit whose reliability is equal to or higher than a predetermined reliability threshold value and a bit that has passed a cyclic redundancy check among the bits for which the lower layer decoder has not passed the cyclic redundancy check; And decoding the bits output from the lower layer decoder using an upper layer code by an upper layer decoder.

According to another aspect of the present invention, there is provided a system for transmitting and receiving data, comprising: an upper layer encoder for encoding source information using upper layer codes and outputting bits; A transmitter for transmitting encoded data, the encoder comprising: a transmitter for transmitting encoded data; And decodes the received coded data using a lower layer code and performs a cyclic redundancy check on each bit of the decoded coded data to determine whether reliability among the bits that have not passed the cyclic redundancy check exceeds a predetermined reliability threshold Layer decoders for outputting bits having a value equal to or greater than a predetermined value and bits passed through a cyclic redundancy check, and an upper layer decoder for decoding the bits output from the lower layer decoder using an upper layer code to recover source information And a data transmission / reception system.

As described above, according to the present invention, it is possible to transmit and receive data with a smaller error rate in a given channel environment. In addition, the number of bits of the total received data required to achieve the same target error rate can be considerably reduced, and it is possible to reduce the transmission and reception of data of the same bit number. In addition, since less information can be processed, the power consumption can be reduced.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals even though they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the term does not limit the nature, order or order of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; may be "connected," "coupled," or "connected. &Quot;

1 is an exemplary view showing an FEC of an upper layer and an FEC of a physical layer.

FIG. 1 shows interworking of codes between an upper layer and a physical layer. Referring to FIG. 1, source information, that is, information of m bits to be transmitted is arranged in an array (an array denoted by A block in FIG. 1) divided into several columns and rows. For example, if there is 5,000 bits of information, it is relocated to a matrix of 50 bits by 100 bits, where 100 bits is the number of bits in each row. The information of 100 bits in each row is encoded by a rateless code to generate parity information having an arbitrary number. In Fig. 1, the bit stream of each row shown in the B block is parity information.

At this time, the number of parity bits that can enter each row of the B block is not predetermined. If the channel environment is bad, more parity information can be generated, and if the channel environment is good, the original information can be restored with only a small number of parity information. The code for generating a predetermined number of parity bits in this way is called a rateless code. At this time, the rateless code is applied to each row separately.

The parity information generated by applying the rateless code to each row of the original source information shown in the A block is encoded again by the FEC of the physical layer. That is, the physical layer FEC is applied to bits in each column shown in the B block to generate a parity code. The generated parity code is represented by C block in FIG. Turbo code or LDPC code (Low-Density Parity-Check Code) is used as the physical layer FEC. After the physical layer FEC is applied to each column, bits of each column in the C block are transmitted at a predetermined time. In this case, when only the parity bit in the C block is transmitted, it is called a non-systematic code, and when the information in the B block and the information in the C block are transmitted together, it is called a systematic code . Systematic code is used in many cases. The unit to be transmitted is a column of C or B and C blocks. That is, the bits in one column are transmitted per slot.

The receiver decodes the transmitted data. That is, when a physical layer decoder receives a row of C or B and C blocks, it starts decoding. At this time, the transmitted data is deformed due to various reasons such as noise, interference, fading, etc., and the received data is not the same as the transmitted data. Recovering the original source information from the transmitted data (i.e., restoring the bits of the B block) is called decryption. The information decoded by the physical layer decoder is transferred to a Rateless Code Decoder. At this time, when decryption is normally unsuccessful in the physical layer decoder, all bits in the column are regarded as unsuccessful in decryption and are not transmitted to the rateless code decoder. The rateless code decoder receives only decoded bits in the physical layer decoder, and uses the decoded bits to recover original source information. The rateless code decoder is performed separately for each row in the A and B blocks.

In an embodiment of the present invention, some information can be utilized even when the physical layer decoder does not completely decode the information. If decoding in the physical layer decoder is not perfect, some bits are error free and some bits are error free. At this time, if some bits are found to be error free, they can be used for decoding in a rateless code decoder. In this way, the rateless code decoder obtains information on more bits, and can decode at an earlier time. At this time, it becomes important to distinguish in the physical layer decoder whether certain bits are error-free and which bits are likely to be erroneous. Although it is impossible to completely distinguish which bits are likely to be erroneous in the physical layer decoder, it is possible to distinguish very precisely. To this end, the proposed technique uses reliability information generated when a physical layer decoder performs decoding.

A turbo code is mainly used as a physical layer code used in a physical layer decoder. A turbo code typically consists of two convolutional codes and an interleaver.

2 is an exemplary view showing a turbo code.

and u is k-bit input information to be transmitted. G ₀ and G ₁ are convolutional codes with a rate of -1. That is, when each bit is input, G ₀ is a function of the current input bit, which is the current input bit, and all past input bits that were input in the past, to produce the current output bit, which is the current output bit. G ₁ also plays a similar role. There is a random interleaver p between G ₀ and G ₁ . The interleaver p randomly permits k bits of input information to generate k bits of output. Thus, the outputted information of k bits becomes the input of G ₁ .

Once this is done a total of 3k bits of the output k of the original information bits u k and a bit of the G ₀ v ₍₀₎ and the output of G ₁ k bits of v (1) is output. When it arrives at the receiver through the channel, the receiver receives 3k bits of noise-added data. As described above, if the amount of added noise is not very large, more than 3 k bits of the original k bits are received, so that the original k bits of information can be restored by using additional information (parity information) of 2 k bits . The coding rate at this time, that is, the number of bits of the information to be transmitted divided by the number of bits to be transmitted is 1/3. A value 1/3, which is a value obtained by dividing the number of bits of data to be transmitted by the number of bits to be transmitted, can be made 1/2 by performing a process called puncturing. That is, if v (0) and v (1) are not transmitted while alternating one bit at a time, the total number of bits to be transmitted is 2k and the coding rate can be reduced to 1/2.

3 is an exemplary diagram illustrating a process of decoding a turbo code.

In Fig. 3, Lc is a constant depending on the channel, and y is a vector received from the channel. Assuming that each bit is mapped to +1 or -1 when 3k bits are transmitted on the channel, then y = x + z, where x is a vector of 3k bits and z is a 3k noise vector.

FIG. 3 shows a decoder block corresponding to two convolutional codes G ₀ and G ₁ . In the block on the left, convolutional code decoding corresponding to G ₀ is performed. At this time. L (0) is the log likelihood ratio (LLR) for the original information of k bits, that is, log [p (xi = 1) / p (xi = -1)] Is calculated from the first decoder. Here, xi is the i-th bit of x. Similarly, L (1) is the LLR for the original information calculated from the second decoder. The L (0) vector is generated by subtracting the Lcy value received from the channel and subtracting the extrinsic information Le (1) from the other decoder from the inverse permutation (pi ^-1 ). This is the extrinsic information that the first decoder delivers to the second decoder. The extrinsic information is replaced and input to the second decoder.

In the second decoder, decoding is performed in a manner similar to the first decoder. As described above, when the decoding is repeated while repeating several loops, original information can be restored more and more accurately. Typically, about ten iterations are performed. At this time, after 10 iterations, the original data can be restored based on the value of L (0). That is, if the i-th element of L (0) is positive, xi is decoded to +1, and if it is negative, it is decoded to -1.

However, there is no guarantee that the decoded bits are the same as the original bits. In order to accurately determine whether decryption is successful, a conventional CRC (Cyclic Redundancy Check) is used as described with reference to FIG. 5 in the following process. That is, assuming that a 32-bit CRC is used, (k-32) bits among the k bits of each row include bits to be transmitted (i.e., parity bits generated in the Raptor Code) The 32 bits contain the CRC bits for this (k-32) bits. As shown in Fig. 5, the physical layer code generates parity bits (k bits of the number of parity bits if the rate is 1/2) with respect to k bits.

4 is an exemplary view showing a rateless code.

In FIG. 4, the information bits correspond to the A block shown in FIG. 1, and the parity bits correspond to the B block shown in FIG. The code shown in FIG. 4 is one rateless code in the A block and the B block. A rateless code is called a rateless code for generating an arbitrary number of parity bits using m input bits. 4, a circular node is referred to as a variable node, and a rectangular node is referred to as a parity check node. The parity check node computes the sum of the parities of several variables.

FIG. 5 is a diagram illustrating a process of using partially decoded information according to an exemplary embodiment of the present invention. Referring to FIG.

If the decoding is successfully performed in the physical layer decoder and passes the CRC, all bits are considered to be decoded with 100% reliability. The probability that a bad bit will pass a CRC is very small, about 10 ^-10 , so it is not a concern. However, if an erroneous bit passes the CRC, a concealing method may be used in which the upper layer restores the original information in various ways or hides the loss of information. Bits that have not passed the CRC are typically discarded and are not delivered to the higher layer hierarchical rate decoder.

In one embodiment of the present invention, a bit having a high reliability among the discarded bits is determined by performing hard decision in an upper layer, and the bit value is determined and transmitted. At this time, if a wrong bit value is transmitted, only bits with high reliability are transmitted because it may affect the decoding process following the wrong bit value. As described above, when the values are received for the additional bits, more bits can be decoded in the upper layer, and a plurality of bits, which are less reliable in the B block due to the decoded bits, Values can be determined. As described above, when the reliability of a certain number of bits in the B block is increased by the upper layer decoder, the physical layer decoder can perform decoding again, and from this, a bit that can be decoded with high reliability by the physical layer decoder The number will increase more. As described above, by repeatedly exchanging additional information between the rateless code decoder and the physical layer decoder, more bits can be restored as a result.

At this time. One additional thing that can be done is that the reliability threshold of the bit that is considered to be decoded successfully by the physical layer decoder can be gradually lowered as the number of iterations increases. Here, how the reliability threshold value is reduced as the number of repetition of decoding is increased can be implemented by a table reference method.

6 is an exemplary diagram illustrating an operational flow according to an embodiment of the present invention.

The reliability of each bit can be expressed by the absolute value of the log likelihood ratio (LLR) of the corresponding bit. That is, the absolute value of the i-th log likelihood ratio of L (0) represents the reliability of xi. At this time, the turbo decoding is performed intermittently in the usual Log-MAP or Max-Log-MAP method. Since the rateless code decoding assumes only erasure, the much simpler message passing- (Message Passing Iterative Decoding). That is, one of three values of 0, 1, or erasure is transmitted between the parity check node and the variable node as a message.

The above embodiment of the present invention described above with reference to FIGS. 1 to 6 can be generalized as another embodiment of the present invention described below.

FIG. 7 is a block diagram of a data transmission / reception system according to another embodiment of the present invention.

The data transmission / reception system 700 according to another embodiment of the present invention may include a transmitter 710 and a receiver 720. The data transmission / reception system 700 may be a wired / wireless communication system, and the wired / wireless communication system may include a high speed downlink packet access (HSDPA) system, a CDMA2000 1x-EV-DO system, a CDMA2000 1x-EV- Voice system, an IEEE 802.16e system, a 3GPP MBMS (Multimedia Broadcast Multicast Service) system, and a wired communication system such as the Internet and an intranet.

The transmitter 710 is a device that transmits data in a wire / wireless communication system. Receiver 720 refers to a device that receives data in a wire / wireless communication system. For example, when the wired / wireless communication system is implemented as an HSDPA system, the transmitter 710 may be implemented as a Node-B or a Radio Network Controller (RNC) ) Or the like.

The transmitter 710 also encodes the bits output from the upper layer encoder 712 using a lower layer code and an upper layer encoder 712 that encodes source information and outputs bits using an upper layer code, And transmits the encoded data to the receiver 720. The receiver 720 decodes the encoded data.

The receiver 720 receives the encoded data, decodes the encoded data received from the transmitter 710 using the lower layer code, performs CRC on each bit of the decoded encoded data, and outputs a bit that has not passed through the CRC A lower layer decoder 722 for outputting a bit whose reliability is greater than or equal to a predetermined reliability threshold value and a bit passed through the CRC and a bit output from the lower layer decoder 722 using an upper layer code are decoded And an upper layer decoder 724 for restoring original source information.

Here, when the wired / wireless communication system is implemented as a 3GPP MBMS system, the source information encoded by the transmitter 710 and restored by the receiver 720 may be broadcast data, and the transmitter 710 and the receiver 720 may be wireless It is possible to transmit and receive encoded data through a channel.

In addition, the receiver 720 may be implemented as a decoding device that decodes the encoded data of the source information, except for a communication device for performing communication with the transmitter 710. [ In this case, the receiver 720 may include a lower layer decoder 722 and an upper layer decoder 724, and the lower layer decoder 722 may decode the encoded data using a lower layer code, The upper layer decoder 724 may output the bits output from the lower layer decoder 722 using the upper layer code, and output the bits output from the lower layer decoder 722 to the lower layer decoder 722. The upper layer decoder 724 may output a bit whose reliability of each bit of the decoded data is greater than or equal to a predetermined reliability threshold. The original source information can be restored.

Here, the lower layer decoder 722 may be a physical layer decoder, and the upper layer decoder 724 may be a rateless code decoder. Further, the lower layer code may be a turbo code, and the upper layer code may be a rateless code.

Also, the lower layer decoder 722 decodes the encoded data using the lower layer code to perform CRC on each bit generated, and determines that the bit passed through the CRC is a bit whose reliability is equal to or higher than a preset threshold value The CRC is performed for each bit generated by decoding the encoded data using the lower layer code, the reliability of the bit that does not pass through the CRC is evaluated, and the reliability of the bit that does not pass through the CRC is compared with a predetermined reliability threshold Bit or more can be output.

In addition, the lower layer decoder 722 may perform hard decoding on bits having a reliability higher than a predetermined reliability threshold value among the bits that have not passed through the CRC, and may determine and output a bit value. Here, the reliability may be an absolute value of the log likelihood ratio of each bit of the decoded data.

8 is a flowchart illustrating an encoding method according to another embodiment of the present invention.

The lower layer decoder 722 decodes the data using the lower layer code (S810), and performs CRC on each bit of the decoded data (S820). Here, performing CRC on each bit of the decoded data may be to evaluate the reliability for each bit. This is because the bit passed through the CRC among the bits of the data decoded by the lower layer decoder 722 can be regarded as having 100% reliability. In practice, any bit of decoded data is decoded incorrectly, but the probability of passing the CRC is very small, about 10 ^-10 , so it is not a concern. Accordingly, the lower layer decoder 722 can determine that the reliability is not less than a predetermined reliability threshold value without evaluating the reliability of the bit passed through the CRC.

On the other hand, in the normal decoding, the CRC is performed on each bit of the decoded data. As a result, the bit that has not passed the CRC is discarded without being outputted to the upper layer decoder 724. It is impossible to guarantee whether or not the corresponding bit is correctly decoded. However, in one embodiment of the present invention, the reliability of a bit that does not pass the CRC is evaluated, and a bit having a reliability higher than a certain level is output to an upper layer decoder 724 so that it can be more accurately decoded.

For this, the lower layer decoder 722 evaluates the reliability of the bits that have not passed the CRC (S830), and outputs a bit whose reliability exceeds a predetermined reliability threshold value and a bit that passes the CRC among the bits that have not passed the CRC (S840). The upper layer decoder 724 decodes the bit output from the lower layer decoder 722 using the upper layer code (S850).

In this way, the bits output from the upper layer decoder 724 may be restored as the source information. However, as described later, the decoding process is performed through interlocking between the lower layer decoder 722 and the upper layer decoder 724 It can be repeated. That is, the lower layer decoder 722 performs steps S810 to S850 again on the decoded bits output from the upper layer decoder 724, and the upper layer decoder 724 is performed again, It is possible to decode the bits outputted from the upper layer code by using the higher layer code. Further, the lower layer decoder 722 and the different layer decoder 724 can repeat this process continuously, but they can repeat only the predetermined maximum number of repetitions. That is, each time the lower layer decoder 722 repeats steps S810 to S850, it is determined whether or not the number of iterations is greater than a predetermined maximum number of iterations, thereby determining whether to repeat the operations.

The upper layer decoder 724 decodes the bits transmitted from the lower layer decoder 722 (bits having a relatively lower reliability than the bits passing through the CRC) to increase the reliability of the bits. The lower layer decoder 722 can decode the lower layer decoder 722 with higher reliability as the number of iterations increases by repeating the decoding process again by the lower layer decoder 722 and again by the upper layer decoder 724 The number of bits increases and ultimately the accuracy of decoding can be further improved.

Further, the lower layer decoder 722 may reduce the predetermined reliability threshold value by a preset value each time it repeatedly performs the steps S810 to S850. That is, since the reliability of the bit increases as the number of times of repetition increases, the lower layer decoder 722 can reduce the preset reliability threshold value by a predetermined value.

According to the embodiment of the present invention described above, a lower error rate can be achieved in a given channel environment. In addition, the number of total received data blocks needed to achieve the same target error rate can be significantly reduced. Less error rate means less data loss, and reducing the total number of received data blocks means less time to receive the same data, and because less information can be processed, .

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. That is, within the scope of the present invention, all of the components may be selectively coupled to one or more of them. In addition, although all of the components may be implemented as one independent hardware, some or all of the components may be selectively combined to perform a part or all of the functions in one or a plurality of hardware. As shown in FIG. The codes and code segments constituting the computer program may be easily deduced by those skilled in the art. Such a computer program can be stored in a computer-readable storage medium, readable and executed by a computer, thereby realizing an embodiment of the present invention. As the storage medium of the computer program, a magnetic recording medium, an optical recording medium, a carrier wave medium, or the like may be included.

Furthermore, the terms "comprises", "comprising", or "having" described above mean that a component can be implanted unless otherwise specifically stated, But should be construed as including other elements. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as predefined terms, should be interpreted to be consistent with the contextual meanings of the related art, and are not to be construed as ideal or overly formal, unless expressly defined to the contrary.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is possible to transmit and receive a small error rate and considerably reduce the number of bits of the total received data required to achieve the same target error rate so that a very useful invention to be.

1 is an exemplary view showing an FEC of an upper layer and an FEC of a physical layer,

Fig. 2 is an illustration showing a turbo code,

3 is a diagram illustrating a process of decoding a turbo code,

4 is an illustration showing a rateless code,

5 is a diagram illustrating a process of utilizing partially decoded information according to an embodiment of the present invention.

6 is an exemplary diagram illustrating an operational flow according to an embodiment of the present invention;

FIG. 7 is a block diagram schematically showing a data transmission / reception system according to another embodiment of the present invention.

8 is a flowchart illustrating an encoding method according to another embodiment of the present invention.

Description of the Related Art

710: Transmitter 712: Upper layer coder

714: Lower layer encoder 720: Receiver

722: Lower layer decoder 724: Upper layer decoder

Claims (14)

An apparatus for decoding data encoded with source information, A lower layer decoder for decoding the data using a lower layer code, and outputting a bit whose reliability of each bit of the decoded data is greater than or equal to a predetermined reliability threshold value; And An upper layer decoder for decoding the bits output from the lower layer decoder using an upper layer code and restoring the source information, And decodes the decoded data. The method according to claim 1, Wherein the lower layer decoder is a physical layer decoder, and the upper layer decoder is a rateless code decoder. The method according to claim 1, Wherein the lower layer code is a turbo code and the upper layer code is a rateless code. The apparatus of claim 1, wherein the lower layer decoder comprises: And performs a cyclic redundancy check on each of the bits to determine that the bits exceeding the cyclic redundancy check are bits having a reliability higher than or equal to a preset threshold value. The apparatus of claim 1, wherein the lower layer decoder comprises: Wherein the deciding unit decides to output a bit whose reliability is equal to or greater than the predetermined reliability threshold by performing a cyclic redundancy check on each bit and evaluating reliability of a bit that has not passed the cyclic redundancy check, . 6. The apparatus of claim 5, wherein the lower layer decoder comprises: Wherein the decoding unit performs hard decision on bits having the estimated reliability value equal to or greater than the preset reliability threshold value to determine and output a bit value. 2. The method of claim 1, And the absolute value of the log likelihood ratio of each bit of the decoded data. A method of decoding data encoded with source information, A lower layer decoding process in which a lower layer decoder decodes the data using a lower layer code; A cyclic redundancy check process in which the lower layer decoder performs a cyclic redundancy check on each bit of the decoded data; A reliability evaluation process of evaluating the reliability of bits for which the lower layer decoder has not passed the cyclic redundancy check; A bit output step of outputting a bit whose reliability is equal to or higher than a predetermined reliability threshold value and a bit that has passed the cyclic redundancy check among the bits for which the lower layer decoder has not passed the cyclic redundancy check; And A process of decrypting a bit output from the lower layer decoder using an upper layer code by an upper layer decoder And decodes the decoded data. 9. The decoding method according to claim 8, Further comprising an iterative process of the lower layer decoder repeatedly performing the layer decoding process and the bit output process on the decoded bits from the upper layer decoder. 10. The decoding method according to claim 9, Further comprising a reliability threshold decreasing step of decrementing the predetermined reliability threshold by a predetermined value each time the lower layer decoder repeats the layer decoding process or the bit outputting process. 10. The decoding method according to claim 9, Further comprising determining whether to repeat the decoding process by determining whether the number of times that the lower layer decoder has repeated the layer decoding process or the bit output process exceeds a preset maximum number of iterations Characterized in that: delete delete delete

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