KR101513649B1 - Display substrate and manufacturing method thereof - Google Patents

Abstract

The display substrate includes a transistor layer, a color filter, a capping layer, a light shielding member, and a pixel electrode. The transistor layer is formed on a base substrate on which a pixel region is defined, and includes a transistor. The color filter is disposed in the pixel region above the transistor layer. The capping layer is formed so as to cover the upper surface and the side surface of the color filter. The light shielding member is disposed on the capping layer between the different color filters, and blocks light. The pixel electrode is disposed on the capping layer in the region where the color filter is formed, and the end overlaps with the light shielding member.

Capping layer, color filter, light shielding member, holding member, etching process

Description

[0001] DESCRIPTION [0002] DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME [0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a display substrate and a method of manufacturing the same, and more particularly, to a display substrate used in a liquid crystal display apparatus and a method of manufacturing the same.

In general, a liquid crystal display panel includes an array substrate on which thin film transistors are arrayed, and a liquid crystal layer interposed between the array substrate and the color filter substrate, including a color filter substrate on which color filters are formed facing the array substrate.

A liquid crystal display panel having a high transmittance structure employing a color-filter on array (COA) substrate having a color filter formed on an array substrate has recently been developed. The COA substrate is formed by forming a thin film transistor layer including a thin film transistor on a base substrate, forming a color photoresist layer on the thin film transistor layer, and patterning the color photoresist layer to form a color filter in a pixel region . The COA substrate is completed by forming a pixel electrode electrically connected to the thin film transistor in a pixel region where the color filter is formed. And a common electrode and a light shielding member facing the pixel electrode are formed on the counter substrate facing the COA substrate.

Recently, a black matrix on array (BOA) substrate has been developed which forms the light shielding member on the COA substrate in order to prevent the occurrence of alignment errors in the process of bonding the COA substrate and the counter substrate on which the light shielding member is formed .

The defect of the BOA substrate due to the alignment error with the counter substrate can be reduced. However, since the color filter and the light shielding member are formed on the array substrate on which the thin film transistor layer is formed, and the column spacer for maintaining the gap with the counter substrate is formed, the manufacturing process is complicated.

Accordingly, it is an object of the present invention to provide a display substrate for simplifying a manufacturing process and improving reliability of a product.

Another object of the present invention is to provide a method of manufacturing the display substrate.

According to an aspect of the present invention, a display substrate includes a transistor layer, a color filter, a capping layer, a light shielding member, and a pixel electrode. The transistor layer is formed on a base substrate on which a pixel region is defined, and includes a transistor. And the color filter is disposed in the pixel region on the transistor layer. The capping layer is formed to cover the upper surface and the side surface of the color filter. The light shielding member is disposed on the capping layer between the different color filters, and blocks light. The pixel electrode is disposed on the capping layer in the region where the color filter is formed, and the end portion overlaps with the light shielding member. The display substrate further includes a retaining member that is spaced from the substrate facing the base substrate and disposed over the capping layer in the region where the color filter is formed. The holding member is made of the same material as the light shielding member. The light shielding member is inserted into the opening defined by the color filters.

The transistor layer includes a gate wiring, a first transistor connected to the first data wiring intersecting the gate wiring, and a second transistor connected to the gate wiring and the second data wiring adjacent to the first data wiring. The pixel electrode includes a first sub-electrode electrically connected to the first transistor and a second sub-electrode electrically connected to the second transistor.

According to another aspect of the present invention, a method of manufacturing a display substrate includes forming a transistor layer including a transistor on a base substrate on which a pixel region is defined. A color filter is formed in the pixel region on the transistor layer. A capping layer is formed on the base substrate on which the color filter is formed to cover the top and side surfaces of the color filter. A light shielding member is formed on the capping layer formed in the region between the different color filters. And the pixel electrode is disposed on the capping layer in the region where the color filter is formed and the end overlaps with the light shielding member. In the step of forming the light shielding member, a gap is maintained between the substrate facing the base substrate and a holding member disposed on the capping layer in the region where the color filter is formed.

In the step of forming the color filter, a first opening is formed in a boundary region of different color filters. The step of forming the shielding member may include forming a shielding material on the base substrate on which the capping layer is formed, forming a slit portion in a region corresponding to the first opening portion, The light shielding material is patterned by the light shielding member and the holding member, respectively.

Wherein the step of forming the transistor layer includes forming a gate wiring on the base substrate, forming a gate insulating layer of the base substrate on which the gate wiring is formed, forming a gate insulating layer on the base substrate on which the data wiring A source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, and a protective insulating layer is formed on the base substrate on which the drain electrode is formed. In the step of forming the color filter, a second opening exposing the protective insulating layer in an area where the drain electrode is formed is further formed.

And forming the contact hole by etching the protective insulating layer and the capping layer formed in the region corresponding to the second opening. The contact hole is formed before forming the light shielding member.

According to such a display substrate and its manufacturing method, it is possible to prevent the holding member from being damaged by forming the contact hole before forming the holding member. Also, the manufacturing process can be simplified by forming the light shielding member formed in the boundary region between the color filters and the holding member by the same material and the same process.

Hereinafter, preferred embodiments of the display apparatus of the present invention will be described in more detail with reference to the drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged from the actual size in order to clarify the present invention. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, where a section such as a layer, a film, an area, a plate, or the like is referred to as being "on " another section, this includes not only the case where it is" directly on "another part, On the contrary, where a section such as a layer, a film, an area, a plate, etc. is referred to as being "under" another section, this includes not only the case where the section is "directly underneath"

1 is a plan view of a display panel according to an embodiment of the present invention. 2 is a cross-sectional view taken along line I-I 'of FIG.

1 and 2, the display panel includes a display substrate 100a, a counter substrate 200, and a liquid crystal layer 300. [ The counter substrate 200 includes a common electrode layer 210.

The display substrate 100 includes a base substrate 101. The base substrate 101 includes a plurality of pixel regions.

A transistor layer TL, color filters 161 and 162, a capping layer 167, a light shielding member 181, a holding member 183 and pixel electrodes PE1 and PE2 are formed on the base substrate 101 do.

The transistor layer TL includes a gate metal pattern formed on the base substrate 101, a gate insulating layer 120, channel patterns 131 and 132, a source metal pattern, and a protective insulating layer 150. The gate metal pattern includes a plurality of gate lines GLn (n is a natural number), gate electrodes GE1 and GE2, and a storage line STL. The n-th gate wiring GLn is formed extending in the first direction. The gate electrodes GE1 and GE2 are formed integrally with the nth gate line GLn. The gate electrode GE1 of the first transistor TR1 and the gate electrode GE2 of the second transistor TR2 are respectively defined in the nth gate line GLn. The storage line STL may be formed parallel to the n-th gate line GLn as shown in the figure.

The gate insulating layer 120 is formed on the gate metal pattern. The channel patterns 131 and 132 are formed corresponding to the region where the source metal pattern is formed. For example, the first channel pattern 131 is formed corresponding to the region where the source and drain electrodes SE1, SE2, DE1, DE2 are formed on the gate electrodes GE1, GE2, The data lines 132 are formed corresponding to the regions where the data lines DLm-2, DLm-1, DLm, DLm + 1, and DLm + 2 are formed. Each of the first and second channel patterns 131 and 132 includes an active layer and an ohmic contact layer.

The source metal pattern includes a plurality of data lines DLm-2, DLm-1, DLm, DLm + 1 and DLm + 2, source electrodes SE1 and SE2 and drain electrodes DE1 and DE2 . The data lines DLm-2, DLm-1, DLm, DLm + 1, DLm + 2 extend in a second direction intersecting the n-th gate line GLn. The source electrodes SE1 and SE2 extend from the data lines DLm-2, DLm-1, DLm, DLm + 1 and DLm + 2, respectively, and are overlapped with the gate electrodes GE1 and GE2. do. The drain electrodes DE1 and DE2 overlap the gate electrodes GE1 and GE2 and are spaced apart from the source electrodes SE1 and SE2. A first contact hole C1 and a second contact hole C2 are formed at the ends of the drain electrodes DE1 and DE2 to be in contact with the pixel electrodes PE1 and PE2.

The protective insulating layer 150 is formed on the base substrate 101 on which the source metal pattern is formed. The protective insulating layer 150 protects the first channel pattern 131 and the source metal patterns of the exposed first and second transistors TR1 and TR2 from the outside.

The color filters 161 and 162 are formed on the pixel regions P1 and P2 on the base substrate 101 on which the transistor layer TL is formed. The color filter 161 has a first color and the second color filter 162 has a second color different from the first color. A first opening H1 for exposing the protective insulating layer 150 is formed in a boundary region between the color filters 161 and 162 having different colors. For example, the color filters 161 and 162 are provided between the mth data line DLm and the (m + 1) th data line DLm + 1, which are boundary regions of the pixel regions P1 and P2. The first opening H1 is formed. For example, the separation distance d between the color filters 161 and 162 is 0 占 퐉 <d? 15 占 퐉. Although not shown, the color filters 161 and 162 correspond to the regions where the first and second contact holes C1 and C2 and the storage line STL are formed, and the second openings H2 .

The capping layer 167 is formed to cover the color filters 161 and 162 to block the impurity ions generated from the color filters 161 and 162 and out-gassing. The capping layer 167 may be formed of silicon nitride, silicon oxide, or the like. For example, the capping layer 167 is formed to cover the top and side surfaces of the color filters 161 and 162.

The light blocking member 181 is formed by being inserted into the first opening H1 formed in the boundary region of the pixel regions P1 and P2. The light shielding member 191 separates the pixel regions P1 and P2 in which different color filters 161 and 162 are formed. The light blocking member 181 is formed of a light blocking material.

The holding member 183 is formed on the color filter 162 to maintain a gap between the display substrate 100a and the counter substrate 200. [ For example, the holding member 183 is formed on the color filter 162 corresponding to the n-th gate line GLn. Or the holding member 183 is formed corresponding to a region where the gate metal pattern and the source metal pattern are formed. The holding member 183 is formed of the same material as the light shielding member 181.

The pixel electrodes PE1 and PE2 are formed on the capping layer 167 corresponding to the pixel regions P1 and P2. As the pixel electrodes PE1 and PE2 are formed on the capping layer 167, the adhesion can be improved. As the adhesive force is improved, a fine pattern such as a micro slit pattern can be formed on the pixel electrodes PE1 and PE2.

For example, one end of the first pixel electrode PE1 overlaps with the light shielding member 181 overlapping the region where the mth data line DLm is formed. One end of the second pixel electrode PE2 overlaps with the light shielding member 181 overlapping the region where the (m + 1) th data line DLm + 1 is formed. Each of the first and second pixel electrodes PE1 and PE2 is divided into a first sub-electrode 171 and a second sub-electrode 172 for dividing a domain in which liquid crystals are arranged.

As shown in the figure, the first sub-electrode 171 and the second sub-electrode 172 may be patterned in a chevron shape. The first sub-electrode 171 is electrically connected to the drain electrode DE1 of the first transistor TR1 through the first contact hole C1. The second sub-electrode 172 is electrically connected to the drain electrode DE2 of the second transistor TR2 through the second contact hole C2.

3A to 3E are cross-sectional views illustrating a manufacturing process of the display substrate shown in FIG.

Referring to FIGS. 1 and 3A, a gate metal layer is formed on a base substrate 101. The gate metal layer is patterned into a gate metal pattern. The gate metal pattern includes the n-th gate line GLn, the gate electrodes GE1 and GE2, and the storage line STL. A gate insulating layer 120 is formed on the base substrate 101 on which the gate metal pattern is formed.

Referring to FIGS. 1 and 3B, a channel layer and a source metal layer are sequentially formed on a base substrate 101 on which the gate insulating layer 120 is formed. The channel layer and the source metal layer are patterned using a single mask. On the gate insulating layer 120, a source metal pattern and channel patterns 131 and 132 formed under the source metal pattern are formed.

The source metal pattern includes the data lines DLm-1 and DLm, the source electrodes SE1 and SE2, and the drain electrodes DE1 and DE2. The first channel pattern 131 is formed under the source electrodes SE1 and SE2 and the drain electrodes DE1 and DE2 and the second channel pattern 132 is formed under the data lines DLm- DLm.

A protective insulating layer 150 is formed on the base substrate 101 on which the source metal pattern is formed. Accordingly, the transistor layer TL is formed in the display region DA.

Referring to FIGS. 1 and 3C, the color filters 161 and 162 are formed on the base substrate 101 on which the transistor layer TL is formed. For example, a color filter 161 having a first color is formed first in the first pixel region P1, and a color filter 162 having a second color is formed sequentially in the first pixel region P2 . A first opening H1 in which the color filters 161 and 162 are removed is formed in a boundary region between the first and second pixel regions P1 and P2 in which different color filters 161 and 162 are formed . That is, the first opening H1 is elongated in the extending direction of the data lines DLm-1 and DLm.

The color filters 161 and 162 are provided with second openings H2 for exposing the protective insulating layer 150 in correspondence with the regions where the first and second contact holes C1 and C2 are formed .

Referring to FIGS. 1 and 3, a capping layer 167 is formed on a base substrate 101 on which the first and second openings H1 and H2 are formed. The capping layer 167 is formed to cover the color filters 161 and 162 to block the impurity ions and out-gassing generated from the color filters 161 and 162. The capping layer 167 is made of an inorganic material, and examples thereof include silicon nitride and silicon oxide.

Subsequently, the base substrate 101 on which the capping layer 167 is formed is etched to expose the drain electrodes DE1 and DE2 by removing the capping layer 167 and the protective insulating layer 150 Thereby forming the first and second contact holes C1 and C2.

1 and 3E, a light shielding layer 180 is formed on a base substrate 101 on which the first and second contact holes C1 and C2 are formed. The light shielding layer 180 is formed to a thickness enough to form a holding member 183 formed in the display area DA.

A mask 530 having a light transmitting portion 531, a light shielding portion 532 and a slit portion 533 is disposed on a base substrate 101 on which the light shielding layer 180 is formed. Of course, the mask 530 may have a semi-transparent portion that transmits some light instead of the slit portion 533 and absorbs or reflects some light.

The transparent portion 531 is disposed corresponding to a region where the holding member 183 is formed. The light-shielding portion 532 is disposed in a region where the light-shielding layer 180 is not formed, for example, a region where the pixel electrodes PE1 and PE2 are formed. The slit part 533 is disposed in a region where the light shielding member 181 is formed, that is, in a region where the first opening H1 is formed.

The light shielding layer 180 is patterned by the mask 530 into the light shielding member 181 and the holding member 183, respectively. When the first light blocking member 181 is formed, the holding member 183 having a light blocking pattern can be formed at the same time. Thus, the manufacturing process can be simplified.

Also, by using the mask 530 including the slit portion 533, the step between the light blocking member 181 and the adjacent color filters 161 and 162 can be reduced.

1 and 3F, a transparent conductive layer 170 is formed on a base substrate 101 on which the light shielding member 181 and the holding member 183 are formed. Examples of the transparent conductive layer include indium tin oxide (ITO), indium zinc oxide (IZO), and the like. The transparent conductive layer 170 is in contact with the drain electrodes DE1 and DE2 through the first and second contact holes C1 and C2 and is formed to be in direct contact with the capping layer 167. [ The transparent conductive layer 170 is superior in adhesion to the capping layer 167, which is the inorganic material, than organic materials such as the color filters 161 and 162.

The transparent conductive layer 170 is patterned by the pixel electrodes PE1 and PE2 formed in the pixel regions P1 and P2. For example, the first pixel electrode PE1 is formed in direct contact with the capping layer 167 formed in the first pixel region P1. One end of the first pixel electrode PE1 overlaps with the light shielding member 181 overlapping the region where the mth data line DLm is formed. Also, the second pixel electrode PE2 is formed in direct contact with the capping layer 167 formed in the second pixel region P2. One end of the second pixel electrode PE2 overlaps with the light shielding member 181 overlapping the region where the (m + 1) th data line DLm + 1 is formed. Each of the first and second pixel electrodes PE1 and PE2 is divided into a first sub-electrode 171 and a second sub-electrode 172 for dividing a domain in which liquid crystals are arranged.

As shown in the figure, the first sub-electrode 171 and the second sub-electrode 172 may be patterned in a chevron shape. The first sub-electrode 171 is electrically connected to the drain electrode DE1 of the first transistor TR1 through the first contact hole C1. The second sub-electrode 172 is electrically connected to the drain electrode DE2 of the second transistor TR2 through the second contact hole C2.

Therefore, the manufacturing process can be simplified by forming the light shielding member 181 and the holding member 183 by the same material and the same process. In addition, it is possible to prevent the holding member 183 from being etched by the etching process by forming the contact holes C1 and C2 in the process before the holding member 183 is formed. In addition, the pixel electrodes PE1 and PE2 are directly in contact with the capping layer 163 to form a fine pattern on the pixel electrodes PE1 and PE2.

Hereinafter, samples of various display substrates were manufactured and compared with the display substrates of the above embodiments. Sample 1 is a display substrate manufactured according to an embodiment of the present invention, and Sample 2 and Sample 3 are display substrates manufactured according to a comparative example for comparison with the embodiment of the present invention. The same reference numerals are given to the same components of the display substrate according to the above-described embodiments.

4 is a cross-sectional view of the display substrate according to Sample 2. Fig. The display substrate 100b according to the sample 2 shown in FIG. 4 sequentially forms the transistor layer TL and the color filters 161 and 162 on the base substrate 101 and then the light shielding member 181 ) And the holding member 183 were simultaneously formed. The capping layer 167 is formed on the base substrate 101 on which the color filters 161 and 162, the light shielding member 181 and the holding member 183 are formed. After the capping layer 167 is formed, the capping layer 167 and the protective insulating layer 150 are etched to form a contact hole C1. During the etching process for forming the contact hole C1, the capping layer 167 formed on the holding member 183 is removed. Then, the pixel electrodes PE1 and PE2 were formed.

That is, the display substrate 100b according to the sample 2 has the light shielding member 181 and the holding member 183 formed before the etching process in which the contact hole C1 is formed. A portion of the retaining member 183 is removed as the capping layer 167 formed on the retaining member 183 is removed during the etching process for forming the contact hole C1. The display substrate 100b according to the sample 2 can lower the liquid crystal filling property as the height of the holding member 183 decreases and can have a cell gap of a non-uniform liquid crystal layer.

5 is a cross-sectional view of the display substrate according to Sample 3; The display substrate 100c according to the sample 3 shown in FIG. 5 sequentially forms the transistor layer TL and the color filters 161 and 162 on the base substrate 101 and then the capping layer 167 ). Next, the capping layer 167 and the protective insulating layer 150 are etched to form the contact holes C1 and C2. After the contact hole C1 is formed, the pixel electrodes PE1 and PE2 are formed, and then the light shielding member 181 and the holding member 183 are formed.

That is, the display substrate 100c according to the sample 3 is formed after the light-shielding member 181 and the holding member 183 are formed by the pixel electrodes PE1 and PE2. As a result, the coupling capacitance increases as the distance between the data lines DLm and DLm + 1 and the pixel electrodes PE1 and PE2 becomes shorter than that of the embodiment and the sample 1. [ It is necessary to pattern the pixel electrodes PE1 and PE2 using a negative photoresist material in order to prevent a short defect between the pixel electrodes PE1 and PE2 in the spacing region between the color filters 161 and 162 .

The following Table 1 summarizes the characteristics of the display substrates according to Sample 1, Sample 2 and Sample 3.

As shown in Table 1, the display substrate 100b according to the sample 2 is formed in such a manner that the holding member 183 is formed before the etching process for forming the contact hole C1, There is a problem that the holding member 183 is damaged and a step is generated.

The coupling capacitance of the display substrate 100c according to the sample 3 increases as the distance between the data lines DLm and DLm + 1 and the pixel electrodes PE1 and PE2 becomes shorter, There is a problem in that it is vulnerable to the flattening between the color filters 161 and 162. As a result, in sample 3, display failure such as vertical cross-talk occurred. In addition, the display substrate 100c according to the sample 3 has a problem that remnants of the light shielding member 181 and the holding member 183 remain on the pixel electrodes 161 and 162 according to the process order.

On the other hand, it was confirmed that the display substrate 100a according to the sample 1 did not suffer from problems such as vertical crosstalk, residual light-shielding material, and damage to the holding member.

As described above, according to the embodiment of the present invention, the holding member can be formed after the etching process for forming the contact hole to prevent the holding member from being damaged by a subsequent process. Also, the manufacturing process can be simplified by forming the light shielding member formed in the boundary region between the color filters and the holding member by the same material and the same process. Also, since the capping layer is formed between the color filters and the pixel electrodes, the adhesion of the pixel electrodes can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

1 is a plan view of a display panel according to an embodiment of the present invention.

2 is a cross-sectional view taken along line I-I 'of FIG.

3A to 3E are cross-sectional views illustrating a manufacturing process of the display substrate shown in FIG.

4 is a cross-sectional view of the display substrate according to Sample 2. Fig.

5 is a cross-sectional view of the display substrate according to Sample 3;

Description of the Related Art

100a: display substrate 200: opposing substrate

300: liquid crystal layer 120: gate insulating layer

131, 132: channel pattern 150: protective insulating layer

161, 162: Color filter 167: Capping layer

171 and 172: First and second sub-electrodes PE1 and PE2:

181: Shielding member 183: Holding member

Claims (16)

delete delete delete delete delete Forming a transistor layer including a transistor on a base substrate on which a pixel region is defined; Forming a color filter in a pixel region on the transistor layer; Forming a capping layer on the base substrate on which the color filters are formed so as to cover upper and side surfaces of the color filters; Forming a light shielding member on the capping layer formed in an area between different color filters; And Forming a pixel electrode which is disposed on the capping layer in an area in which the color filter is formed and whose end overlaps with the light shielding member, Wherein the step of forming the light shielding member maintains a space between the substrate and the substrate facing the base substrate and forms a holding member disposed on the capping layer in an area where the color filter is formed, The light shielding member and the holding member are formed of the same material, Forming a first opening in a border region of different color filters in the forming of the color filter, The step of forming the light shielding member Forming a light shielding material on the base substrate on which the capping layer is formed; And The light shielding material is shielded by the light shielding member and the holding member by using a mask in which a slit portion is provided in an area corresponding to the first opening and a translucent portion is arranged corresponding to a region in which the holding member is formed, And patterning the substrate. delete delete delete delete 7. The method of claim 6, wherein forming the transistor layer comprises: Forming a gate wiring on the base substrate; Forming a gate insulating layer of the base substrate on which the gate wiring is formed; Forming a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, on a base substrate on which the gate insulating layer is formed; And And forming a protective insulating layer on the base substrate on which the drain electrode is formed. 12. The method of claim 11, wherein in forming the color filter And a second opening exposing the protective insulating layer in an area where the drain electrode is formed. 13. The method of claim 12, further comprising forming a contact hole by etching the protective insulating layer and the capping layer formed in a region corresponding to the second opening. 14. The method of manufacturing a display substrate according to claim 13, wherein the contact holes are formed before forming the light shielding member. 15. The method of claim 14, wherein the pixel electrode is in contact with the drain electrode through the contact hole. 16. The method of claim 15, wherein the pixel electrodes comprise a first sub-electrode and a second sub-electrode patterned to be spaced apart from each other.

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