KR101221207B1 - Symbol Timing Offset Synchronizing Apparatus Having Low Size and Design Method - Google Patents

Abstract

Disclosed are a symbol timing offset synchronizer having a low area structure and a design method thereof. The symbol timing offset synchronizer according to an embodiment of the present invention, in the symbol timing offset synchronizer, converts the direct filter structure into a predirect direct filter structure and then converts the filter coefficients of the predirect direct filter structure to a CSD (Canonic Signed Digit). Type, and the filter structure is redesigned based on the CSD type coefficients.

Description

Symbol Timing Offset Synchronizing Apparatus Having Low Size and Design Method}

The present invention relates to a symbol timing offset synchronizer having a low area structure, and more particularly, to a symbol timing offset synchronizer having a low area structure in a symbol timing offset synchronizer of an IEEE 802.11a WLAN, which is an OFDM communication method. And a design method thereof.

The basic principle of Orthogonal Frequency Division Multiplexing (OFDM) scheme is to divide a data stream having a high data rate into a large number of data streams having a low data rate, and transmit them simultaneously using a plurality of subcarriers. That is, OFDM is regarded as a special form of a multi-carrier transmission method in which data streams are simultaneously transmitted side by side on a plurality of sub-channels. Therefore, the OFDM technique is a "multiplexing technique" in terms of simultaneously transmitting a high-speed source data stream of one channel in multiple channels, and is a kind of "modulation technique" in terms of splitting and transmitting the multiple carriers. The waveforms of the subcarriers are orthogonal on the time axis, but overlapped on the frequency axis.

Recently, such an OFDM modulation scheme has been widely used in various wired and wireless data transmission systems. The OFDM system has a higher frequency utilization efficiency than the conventional single carrier transmission scheme, solves the inter symbol interference problem by using a plurality of subcarriers having orthogonal relation, and solves the guard interval. It can be used to achieve excellent performance even in a multipath fading environment.

However, the OFDM modulation scheme has a weak point in the synchronization algorithm. That is, carrier frequency offset due to carrier frequency mismatch between transmitter and receiver generates inter-carrier interference and prevents accurate synchronization of OFDM symbols, causing interference between symbols, thereby degrading system performance.

Therefore, in order to accurately demodulate an OFDM signal, symbol timing synchronization of a signal is very important. High-speed data transmissions generate multipath delays that are dozens of clock cycles in indoor wireless environments. Symbol timing offsets are caused by uncertainty in symbol arrival times and differences in the sampling frequency of the transmitter and receiver due to these multipath delays. The phase of the signal is rotated and a synchronization error of the fast fourier transform (FFT) window position causes interference between adjacent symbols. As the symbol synchronization error is a reason for greatly degrading the performance of the system, the symbol timing offset synchronization of the transmitting and receiving end must be preceded before the frequency offset synchronization block is performed in the receiving end of the OFDM system.

An embodiment of the present invention was devised to meet the above needs, and provides a symbol timing offset synchronizer having a low area structure and a design method thereof in a symbol timing offset synchronizer of an IEEE 802.11a WLAN, which is an OFDM communication scheme. For the purpose of

A symbol timing offset synchronizer according to an embodiment of the present invention for achieving the above object, in the symbol timing offset synchronizer, after converting the direct filter structure to a pre-direct filter structure, the filter of the pre-direct filter structure The coefficients are converted into CSD (Canonic Signed Digit) type, and the filter structure is redesigned based on the CSD type coefficients.

Preferably, the training symbols of the pre-direct type filter structure are represented by two's complement type and then converted into the CSD type.

Here, the pre-direct filter structure has four filters of r ₁ (n), r ₂ (n), i ₁ (n), and i ₂ (n), where r is real and i is imaginary ( image).

In this case, r ₁ (n) and i ₁ (n) may be the same filter, and r ₂ (n) and i ₂ (n) may be the same filter.

According to another aspect of the present invention, there is provided a method of designing a symbol timing offset synchronizer, the method comprising: converting a direct filter structure to a pre-direct filter structure; Converting filter coefficients of the pre-direct filter structure into a CSD type; And redesigning the filter structure based on the CSD type coefficients.

Advantageously, the method of designing the symbol timing offset synchronizer further comprises the step of expressing the training symbols of the pre-directed filter structure in two's complement form, the symbols represented by the two's complement form. On the basis of this, the CSD type can be converted.

Here, the pre-direct filter structure has four filters of r ₁ (n), r ₂ (n), i ₁ (n), and i ₂ (n), where r is real and i is imaginary ( image).

In this case, r ₁ (n) and i ₁ (n) may be the same filter, and r ₂ (n) and i ₂ (n) may be the same filter.

According to an embodiment of the present invention, a multiplier of a symbol timing offset synchronizer is designed with a filter concept, and then converted into a pre-direct structure in one step, and then the filter coefficients are converted into a CSD (Canonic Signed Digit) filter in two steps. A low area symbol timing offset synchronizer structure can be obtained.

1 is a diagram illustrating a preamble structure used in IEEE 802.11a.
2 is a block diagram illustrating a symbol timing offset and a frequency offset synchronizer for WLAN.
3 is a diagram illustrating an example of a structure of a symbol timing offset synchronizer.
4 is a diagram illustrating a pre-direct type overall structure of a symbol timing offset synchronizer according to an exemplary embodiment of the present invention.
5 shows an example of a low area r ₁ (n) filter structure redesigned according to an embodiment of the present invention.
6 is a diagram illustrating an example of a low area r ₂ (n) filter structure redesigned according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, a detailed description of known techniques well known to those skilled in the art may be omitted.

In describing the constituent elements of the present invention, the same reference numerals may be given to constituent elements having the same name, and the same reference numerals may be given thereto even though they are different from each other. However, even in such a case, it does not mean that the corresponding component has different functions according to the embodiment, or does not mean that the different components have the same function. It should be judged based on the description of each component in the example.

In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In addition, in describing the component of this invention, terms, such as 1st, 2nd, A, B, (a), (b), can be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; may be "connected," "coupled," or "connected. &Quot;

A packet generated at a transmitting end of a WLAN (IEEE 802.11a) OFDM wireless communication method is composed of a preamble, a header, and a payload, which is actually data to be transmitted. The structure of the preamble used in IEEE 802.11a is composed of 160 short training symbol and 160 long training symbol, as shown in FIG.

Here, the short training symbol is used for signal detection, AGC, diversity selection, timing synchronization, and coarse frequency offset estimation. In addition, the long training symbol is used for channel estimation and fine frequency offset estimation.

Short training sequences consist of 10 identical symbols from s ₁ to s ₁₀ , with each symbol consisting of 16 real parts and 16 imaginary parts. In addition, the long training sequences consist of two symbols, l ₁ and l ₂ , each of which consists of 64 real and 64 imaginary parts.

Symbol timing offset synchronization using a preamble is a task of accurately finding the starting point of a symbol by synchronizing timing using a training symbol having a periodic characteristic. This start point is accurately known to the frequency offset synchronizer block to match the timing of the symbols that are input to the FFT / IFFT block. A block diagram of a symbol timing offset synchronizer and a frequency offset synchronizer for WLAN using the preamble is shown in FIG.

As shown in FIG. 2, I and Q of the short training symbols s ₁ to s ₇ of the preambles are first input to the symbol timing offset synchronizer to obtain timing synchronization. To find the timing offset, calculate

[Equation 1]

In Equation 1, R _n is a correlation value calculated by the cross-correlation method, X _{15 -n} is the 15-nth value of the short training symbol known to the receiver in advance, * means conjugate, and is a received signal. The cross-correlation values of the received signals are obtained by complex multiplication of the received signal with 16 samples of the short training symbol. Accordingly, when Equation 1 is continuously performed on the received signal, the symbol timing synchronization can be accurately obtained because the correlation value is greatly increased at the time point when 16 repeated real and imaginary samples are finished. The operation of the short training symbol and the input signal known in advance in Equation 1 can be expressed by the following equation.

&Quot; (2) "

In Equation 2, the complex signal X is a short training symbol known to the receiver in advance, x _r represents a real value, and x _i represents an imaginary value. The complex signal Y is a received signal and y _r represents a real value and y _i represents an imaginary value. This equation yields a correlation value, which requires two real multiplication blocks and two imaginary multiplication blocks, requiring a total of four multiplication blocks. An example of the structure of a symbol timing offset synchronizer including four multiplication blocks is shown in FIG. 3.

In the symbol timing offset synchronizer structure of FIG. 3, y _r represents the real number of the received signal, y _i represents the imaginary number of the received signal, x _r0 represents the zeroth real sample value of the known training symbol, and there are 16 up to 15 times. _i0 is the zeroth imaginary sample value of the training symbol, with a total of 16 up to 15 times. The preamble input value is a complex number, and a real number y _r and an imaginary y _i are input for each multiplier part. The input signals are input to D0 for every clock that is a shift register and shifted to the shift register next to it. There are a total of 15 shift registers from D0 to D14. The values entered in each shift register are multiplied by x _r and x _i in each multiplier part for each clock.

The real multiplication calculation block of FIG. 3 calculates the sum of the value of Σy _r x _{r and} the value of Σy _i x _i , and the imaginary multiplication calculation block calculates the sum of the value of Σy _i x _{r and} the value of Σy _r x _i . Since the symbol timing synchronizer shown in FIG. 3 uses 64 multipliers, the implementation area becomes large. Therefore, in the symbol timing offset synchronizer structure shown in FIG. 3, a structure that can efficiently design a multiplier part and implement a low area needs to be proposed.

The structure of a symbol timing offset synchronizer according to an embodiment of the present invention designs a symbol timing offset synchronizer by using a filter concept. Approaching the filter concept, it can be seen as a filter of 16 filter coefficients of the short training symbol of the preamble. For example, the bottom area structure for the structure of FIG. 3 may be comprised of two stages: the pre-direct structure design step (step 1) and the CSD coefficient design step (step 2).

The symbol timing offset synchronizer, which uses 15 multipliers, receives a complex number of inputs every clock, which multiplies the short training symbols known to the receiver. The multiplier part consists of four parts, two real parts and two imaginary parts, and one multiplier part consists of 15 multipliers and 15 shift registers. Therefore, the total multiplier and shift registers are required 60 each, and the operation area is increased by performing 60 operations for each clock. This disadvantage is realized by converting the filter coefficients to CSD to reduce the partial product, and then using only the adder and shifter. In order to use this method, the pre-direct filter structure is used in one step. For example, the symbol timing offset synchronizer structure shown in FIG. 3 uses a direct form filter structure, which is converted into a transposed direct form filter structure shown in FIG. 4.

The structure of the symbol timing offset synchronizer as shown in FIG. 4 is composed of four filters. That is, it consists of four filters of r ₁ (n), r ₂ (n), i ₁ (n), and i ₂ (n). Here, the r ₁ (n) filter and the i ₁ (n) filter are the same filter because they have the same coefficient, and the r ₂ (n) filter and the i ₂ (n) filter are the same filter because they have the same coefficient. By converting such filter coefficients into CSD (Canonic Signed Digit) type, a low area for r ₁ (n) filter and r ₂ (n) filter can be realized.

First, the design of the low-area filter structure for the r ₁ (n) filter will be described.

 In order to design a low area structure using an adder with respect to the filter structure as shown in Fig. 4, the filter coefficients used can be converted into a CSD type. To convert to CSD type, training symbols are represented as 2's complement type and then converted to CSD type. This is because the implementation of the CSD type reduces the number of adders used. Table 1 is a 16-bit two's complement type representing the real value of the coefficient used in the filter.

[Table 1] 2's complement type of short training symbol (REAL) (r ₁ (n) block)

Table 1 shows the two's complement coefficients and the number of adders required. The number of 1s in Table 1 is proportional to the number of adders. That is, the number of 1 is proportional to the implementation area. In other words, using the two's complement coefficient has a relatively large number of ones, so the number of adders required increases, thereby increasing the implementation area.

Therefore, to reduce the number of adders, we convert them to coefficients of the CSD type. That is, the real and imaginary values of the short training symbol used as the filter coefficients are changed to the CSD type. Table 2 shows the two's complement coefficients of Table 1 in 16-bit CSD type.

[Table 2] CSD type of short training symbol (REAL) (r ₁ (n) block)

In the implementation of the r ₁ (n) filter, the use of CSD type filter coefficients can reduce the number of adders over the two's complement structure. The CSD type coefficients of Table 2 are expressed in order from x _r0 to x _r15 . The subscript r means real. Therefore, Table 2 is represented by the equation (3).

&Quot; (3) "

According to an embodiment of the present invention, the r ₁ (n) filter implementing Equation 3 using an adder is shown in FIG. 5. Referring to FIG. 5, the fifteen operation values may be calculated through shift, addition, and subtraction operations by receiving a signal from a preamble with a filter.

Next, the design of the low area filter structure for the r ₂ (n) filter will be described.

The two's complement type of the imaginary value of the short training symbol is shown in Table 3. The imaginary value is equal to the delay of 8 samples of the real value.

[Table 3] 2's complement type of short training symbol (IMAGE) (r ₂ (n) block)

Table 4 expresses the two's complement type of the imaginary value of the short training symbol shown in Table 3 in CSD form.

[Table 4] CSD type (r ₂ (n) block) of short training symbol (IMAGE)

If Table 4 is expressed as an equation, it is as shown in Equation 4.

&Quot; (4) "

According to an embodiment of the present invention, if the r2 (n) filter is implemented using Equation 4, it may be represented as shown in FIG.

An embodiment of the present invention has proposed a low-area structure for a symbol timing offset synchronizer block of an IEEE 802.11a WLAN, which is an OFDM communication scheme. By designing the multiplier of the symbol timing offset synchronizer in the filter concept and converting the filter coefficient into the CSD type filter in two stages, the structure of the low-area symbol timing offset synchronizer was obtained.

The present invention is not necessarily limited to these embodiments, as all the constituent elements constituting the embodiment of the present invention are described as being combined or operated in one operation. In other words, within the scope of the present invention, all of the components may be selectively operated in combination with one or more. In addition, although all of the components may be implemented as one independent hardware, some or all of the components may be selectively combined to perform a part or all of the functions in one or a plurality of hardware. As shown in FIG. In addition, such a computer program may be stored in a computer-readable medium such as a USB memory, a CD disk, a flash memory, etc., and read and executed by a computer, thereby implementing embodiments of the present invention. As the storage medium of the computer program, a magnetic recording medium, an optical recording medium, a carrier wave medium, or the like may be included.

Furthermore, all terms including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined in the Detailed Description. Terms used generally, such as terms defined in a dictionary, should be interpreted to coincide with the contextual meaning of the related art, and shall not be interpreted in an ideal or excessively formal sense unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the technical idea of the present invention. Accordingly, the scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

Claims (8)

In symbol timing offset synchronizer,
After converting the direct filter structure to the pre-direct filter structure, the filter coefficient of the pre-direct filter structure is converted into the CSD (Canonic Signed Digit) type, and the filter structure is redesigned based on the CSD type coefficient, (IEEE 802.11a) A packet generated at the transmitting end of the OFDM wireless communication method is composed of a preamble, a header, and a payload, which is data to be actually transmitted, and a packet of a preamble used in IEEE 802.11a. The structure consists of 160 samples of short training symbol and 160 samples of long training symbol, wherein the short training symbol is used for signal detection, AGC, diversity selection, timing synchronization, coarse frequency offset estimation, and the long training symbol is channel estimation. And fine frequency offset estimation, the short training sequences consist of 10 identical symbols from s ₁ to s ₁₀ , each symbol being 1 It consists of 6 real parts and 16 imaginary parts, and the long training sequences consist of two symbols, l ₁ and l ₂ , each symbol consisting of 64 real parts and 64 imaginary parts, 8-tap transposition direct type A symbol timing offset synchronizer characterized by a simplified structure and converting eight filter coefficients to a CSD type.
delete delete delete In the design method of the symbol timing offset synchronizer,
Converting the direct filter structure to a pre-direct filter structure;
Converting filter coefficients of the pre-direct filter structure into a CSD type; And
Redesigning the filter structure based on CSD type coefficients
Including;
A packet made at a transmitting end of a WLAN (IEEE 802.11a) OFDM wireless communication method is composed of a preamble, a header, and a payload, which is data to be actually transmitted, and a preamble used in IEEE 802.11a. The structure consists of 160 samples of Short training symbol and 160 samples of Long training symbol, wherein the Short training symbol is used for signal detection, AGC, Diversity selection, Timing synchronization, Coarse frequency offset estimation, and the Long training symbol is Channel Used for estimation and fine frequency offset estimation, the short training sequences consist of 10 identical symbols from s ₁ to s ₁₀ , each symbol consists of 16 real and 16 imaginary parts, and the long training sequences are l ₁ and l is composed of two symbols of each symbol ₂ is composed of a 64 real and 64 imaginary, 8-tap pre-like structure directly Simplified design and method of the symbol timing offset synchronizer, characterized in that to convert the eight filter coefficients to the CSD type. delete delete delete

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