KR101188259B1 - Semiconductor Memory Apparatus and Method of Testing the Same - Google Patents

Abstract

The semiconductor memory device may further include: a test mode controller configured to generate a test enable signal in response to a test mode setting signal and a read command; and generating first alignment data by firstly arranging first input data inputted in series. A first data alignment unit for transmitting to a data driver, a decoding unit for decoding the first alignment data in response to the test enable signal to generate a decoded signal, and a test execution for executing a preset test mode in response to the decoded signal And a second data alignment unit configured to align second input data serially input in response to the test enable signal in parallel to generate second alignment data, and to transmit the second alignment data to the second data driver.

Semiconductor memory device, test, collation

Description

Semiconductor Memory Apparatus and Method of Testing the Same

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device for improving the area efficiency and a test method thereof.

In general, in order to produce a semiconductor memory device, a test step is necessary because the simulation result used in the design and the operation of the chip used in the actual product may be different. Many types of tests have been conducted to reduce the failure rate of actual semiconductor memory devices. Each test is performed by coding a plurality of bits of test code input at this time, if the mode register set circuit defines a test mode. To this end, the semiconductor memory device includes a decoding unit, which is used to decode a plurality of test codes to execute a predetermined test mode.

In order to execute the test mode, the conventional semiconductor memory device had to include a plurality of signal transmission lines for transmitting a plurality of bits of test code to the decoding unit. However, such signal transmission lines are often required to be connected long in the structure of a general semiconductor memory device, and thus it is difficult to guarantee the stability of power supply of each signal line. In addition, as semiconductor memory devices are becoming more and more highly integrated, securing space to arrange such signal lines becomes increasingly difficult. As such, the transmission lines of a large number of test codes provided to execute the tests have reduced the density of the semiconductor memory device, and thus, the high integration implementation of the semiconductor memory device has faced limitations.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a semiconductor memory device and a test method thereof for improving area efficiency.

According to one or more exemplary embodiments, a semiconductor memory device may include a test mode controller configured to generate a test enable signal in response to a test mode setting signal and a read command; A first data alignment unit for generating first alignment data by aligning serially input first input data and transmitting the first alignment data to the first data driver; A decoder configured to decode the first alignment data in response to the test enable signal to generate a decoded signal; A test execution unit executing a preset test mode in response to the decoded signal; And a second data alignment unit for generating second alignment data by aligning second input data serially input in parallel in response to the test enable signal and transferring the same to the second data driver.

Also, a test method of a semiconductor memory device according to an embodiment of the present invention may include: a) enabling a test enable signal in response to a test mode setting signal; b) deactivating operations of other data alignment units, except for one data alignment unit, in response to the test enable signal; c) inputting a test code into the activated data alignment unit, decoding a signal output therefrom, and executing a test operation; And d) disabling the test enable signal in response to an input of a read command.

The semiconductor memory device and its test method of the present invention eliminate the difficulty of arranging a signal transmission line for executing the test mode by supporting a data input path, thereby supporting a high integration implementation. Create an effect.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

As illustrated, the semiconductor memory device according to an exemplary embodiment of the present invention may generate a test enable signal TEN in response to a test mode setting signal TMS and a read command RD. ; A first data alignment unit 20 for generating first alignment data DALN1 by arranging first input data DIN1 input in series in parallel; A first data driver 30 driving the first alignment data DALN1 and transferring the first alignment data DALN1 to a global data bus GIO; A decoding unit 40 decoding the first alignment data DALN1 to generate a decoding signal DEC in response to the test enable signal TEN; A test execution unit 50 executing a preset test mode in response to the decoding signal DEC; A second data alignment unit 60 generating second alignment data DALN2 by aligning second input data DIN2 input in series in parallel in response to the test enable signal TEN; And a second data driver 70 driving the second alignment data DALN2 and transferring the second alignment data DALN2 to the global data bus GIO.

Here, the test mode setting signal TMS is a signal that is enabled by the mode register set circuit defining the test mode. The read command RD is an internal read command generated in the semiconductor memory device by receiving an external read command. The test mode control unit 10 enables the test enable signal TEN when the test mode setting signal TMS is enabled, and the test enable signal TEN when the read command RD is enabled. Disable).

Each of the first input data DIN1 and the second input data DIN2 is serial data including a plurality of consecutive data bits. On the other hand, each of the first alignment data DALN1 and the second alignment data DALN2 is parallel data including a plurality of data bits to which each signal line is allocated. The first data aligner 20 and the second data aligner 60 each include a data input buffer (not shown), and when the test enable signal TEN is disabled, A general data input circuit for generating the first alignment data DALN1 and the second alignment data DALN2 by buffering and arranging the bits of the first input data DIN1 and the second input data DIN2 in parallel. Performs the operation of.

However, when the test enable signal TEN is enabled, the second data alignment unit 60 is deactivated. In this case, the first data alignment unit 20 maintains an activation state. Thus, the first data alignment unit 60 can act as a means for inputting a test code.

Here, although it is shown that one second data alignment unit 60 is provided, a plurality of second data alignment units 60 are actually provided. When the size of the semiconductor memory device is X4, three second data alignment units 60 are provided. When the size of the semiconductor memory device is X8, seven second data alignment units 60 are provided. When the size of the memory device is X16, 15 second data alignment units 60 are provided.

That is, in the semiconductor memory device, when the test mode is executed, all of the plurality of second data alignment units 60 are inactivated, and the first data alignment unit 20 maintains an activation state. At this time, when a plurality of test codes of a plurality of bits are continuously input from the outside of the semiconductor memory device through the first data alignment unit 20, the first data alignment unit 20 may operate the first data alignment unit 20. It is sorted as one sorting data DALN1.

The decoding unit 40 performs a decoding operation on the first alignment data DALN1 only when the test enable signal TEN is enabled. When the test enable signal TEN is enabled, the first alignment data DALN1 is a signal generated by aligning the test code. As a result, the decoding unit 40 transmits the data from the outside in the test mode. The decoded test code is decoded to generate the decoded signal DEC. Thereafter, the test execution unit 50 executes a test operation according to a logic value of the decoding signal DEC. The test executed by the test execution unit 50 may be various types, for example, there may be a sense amplifier enable timing test, a power level test, and a compression test.

As described above, in the semiconductor memory device according to the exemplary embodiment of the present invention, unnecessary signal lines are transmitted by transmitting test codes by using an input path of data in the test mode without separately providing lines for transmitting test codes. To improve area efficiency. In addition, in the test mode, the plurality of data alignment units to which the test code is not input may be deactivated, and only one data alignment unit to which the test code is input may be activated, thereby suppressing unnecessary power consumption. By such a configuration, the degree of integration of the semiconductor memory device can be improved.

FIG. 2 is a detailed configuration diagram of the test mode controller shown in FIG. 1.

As shown, the test mode control unit 10 includes: an inversion delay unit IDLY for inverting and delaying the test mode setting signal TMS; A first NAND gate ND1 for receiving the test mode setting signal TMS and the output signal of the inversion delay unit IDLY; A first inverter IV1 receiving an output signal of the first NAND gate ND1; A first transistor TR1 having a reset signal RST input to a gate terminal, an external supply power supply VDD applied to a source terminal, and a drain terminal thereof connected to a first node N1; A second transistor TR2 having the reset signal RST input to a gate terminal thereof and a drain terminal thereof connected to the first node N1; A third transistor TR3 having an output signal of the first inverter IV1 input to a gate terminal thereof, a drain terminal thereof connected to a source terminal of the second transistor TR2, and a source terminal of which is grounded; A second inverter IV2 receiving the read command RD; A fourth transistor TR4 having an output signal of the second inverter IV2 at a gate terminal thereof, an external supply power source VDD being applied at a source terminal thereof, and a drain terminal thereof connected to the first node N1; A third inverter IV3 receiving the potential formed at the first node N1 and outputting the test enable signal TEN; And a fourth inverter IV4 forming a latch structure with the third inverter IV3.

Here, the reset signal RST is a low enable signal. When the reset signal RST is enabled, the potential of the first node N1 becomes a high level. When the reset signal RST is disabled, the second transistor TR2 is turned on, but the potential of the first node N1 is maintained. The output signal of the first inverter IV1 is implemented in the form of a pulse signal that is enabled at a high level when the test mode setting signal TMS is enabled. In the state where the second transistor TR2 is turned on, When the output signal of the first inverter IV1 has a high level potential, the potential of the first node N1 transitions to a low level. Thus, the test enable signal TEN is enabled.

Thereafter, when the read command RD is enabled, the fourth transistor TR4 is turned on, so that the potential of the first node N1 is at a high level. Therefore, the test enable signal TEN is disabled.

That is, when the test mode setting signal TMS is enabled, the test mode control unit 10 enables the test enable signal TEN in response thereto, and then the read command RD is enabled. The operation of maintaining the enable period of the test enable signal TEN until a point in time is performed.

3 is a detailed block diagram of the first data alignment unit illustrated in FIG. 1.

As shown, the first data aligner 20 includes: a first data input buffer 210 for buffering the first input data DIN1 in response to a buffer enable signal BEN; A first data delay unit (220) for delaying data output from the first data input buffer (210); And a first pre-fetch for generating the first alignment data DALN1 by aligning the data transmitted from the first data delay unit 220 in parallel in response to a data strobe clock DQS and an internal clock CLK_INT. It includes a (Pre-fetch) unit 230.

By such a configuration, the first data alignment unit 20 buffers the first input data DIN1 when only the buffer enable signal BEN is enabled regardless of whether the test mode is implemented or not. Aligning in parallel may be performed to output the first alignment data DALN1. Therefore, the first data alignment unit 20 may be used to provide a path for the user to input the test code in the test mode.

4 is a detailed configuration diagram of the first pre-fetch unit illustrated in FIG. 3.

Here, the data strobe clock DQS is implemented by a rising data strobe clock RDQS and a falling data strobe clock FDQS, and the rising data strobe clock RDQS and the falling data strobe clock FDQS are each other. Has the opposite phase. In addition, the first alignment data DALN1 is represented as the first-first alignment data DALN1-1 to the first-8th alignment data DALN1-8. Data transmitted from the first data delay unit 220 is represented as delay data (D).

As shown, the first pre-fetch unit 230 includes: a first flip-flop FF1 for latching the delay data D in response to the rising data strobe clock RDQS; A second flip-flop (FF2) for latching an output signal of the first flip-flop (FF1) in response to the polling data strobe clock (FDQS); A third flip-flop (FF3) for latching the delay data (D) in response to the polling data strobe clock (FDQS); A fourth flip-flop FF4 for latching an output signal of the second flip-flop FF2 in response to the rising data strobe clock RDQS; A fifth flip-flop FF5 for latching an output signal of the third flip-flop FF3 in response to the rising data strobe clock RDQS; A sixth flip-flop (FF6) for latching an output signal of the fourth flip-flop (FF4) in response to the polling data strobe clock (FDQS); And a seventh flip-flop FF7 latching an output signal of the fifth flip-flop FF5 in response to the polling data strobe clock FDQS.

The first pre-fetch unit 230 may further include a first delayer DLY1 for delaying an output signal of the second flip-flop FF2 and outputting first-first alignment data DALN1-1; A second delayer (DLY2) for delaying the output signal of the sixth flip-flop (FF6) to output the first to third alignment data (DALN1-3); A third delayer (DLY3) for delaying the output signal of the seventh flip-flop (FF7) to output the 1-5th alignment data DALN1-5; A fourth delayer (DLY4) for delaying the output signal of the third flip-flop (FF3) to output the 1-7th alignment data DALN1-7; An eighth flip-flop FF8 for latching the first-first alignment data DALN1-1 and outputting the first-second alignment data DALN1-2 in response to the internal clock CLK_INT; A ninth flip-flop FF9 for latching the first to third alignment data DALN1-3 to output the first to fourth alignment data DALN1-4 in response to the internal clock CLK_INT; A tenth flip-flop (FF10) for latching the first to fifth alignment data DALN1-5 and outputting the first to sixth alignment data DALN1-6 in response to the internal clock CLK_INT; And an eleventh flip-flop FF11 that latches the first-7th alignment data DALN1-7 and outputs the first-8th alignment data DALN1-8 in response to the internal clock CLK_INT. .

With this configuration, the first pre-fetch unit 230 aligns the 8-bit delay data D inputted in series in parallel to form the 1-1 first alignment data DALN1-1 to 1st. -8 can be output as sorting data (DALN1-8).

FIG. 5 is a detailed configuration diagram of the second data alignment unit shown in FIG. 1.

As illustrated, the second data alignment unit 60 generates a buffer control signal BFCTRL by combining the buffer enable signal BEN and the test enable signal TEN. ; A second data input buffer 620 for buffering the second input data DIN2 in response to the buffer control signal BFCTRL; A second data delay unit 630 for delaying data output from the second data input buffer 620; A fetch controller 640 for generating a fetch control clock CLK_FTC by combining the test enable signal TEN and the internal clock CLK_INT; And secondly generating the second alignment data DALN2 by arranging the data transmitted from the second data delay unit 630 in parallel in response to the data strobe clock DQS and the fetch control clock CLK_FTC. It includes; pre-fetch unit 650.

The buffer controller 610 includes a fifth inverter IV5, a sixth inverter IV6, and a second NAND gate ND2 in the illustrated form, and the test enable signal TEN is in a disabled state. When the buffer enable signal BEN is enabled, the buffer control signal BFCTRL is enabled. However, when the test enable signal TEN is enabled, the buffer controller 610 disables the buffer control signal BFCTRL. Accordingly, the second data input buffer 620 may operate only in a section in which the test enable signal TEN is disabled, and in a section in which the test enable signal TEN is enabled, that is, in a test mode. In this case, the operation is stopped to suppress unnecessary power consumption.

The fetch control unit 640 includes a seventh inverter IV7, an eighth inverter IV8, and a third NAND gate ND3 in the illustrated form, and the test enable signal TEN is in a disabled state. The internal clock CLK_INT is non-inverted to generate the fetch control clock CLK_FTC. However, the fetch control unit 640 disables the fetch control clock CLK_FTC when the test enable signal TEN is enabled. Accordingly, the second pre-fetch unit 650 may operate only in a section where the test enable signal TEN is disabled, and a section in which the test enable signal TEN is enabled, that is, a test mode. In operation, the operation is stopped to suppress unnecessary power consumption.

It can be easily understood that the second pre-fetch unit 650 is configured in the same form as the first pre-fetch unit 230 illustrated in FIG. 4. However, the second prefetch unit 650 differs from the first pre-fetch unit 230 only in that it operates under the control of the fetch control clock CLK_FTC instead of the internal clock CLK_INT.

As such, the second data alignment unit 60 is configured to be inactivated in the test mode so that power consumption does not occur from the inside. Although only a configuration of suppressing power consumption in the data input path is shown here, the technical idea of the present invention is also applied to a buffer of the data strobe clock (DQS), which is not shown, to suppress power consumption in a test mode. It will be appreciated that it is understood to fall within the scope of the present invention.

As described above, the semiconductor memory device and the test method thereof according to the present invention enable the test enable signal in response to the test mode setting signal, and then perform a data alignment circuit in response to the enabled test enable signal. Except to perform the operation of deactivating other data alignment circuits. The signal output from the activated data alignment circuit is decoded, and a test operation is performed in response to the decoded signal. Thereafter, when the read command is input, the test enable signal is disabled.

By such an operation, the semiconductor memory device and the test method of the present invention can apply a test mode without having a separate transmission line of a test code by transmitting a test code using a data input path, thereby providing an area. Gain the advantage of increasing margins. In addition, the power loss may not be increased by deactivating all other paths except for the data input path for transmitting the test code in the test mode. As a result, the present invention provides a technical foundation that can greatly contribute to high integration and low power implementation of semiconductor memory devices.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a detailed configuration diagram of the test mode control unit shown in FIG. 1;

3 is a detailed configuration diagram of the first data alignment unit illustrated in FIG. 1;

4 is a detailed configuration diagram of the first pre-fetch unit illustrated in FIG. 3;

FIG. 5 is a detailed configuration diagram of the second data alignment unit shown in FIG. 1.

Description of the Related Art [0002]

10: test mode control unit 20: first data alignment unit

40: decoding unit 50: test execution unit

60: second data alignment unit

Claims (11)

A test mode control unit configured to enable the test enable signal when the test mode setting signal is enabled, and disable the test enable signal when the read command is enabled; A first data alignment unit for generating first alignment data by sorting serially input first input data into parallel data and transmitting the first alignment data to the first data driver; A decoder configured to decode the first alignment data to generate a decoded signal only when the test enable signal is enabled; A test execution unit executing a preset test mode in response to the decoded signal; And When the test enable signal is enabled, the test enable signal is deactivated. When the test enable signal is disabled, the second input data which is serially input is aligned to generate second data, and the second data is transferred to the second data driver. A second data alignment unit; And the first and second data drivers are configured to drive and transfer the first and second alignment data to a global data bus, respectively. delete The method of claim 1, The first data alignment unit, A data input buffer for buffering the first input data in response to a buffer enable signal; A data delay unit for delaying data output from the data input buffer; And A pre-fetch unit aligning data transmitted from the data delay unit in parallel in response to a data strobe clock and an internal clock to generate the first alignment data; A semiconductor memory device comprising a. delete delete The method of claim 1, The second data sorter, A buffer controller which generates a buffer control signal by combining a buffer enable signal and the test enable signal; A data input buffer for buffering the second input data in response to the buffer control signal; A data delay unit for delaying data output from the data input buffer; A fetch controller configured to generate a fetch control clock by combining the test enable signal and an internal clock; And A pre-fetch unit aligning data transmitted from the data delay unit in parallel in response to a data strobe clock and the fetch control clock to generate the second alignment data; A semiconductor memory device comprising a. delete delete delete delete delete

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