KR101132301B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device capable of controlling a step of an insulating film to stabilize a subsequent process. A method of manufacturing a semiconductor device according to the present invention includes etching a semiconductor substrate to form a pillar-type active pattern; Forming a first conductive pattern on a sidewall of a lower end of the pillar-type active pattern; Forming a second conductive pattern extending in a first direction in a surface of the semiconductor substrate between the pillar-type active patterns; Filling a first insulating layer in the space between the pillar-type active patterns; Firstly recessing the first insulating layer to expose the first conductive pattern in a second direction perpendicular to the first direction; Forming a third conductive pattern contacting the exposed first conductive pattern and extending in the second direction on the first recessed first insulating layer; Second recessing the first insulating layer to expose the pillar-type active pattern in the first direction; And forming a second insulating layer on the second recessed first insulating layer and the third conductive pattern.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of stabilizing a subsequent step by controlling a step of an insulating film.

As the degree of integration of semiconductor devices increases, the area occupied by each unit cell decreases in plan. In response to such a reduction in the unit cell area, various methods for forming buried contacts for storage node contacts of transistors, bit lines, word lines, and capacitors over a limited area have been studied. As one of the methods, a semiconductor device having a transistor (hereinafter referred to as a vertical transistor) having a vertical channel in a semiconductor substrate by arranging a junction region up and down in an active region has been proposed.

The vertical transistor forms a gate to surround sidewalls of a pillar-type active pattern formed on a surface of a semiconductor substrate, and forms junction regions at upper and lower portions of the pillar-type active pattern around the gate, respectively. A vertical transistor having a vertical channel with respect to the main surface of the semiconductor substrate is formed. Therefore, reducing the area of the transistor does not depend on the channel length.

Hereinafter, a manufacturing method of a semiconductor device having a vertical transistor according to the prior art will be briefly described.

A pad oxide film and a pad nitride film are sequentially formed on the semiconductor substrate, and a portion of the semiconductor substrate is etched using the pad nitride film and the pad oxide film as an etching mask to form a pillar-shaped active pattern. A gate is formed on sidewalls of the lower end of the pillar-type active pattern. A junction region is formed in the portion of the semiconductor substrate adjacent to the gate, and then a buried bit line is formed in the portion of the semiconductor substrate below the junction region.

After forming the trench by etching the buried bit line and a portion of the semiconductor substrate below, a first insulating layer is formed to fill the trench. The first insulating layer is formed of a BPSG (Borophosphours Silicate Glass) film. After etching a part of the thickness of the first insulating layer to expose the lower end of the gate, a polysilicon layer is formed. The polysilicon layer is etched to form a word line extending in the direction perpendicular to the buried bit line. A second insulating film is formed on the word line. The second insulating layer is formed of a spin-on dielectric (SOD) layer. After etching the second insulating layer to expose the pad nitride layer, the pad nitride layer is removed.

However, in the above-described conventional technique, when the pad nitride layer is removed, a part of the thickness of the second insulating layer is etched together. In this case, the second insulating layer has a different thickness in the bit line direction and the word line direction. The second insulating film is etched in the line direction to expose the first insulating film portion, and the first insulating film is not exposed in the word line direction.

As a result, the first insulating film is etched to the bottom of the pad oxide film because the first insulating film having a higher etching speed than the second insulating film is exposed in the bit line direction, whereas only the second insulating film is etched in the word line direction so that the bit is etched. Steps are generated in the insulating film remaining in the line direction and the word line direction.

1 is a photograph of a semiconductor device showing a state in which a step is generated in an insulating film.

As shown, in the bit line direction (A? A 'line), the insulating film remains on the sidewall of the active pattern with a thickness lower than the surface of the semiconductor substrate (the thickness has a negative value), so that it appears dark. In the word line direction (B? B 'line), the thickness remains higher than the surface of the semiconductor substrate (the thickness has a positive (+) value), so that the color appears relatively brighter than the bit line direction (A? A'). .

As such, when an insulating film having a different thickness remains in the bit line direction and the word line direction in the vicinity of the active pattern, a step difference between the insulating films may occur, thereby stably performing a subsequent process performed on the resultant of the semiconductor substrate including the insulating film. Can't.

The present invention provides a method for manufacturing a semiconductor device capable of controlling the step difference of the insulating film.

The present invention also provides a method of manufacturing a semiconductor device capable of stabilizing subsequent processes.

A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a pillar-type active pattern by etching a semiconductor substrate; Forming a first conductive pattern on a sidewall of a lower end of the pillar-type active pattern; Forming a second conductive pattern extending in a first direction in a surface of the semiconductor substrate between the pillar-type active patterns; Filling a first insulating layer in the space between the pillar-type active patterns; Firstly recessing the first insulating layer to expose the first conductive pattern in a second direction perpendicular to the first direction; Forming a third conductive pattern contacting the exposed first conductive pattern and extending in the second direction on the first recessed first insulating layer; Second recessing the first insulating layer to expose the pillar-type active pattern in the first direction; And forming a second insulating layer on the second recessed first insulating layer and the third conductive pattern.

The first conductive pattern includes a gate.

The second conductive pattern includes a bit line.

And forming a trench by etching the second conductive pattern and a portion of the semiconductor substrate below after forming the second conductive pattern and before filling the first insulating layer.

The first insulating layer includes a BPSG (Borophosphours Silicate Glass) film.

The third conductive pattern includes a word line.

The word line includes a polysilicon film.

The secondary recess is performed such that the pillar-type active pattern is exposed to 100 to 200 microseconds.

The secondary recess is performed such that the first insulating layer is 500 to 1000 Å removed.

The secondary recess is performed by a cleaning method using a mixed solution of HF and DIW (Deionized Water).

The mixed solution of HF and DIW includes a solution in which HF: DIW is mixed at a ratio of 1: 500 to 1: 5.

The cleaning method is performed using a wet bath or a single wafer cleaner.

The secondary recess is carried out at a temperature of 1 ~ 30 ℃.

The secondary recess is performed for 10 to 100 seconds.

The second insulating layer includes a spin-on dielectric (SOD) layer.

The present invention forms a word line and then recesses a part of the thickness of the first insulating film in the bit line direction, and then forms a second insulating film on the word line and the recessed first insulating film, thereby forming the bit line direction and the word. A second insulating film having a similar thickness in the line direction can be formed.

Accordingly, the present invention can prevent the portion of the first insulating layer under the second insulating layer from being exposed in the bit line direction, thereby controlling the step of the second insulating layer to stabilize the subsequent process.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A and 2B to 9A and 9B are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 2A to 9A respectively correspond to the line AA ′ of FIG. 1. 2B to 9B are cross-sectional views corresponding to the line BB ′ of FIG. 1, respectively.

2A and 2B, a pad oxide film 102 and a pad nitride film 104 are sequentially formed on the semiconductor substrate 100, and then the pad nitride film 104 and the pad oxide film 102 are patterned to form the semiconductor. A mask pattern MK exposing a portion of the substrate 100 is formed. The upper pillar P1 is formed by etching the portion of the semiconductor substrate 100 exposed by the mask pattern MK. The upper pillar P1 is formed by, for example, an anisotropic etching process.

After forming a spacer (not shown) on sidewalls of the mask pattern MK and the upper pillar P1, a portion of the semiconductor substrate 100 exposing the spacer and the mask pattern MK as an etch mask is etched to form a lower pillar. (P2) is formed. The lower pillars P2 are formed by, for example, an isotropic etching process. As a result, the pillar-shaped active pattern P including the upper pillar P1 and the lower pillar P2 is formed on the surface of the semiconductor substrate 100.

Referring to FIGS. 3A and 3B, after the gate insulating layer 106 is formed on the surface of the semiconductor substrate 100 including the pillar-type active pattern P, the pillar-type layer is formed on the gate insulating layer 106. The gate conductive film 108 is formed to fill the space between the active patterns P. Thereafter, the gate conductive layer 108 is etched to form the gate 110 on the sidewall of the lower pillar P2. The gate 110 is preferably formed in an annular shape surrounding the sidewall of the lower pillar P2.

4A and 4B, a buried bit line 112 is formed in the surface of the semiconductor substrate 100 between the pillar-shaped active pattern P including the gate 110. The buried bit line 112 is formed by, for example, an ion implantation process, and is preferably formed to extend in a first direction (A? A ′ in FIG. 1) within the surface of the semiconductor substrate 100.

Referring to FIGS. 5A and 5B, the buried bit line 112 and a portion of the semiconductor substrate 100 below are etched to form a bit line isolation trench T. Referring to FIGS. Before forming the bit line isolation trench T, a liner insulating film (not shown) and an insulating film (not shown) may be formed on the semiconductor substrate 100 on which the buried bit line 112 is formed.

6A and 6B, a first insulating layer 114 is formed to fill a space between the bit line isolation trench T and the pillar-type active pattern P. Referring to FIGS. The first insulating layer 114 is formed of, for example, a BPSG (Borophosphours Silicate Glass) film. Then, the first insulating layer 114 is etched to expose the pad nitride layer 104.

Referring to FIGS. 7A and 7B, the first insulating layer 114 is first recessed in a second direction perpendicular to the first direction that is the buried bit line direction (the line B′B ′ of FIG. 1). The primary recess is performed so that the gate 110 is exposed, preferably, to the lower end of the gate 110.

8A and 8B, a conductive film, for example, a polysilicon film is formed on the first recessed first insulating film 114. Then, the polysilicon layer is etched to form a word line 116 in contact with the exposed gate 110. The word line 116 is preferably formed to extend in the second direction.

9A and 9B, the first insulating layer 114 is secondly recessed in the first direction. The secondary recess may be performed so that the pillar-type active pattern P is exposed, and preferably, the portion of the pillar-type active pattern P is exposed to 100 to 200 ns. For example, the first insulating layer 500 to 1000 ns may be exposed. 114) is removed.

Here, the secondary recess is performed by a cleaning method using a mixed solution of 49% HF and DIW (Deionized Water). The cleaning method is preferably performed using a solution in which the HF: DIW is mixed at a ratio of 1: 500 to 1: 5, and is, for example, a wet bath or a single wafer cleaner. Perform using In addition, the secondary recess is performed for 10 to 100 seconds under a temperature condition of 1 to 30 ℃.

10A and 10B, a second insulating layer 118 is formed on the second recessed first insulating layer 114 and the word line 116. The second insulating film 118 is formed of, for example, a spin-on dielectric (SOD) film. Subsequently, the second insulating layer 118 is etched to expose the pad nitride layer 104.

11A and 11B, the exposed pad nitride film 104 is removed. Removal of the pad nitride film 104 is performed using, for example, a phosphoric acid solution. In this case, a portion of the thickness of the portion of the second insulating layer 118 exposed when the pad nitride layer 104 is removed is etched together.

Here, since the second insulating film is formed after the partial thickness of the first insulating film is removed in the first direction through the secondary recess, a second insulating film having a similar thickness in the first direction and the second direction is formed. to be. Accordingly, the present invention can prevent the first insulating film under the second insulating film from being exposed in the first direction even when a part of the thickness of the second insulating film is etched together when the pad nitride film is removed.

Therefore, the present invention can control the step of the second insulating film after the removal of the pad nitride film to leave a second insulating film of uniform thickness in both the first direction and the second direction, thereby stabilizing subsequent processes. You can.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a photograph of a semiconductor device showing a state in which a step is generated in the insulating film.

2A and 2B to 9A and 9B are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 pad oxide film

104: pad nitride film MK: mask pattern

P1: upper pillar P2: lower pillar

P: pillar type active pattern 106: gate insulating film

108: gate conductive film 110: gate

112: buried bit line T: trench for bit line separation

114: first insulating film 116: word line

118: second insulating film

Claims (15)

Etching the semiconductor substrate to form a pillar-type active pattern; Forming a first conductive pattern on a sidewall of a lower end of the pillar-type active pattern; Forming a second conductive pattern extending in a first direction in a surface of the semiconductor substrate between the pillar-type active patterns; Filling a first insulating layer in the space between the pillar-type active patterns; Firstly recessing the first insulating layer to expose the first conductive pattern in a second direction perpendicular to the first direction; Forming a third conductive pattern contacting the exposed first conductive pattern and extending in the second direction on the first recessed first insulating layer; Second recessing the first insulating layer to expose the pillar-type active pattern in the first direction; And Forming a second insulating film on the second recessed first insulating film and the third conductive pattern; Method of manufacturing a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the first conductive pattern includes a gate. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The second conductive pattern includes a bit line. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, After the forming of the second conductive pattern and before the embedding of the first insulating layer, Etching the second conductive pattern and a portion of the semiconductor substrate below to form a trench; Method of manufacturing a semiconductor device further comprising. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The first insulating film is a manufacturing method of a semiconductor device comprising a BPSG (Borophosphours Silicate Glass) film. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And the third conductive pattern comprises a word line. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, And the word line comprises a polysilicon film. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, The second recess is a method of manufacturing a semiconductor device, characterized in that for performing the pillar-type active pattern exposed to 100 ~ 200Å. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The second recess is a method of manufacturing a semiconductor device, characterized in that to remove the first insulating film 500 ~ 1000 ～. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The secondary recess is a method of manufacturing a semiconductor device, characterized in that performed by a cleaning method using a mixed solution of HF and DIW (Deionized Water). Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, The method of manufacturing a semiconductor device, characterized in that the mixed solution of HF and DIW comprises a mixture of HF: DIW in a ratio of 1: 500 to 1: 5. Claim 12 was abandoned upon payment of a registration fee. 11. The method of claim 10, The cleaning method is a method of manufacturing a semiconductor device, characterized in that performed using a wet bath (Wet Bath), or a single wafer cleaner (Single Wafer Cleaner). Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, The secondary recess is a method of manufacturing a semiconductor device, characterized in that performed at a temperature condition of 1 ~ 30 ℃. Claim 14 was abandoned when the registration fee was paid. The method of claim 1, The secondary recess is a method of manufacturing a semiconductor device, characterized in that performed for 10 to 100 seconds. Claim 15 was abandoned upon payment of a registration fee. The method of claim 1, And the second insulating layer comprises a spin-on dielectric (SOD) layer.

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