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KR101107660B1 - Stack package - Google Patents

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KR101107660B1
KR101107660B1 KR1020110076463A KR20110076463A KR101107660B1 KR 101107660 B1 KR101107660 B1 KR 101107660B1 KR 1020110076463 A KR1020110076463 A KR 1020110076463A KR 20110076463 A KR20110076463 A KR 20110076463A KR 101107660 B1 KR101107660 B1 KR 101107660B1
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package
substrate
disposed
semiconductor chip
stack package
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KR20110115108A (en
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강태민
황유경
손재현
이대웅
이병도
김유환
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주식회사 하이닉스반도체
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
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    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 구성요소들간의 열팽창계수 차이로 인한 크랙 발생을 감소시킨 스택 패키지를 개시한다. 개시된 본 발명의 스택 패키지는, 상면에 제1본드핑거들 및 제1접속패드들이 배치되고 하면에 제1볼랜드들이 배치된 제1기판과, 상기 제1기판의 상면 상에 배치되고 상기 제1본드핑거들과 전기적으로 연결된 제1본딩패드들을 구비한 제1반도체칩과, 상기 제1반도체칩을 밀봉하도록 상기 제1기판의 상면 상에 형성되고 상기 제1접속패드들을 노출시키는 홀들을 구비한 제1봉지부재,를 갖는 제1패키지; 상기 제1패키지 상에 스택되며, 상면에 제2본드핑거들이 배치되고 하면에 제2볼랜드들이 배치된 제2기판과, 상기 제2기판의 상면 상에 배치되고 상기 제2본드핑거들과 전기적으로 연결된 제2본딩패드들을 구비한 제2반도체칩과, 상기 제2반도체칩을 밀봉하도록 상기 제2기판의 상면 상에 형성된 제2봉지부재,를 갖는 제2패키지; 및 상기 제1봉지부재의 홀들 내에 상기 제1패키지와 제2패키지를 전기적으로 연결하도록 설치된 플렉서블 전도체;를 포함한다. The present invention discloses a stack package that reduces the occurrence of cracks due to thermal expansion coefficient differences between components. The disclosed stack package includes a first substrate having first bond fingers and first connection pads disposed on an upper surface thereof and first borlands disposed on a lower surface thereof, and disposed on an upper surface of the first substrate and bonded to the first bond. A first semiconductor chip having first bonding pads electrically connected to fingers, and a hole formed on an upper surface of the first substrate to seal the first semiconductor chip and having holes exposing the first connection pads. A first package having a sealing member; A second substrate stacked on the first package and having second bond fingers disposed on an upper surface thereof and second borlands disposed on a lower surface thereof; and disposed on an upper surface of the second substrate and electrically connected to the second bond fingers A second package having a second semiconductor chip having second bonding pads connected thereto, and a second encapsulation member formed on an upper surface of the second substrate to seal the second semiconductor chip; And a flexible conductor installed to electrically connect the first package and the second package in the holes of the first encapsulation member.

Description

스택 패키지{Stack package}Stack package

본 발명은 스택 패키지에 관한 것으로, 보다 상세하게는, 구성요소들간의 열팽창계수 차이로 인한 크랙 발생을 감소시킨 스택 패키지에 관한 것이다. The present invention relates to a stack package, and more particularly, to a stack package that reduces the occurrence of cracks due to the difference in thermal expansion coefficient between the components.

최근 들어, 방대한 데이터를 저장함은 물론 방대한 데이터를 단시간 내에 처리하는 것이 가능한 메모리 반도체칩을 갖는 반도체 패키지가 개발된 바 있다. Recently, semiconductor packages having memory semiconductor chips capable of storing massive data and processing massive data in a short time have been developed.

또한, 다수개의 메모리 반도체칩들을 칩 레벨로, 또는, 패키지 레벨로 적층하여 데이터 저장 용량을 보다 증가시킨 스택 패키지가 개발되고 있다. 패키지 온 패키지(Package on Package)는 메모리 반도체칩들을 패키지 레벨로 적층하여 구성한 스택 패키지의 대표적 예이다. In addition, a stack package that increases data storage capacity by stacking a plurality of memory semiconductor chips at a chip level or a package level has been developed. A package on package is a representative example of a stack package formed by stacking memory semiconductor chips at a package level.

아울러, 최근에는 메모리 반도체칩들과 시스템 반도체칩을 적층하여 데이터 저장 용량은 물론 데이터 처리 속도를 보다 향상시킨 시스템 인 패키지(System In Package)가 개발되고 있다. 이러한 시스템 인 패키지는 메모리 반도체칩들과 시스템 반도체칩을 칩 레벨로 적층하여 구성하는 것이 일반적이며, 경우에 따라서는 상기 메모리 반도체칩들과 시스템 반도체칩을 패키지 레벨로 적층하여 구성하기도 한다. In addition, recently, a system in package has been developed in which memory semiconductor chips and system semiconductor chips are stacked to improve data storage capacity and data processing speed. Such a system-in-package is generally formed by stacking memory semiconductor chips and a system semiconductor chip at a chip level, and in some cases, the memory semiconductor chips and a system semiconductor chip are stacked at a package level.

그런데, 반도체 패키지들을 상,하로 적층하여 구성하는 종래의 스택 패키지는 구성요소들간의 열팽창계수 차이로 인해 크랙(crack)이 발생됨으로써 신뢰성 문제를 일으키고 있다. However, in the conventional stack package that is formed by stacking semiconductor packages up and down, cracks are generated due to thermal expansion coefficient differences between components, thereby causing reliability problems.

구체적으로, 종래의 스택 패키지는 제1패키지 내에 프리-솔더(pre-solder) 또는 구리 포스트(copper post)를 형성하여 제1패키지와 제2패키지간의 전기적 연결을 달성하고 있다. Specifically, the conventional stack package forms a pre-solder or copper post in the first package to achieve electrical connection between the first package and the second package.

그런데, 이와 같은 종래의 스택 패키지 구조에서는 반도체칩을 밀봉하고 있는 봉지부재인 EMC(Epoxy Molding Compound)와 제1패키지와 제2패키지간의 전기적 연결을 위해 상기 제1패키지 내에 형성한 프리-솔더 또는 구리-포스트간 열팽창계수(Coefficient of Thermal Expansion; CTE)의 미스매치(mismatch)로 인해 상기 제1패키지의 휨(warpage)이 일어남은 물론 크랙이 발생하게 되고, 이 결과, 신뢰성이 저하된다. However, in the conventional stack package structure, the pre-solder or copper formed in the first package for the electrical connection between the epoxy molding compound (EMC), which is an encapsulation member sealing the semiconductor chip, and the first package and the second package. The mismatch of the coefficient of thermal expansion (CTE) between posts causes warpage of the first package as well as cracks, resulting in lower reliability.

본 발명은 구성요소들간 CTE 미스매치로 인한 휨의 발생을 감소시킨 스택 패키지를 제공한다. The present invention provides a stack package that reduces the occurrence of warpage due to CTE mismatch between components.

또한, 본 발명은 구성요소들간 CTE 미스매치로 인한 크랙 발생을 억제시킨 스택 패키지를 제공한다. The present invention also provides a stack package that suppresses the occurrence of cracks due to CTE mismatch between components.

게다가, 본 발명은 구성요소들간의 CTE 미스매치로 인한 휨 및 크랙 발생을 감소시킴으로써 신뢰성을 향상시킨 스택 패키지를 제공한다.In addition, the present invention provides a stack package with improved reliability by reducing warpage and cracking caused by CTE mismatch between components.

본 발명에 따른 스택 패키지는, 상면에 제1본드핑거들 및 제1접속패드들이 배치되고 하면에 제1볼랜드들이 배치된 제1기판과, 상기 제1기판의 상면 상에 배치되고 상기 제1본드핑거들과 전기적으로 연결된 제1본딩패드들을 구비한 제1반도체칩과, 상기 제1반도체칩을 밀봉하도록 상기 제1기판의 상면 상에 형성되고 상기 제1접속패드들을 노출시키는 홀들을 구비한 제1봉지부재,를 갖는 제1패키지; 상기 제1패키지 상에 스택되며, 상면에 제2본드핑거들이 배치되고 하면에 제2볼랜드들이 배치된 제2기판과, 상기 제2기판의 상면 상에 배치되고 상기 제2본드핑거들과 전기적으로 연결된 제2본딩패드들을 구비한 제2반도체칩과, 상기 제2반도체칩을 밀봉하도록 상기 제2기판의 상면 상에 형성된 제2봉지부재,를 갖는 제2패키지; 및 상기 제1봉지부재의 홀들 내에 상기 제1패키지와 제2패키지를 전기적으로 연결하도록 설치된 플렉서블 전도체;를 포함한다. According to the present invention, a stack package includes a first substrate having first bond fingers and first connection pads disposed on an upper surface thereof and first borlands disposed on a lower surface thereof, and a first substrate disposed on an upper surface of the first substrate and bonded to the first bond. A first semiconductor chip having first bonding pads electrically connected to fingers, and a hole formed on an upper surface of the first substrate to seal the first semiconductor chip and having holes exposing the first connection pads. A first package having a sealing member; A second substrate stacked on the first package and having second bond fingers disposed on an upper surface thereof and second borlands disposed on a lower surface thereof; and disposed on an upper surface of the second substrate and electrically connected to the second bond fingers A second package having a second semiconductor chip having second bonding pads connected thereto, and a second encapsulation member formed on an upper surface of the second substrate to seal the second semiconductor chip; And a flexible conductor installed to electrically connect the first package and the second package in the holes of the first encapsulation member.

본 발명에 따른 스택 패키지는 상기 제1볼랜드에 부착된 제1접속단자를 더 포함한다. The stack package according to the present invention further includes a first connection terminal attached to the first borland.

상기 플렉서블 전도체는, 그의 일부분이 상기 제1봉지부재로부터 노출되고, 상기 노출된 부분이 상기 제2볼랜드에 직접 연결된다. The flexible conductor is partially exposed from the first encapsulation member, and the exposed portion is directly connected to the second borland.

본 발명에 따른 스택 패키지는 상기 제2볼랜드에 부착되고 상기 제1봉지부재 내에 설치된 상기 플렉서블 전도체와 연결된 제2접속단자를 더 포함한다. The stack package according to the present invention further includes a second connection terminal attached to the second borland and connected to the flexible conductor installed in the first encapsulation member.

상기 플렉서블 전도체는, 그의 일부분이 상기 제1봉지부재로부터 노출되고, 상기 노출된 부분이 상기 제2접속단자에 연결된다. A portion of the flexible conductor is exposed from the first encapsulation member, and the exposed portion is connected to the second connection terminal.

상기 제2접속단자는 솔더볼 또는 다른 플렉서블 전도체를 포함한다. The second connection terminal includes a solder ball or other flexible conductor.

상기 플렉서블 전도체는 일면 상에 구리패턴이 형성된 플렉서블 서킷 보드가 상기 구리패턴이 외측면에 배치되게 원통형으로 말려진 형상을 갖거나, 또는, 일면 상에 구리패턴이 형성된 플렉서블 서킷 보드가 단면이 지그재그로 구부려진 형상을 갖는다. The flexible conductor may have a shape in which a flexible circuit board on which a copper pattern is formed is rolled into a cylindrical shape so that the copper pattern is disposed on an outer surface thereof, or a flexible circuit board having a copper pattern on one surface is zigzag in cross section. It has a curved shape.

상기 홀들은 상기 제1봉지부재 내에 상기 제1접속패드들을 각각 노출시키면서 상기 플렉서블 전도체가 각각 삽입되도록 형성된다. The holes are formed such that the flexible conductors are respectively inserted while exposing the first connection pads in the first encapsulation member.

본 발명에 따른 스택 패키지는 상기 플렉서블 전도체들이 삽입된 상기 홀들 내에 형성된 언더필을 더 포함한다. The stack package according to the present invention further includes an underfill formed in the holes into which the flexible conductors are inserted.

상기 홀들은 인접하는 한 쌍의 제1접속패드를 동시에 노출시키도록 형성된다. The holes are formed to simultaneously expose a pair of adjacent first connection pads.

상기 플렉서블 전도체는, 일면 및 이에 대향하는 타면을 갖는 플렉서블 서킷 보드와 상기 플렉서블 서킷 보드의 일면 상에 형성된 구리패턴을 포함하고, 상기 구리패턴이 상기 홀의 일측벽 및 이에 대향하는 타측벽 상에 상호 이격하여 ㄷ자 모양 및 미러 ㄷ자 모양으로 배치된 형상을 갖는다. The flexible conductor includes a flexible circuit board having one surface and the other surface opposite thereto and a copper pattern formed on one surface of the flexible circuit board, wherein the copper patterns are spaced apart from each other on one side wall of the hole and the other side wall opposite thereto. It has a shape arranged in a U-shape and a mirror U-shape.

본 발명에 따른 스택 패키지는 상기 플렉서블 전도체가 삽입된 상기 홀들 내에 형성된 언더필을 더 포함한다. The stack package according to the present invention further includes an underfill formed in the holes into which the flexible conductor is inserted.

상기 제1본딩패드를 구비한 제1반도체칩 및 상기 제2본딩패드를 구비한 제2반도체칩은 각각 상기 제1본드핑거가 배치된 제1기판의 상면 및 상기 제2본드핑거가 배치된 제2기판의 상면 상에 페이스 업 타입으로 배치된다. Each of the first semiconductor chip having the first bonding pad and the second semiconductor chip having the second bonding pad may include a top surface of the first substrate on which the first bond finger is disposed and a second bond finger on which the second bond chip is disposed. 2 It is disposed in the face up type on the upper surface of the substrate.

본 발명에 따른 스택 패키지는 상기 상기 제1반도체칩의 제1본딩패드와 상기 제1기판의 제1본드핑거 사이 및 상기 제2반도체칩의 제2본딩패드와 상기 제2기판의 제2본드핑거 사이를 전기적으로 연결하는 연결부재를 더 포함한다. According to the present invention, a stack package is provided between a first bonding pad of the first semiconductor chip and a first bond finger of the first substrate and a second bonding pad of the second semiconductor chip and a second bond finger of the second substrate. It further comprises a connection member for electrically connecting between.

상기 연결부재는 전도성 와이어 또는 패턴 필름을 포함한다. The connection member includes a conductive wire or a pattern film.

상기 제1본딩패드를 구비한 제1반도체칩 및 상기 제2본딩패드를 구비한 제2반도체칩은 각각 상기 제1본드핑거가 배치된 제1기판의 상면 및 상기 제2본드핑거가 배치된 제2기판의 상면 상에 페이스 다운 타입으로 배치된다. Each of the first semiconductor chip having the first bonding pad and the second semiconductor chip having the second bonding pad may include a top surface of the first substrate on which the first bond finger is disposed and a second bond finger on which the second bond chip is disposed. 2 It is disposed in the face down type on the upper surface of the substrate.

상기 제1반도체칩의 제1본딩패드와 제1기판의 제1본드핑거 사이 및 상기 제2반도체칩의 제2본딩패드와 제2기판의 제2본드핑거 사이를 전기적으로 연결하는 연결부재를 더 포함한다. A connection member electrically connecting between the first bonding pad of the first semiconductor chip and the first bond finger of the first substrate and between the second bonding pad of the second semiconductor chip and the second bond finger of the second substrate. Include.

상기 연결부재는 범프 또는 솔더를 포함한다. The connecting member includes bumps or solders.

본 발명은 스택 패키지를 구현함에 있어서 제1패키지 내에 플렉서블 서킷 보드에 구리패턴이 형성된 구조의 플렉서블 전도체(Flexible conductor)를 형성하고, 이러한 플렉서블 전도체를 이용해서 제1패키지와 제2패키지간의 전기적 연결을 달성한다. According to the present invention, in the implementation of a stack package, a flexible conductor having a structure in which a copper pattern is formed on a flexible circuit board is formed in a first package, and the electrical connection between the first package and the second package is formed using the flexible conductor. To achieve.

이 경우, 상기 플렉서블 전도체가 제1패키지와 제2패키지간의 전기적 신호 전달을 위한 인터페이스(interface) 역할을 함은 물론 제1패키지에서의 구성요소들간 CTE 미스매치에 기인하여 발생되는 스트레스(stress)의 버퍼(buffer) 역할을 하게 된다. In this case, the flexible conductor serves as an interface for transmitting an electrical signal between the first package and the second package, as well as the stress caused by the CTE mismatch between the components in the first package. It will act as a buffer.

따라서, 본 발명에 따른 스택 패키지는 상기 플렉서블 전도체가 스트레스 버퍼의 역할을 하는 것을 통해, 종래의 그것과 비교할 때, 제1패키지의 휨이 개선됨은 물론 크랙 발생이 억제되며, 그래서, 향상된 신뢰성을 갖게 된다.Therefore, the stack package according to the present invention, through the flexible conductor acts as a stress buffer, compared with the conventional one, the warpage of the first package is improved as well as the occurrence of cracks is suppressed, so that the improved reliability do.

도 1은 본 발명의 제1실시예에 따른 스택 패키지를 도시한 단면도이다.
도 2 및 도 3은 본 발명의 일 실시예에 따른 스택 패키지에서의 플렉서블 전도체를 설명하기 위한 사시도들이다.
도 4는 본 발명의 제2실시예에 따른 스택 패키지를 도시한 단면도이다.
도 5는 본 발명의 제3실시예에 따른 스택 패키지를 도시한 단면도이다.
도 6은 본 발명의 제4실시예에 따른 스택 패키지를 도시한 단면도이다.
도 7은 본 발명의 제5실시예에 따른 스택 패키지를 도시한 단면도이다. 1 is a cross-sectional view showing a stack package according to a first embodiment of the present invention.
2 and 3 are perspective views illustrating a flexible conductor in a stack package according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a stack package according to a second embodiment of the present invention.
5 is a cross-sectional view illustrating a stack package according to a third embodiment of the present invention.
6 is a cross-sectional view illustrating a stack package according to a fourth embodiment of the present invention.
7 is a cross-sectional view illustrating a stack package according to a fifth embodiment of the present invention.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 제1실시예에 따른 스택 패키지를 도시한 단면도이다. 도시된 바와 같이, 본 발명의 제1실시예에 따른 스택 패키지(100)는 제1패키지(100a) 및 상기 제1패키지(100a) 상에 스택된 제2패키지(100b)를 포함한다. 1 is a cross-sectional view showing a stack package according to a first embodiment of the present invention. As shown, the stack package 100 according to the first embodiment of the present invention includes a first package 100a and a second package 100b stacked on the first package 100a.

상기 제1패키지(100a)는 제1기판(110a)과 상기 제1기판(110a) 상에 배치된 제1반도체칩(120a)과 상기 제1반도체칩(120a)을 밀봉하는 제1봉지부재(150a) 및 상기 제1봉지부재(150a) 내에 배치된 플렉서블 전도체(170)를 포함한다. The first package 100a may include a first encapsulation member sealing the first semiconductor chip 120a and the first semiconductor chip 120a disposed on the first substrate 110a and the first substrate 110a. 150a) and a flexible conductor 170 disposed in the first encapsulation member 150a.

상기 제1기판(110a)은 인쇄회로기판(Printed Circuit Board)인 것으로 이해될 수 있으며, 그의 상면에 배치된 제1본드핑거들(112a) 및 제1접속패드들(114a)과 그의 하면에 배치된 제1볼랜드들(116a)을 포함한다. 상기 제1반도체칩(120a)은, 예를 들어, 에지 패드 타입(edge pad type) 칩이며, 상기 제1기판(110a)의 상면에 제1접착부재(130a)를 매개로 하여 페이스-업 타입(face-up type)으로 부착된다. The first substrate 110a may be understood as a printed circuit board, and disposed on the first bond fingers 112a and the first connection pads 114a and the bottom surface thereof. First borlands 116a. The first semiconductor chip 120a is, for example, an edge pad type chip, and is face-up type on the upper surface of the first substrate 110a via the first adhesive member 130a. (face-up type) is attached.

상기 제1패키지(100a)는 상기 제1반도체칩(120a)의 제1본딩패드(122a)와 이에 인접하여 배치된 상기 제1기판(110a)의 제1본드핑거(112a)를 연결하는 제1연결부재(140a)들을 더 포함한다. 상기 제1연결부재(140a)는, 도시된 바와 같이, 전도성 와이어가 이용될 수 있다. 한편, 도시하지 않았으나, 상기 제1연결부재(140a)로서는 회로패턴을 구비한 패턴 필름도 이용될 수도 있다. The first package 100a connects a first bonding pad 122a of the first semiconductor chip 120a to a first bond finger 112a of the first substrate 110a disposed adjacent thereto. It further includes a connection member (140a). As shown in the drawing, the first connection member 140a may use a conductive wire. Although not shown, a pattern film having a circuit pattern may also be used as the first connection member 140a.

상기 제1패키지(100a)는 제1기판(110a) 하면의 제1볼랜드들(116a) 상에 각각 부착된 제1접속부재들(160a)을 더 포함한다. 상기 제1접속부재(160a)는, 도시된 바와 같이, 솔더 볼이 이용될 수 있다. The first package 100a further includes first connection members 160a attached to the first borlands 116a on the bottom surface of the first substrate 110a. As the first connection member 160a, as shown, a solder ball may be used.

상기 제1봉지부재(150a)는 상기 제1반도체칩(120a) 및 제1연결부재(140a)를 포함한 상기 제1기판(110a)의 상면을 덮도록 형성된다. 상기 제1봉지부재(150a)로서는, 예를 들어, EMC(Epoxy Molding Compound)가 이용될 수 있다.The first encapsulation member 150a is formed to cover the top surface of the first substrate 110a including the first semiconductor chip 120a and the first connection member 140a. As the first encapsulation member 150a, for example, an epoxy molding compound (EMC) may be used.

상기 플렉서블 전도체(170)는 제1패키지(100a)의 제1봉지부재(150a) 내에 배치된다. 본 실시예에서, 상기 플렉서블 전도체(170)는, 도 2에 도시된 바와 같이, 절연성의 플렉서블 서킷 보드(172)와 상기 플렉서블 서킷 보드(172)의 일면 상에 형성된 구리패턴(174)을 포함하며, 이와 같이 일면 상에 구리패턴(174)이 형성된 플렉서블 서킷 보드(172)가 상기 구리패턴(174)이 외측면에 배치되게 원기둥 모양으로 말려져 있는 형상을 갖는다. 이때, 상기 플렉서블 서킷 보드(172)의 양측단은, 예를 들어, 접착제에 의해 상호 부착된다. The flexible conductor 170 is disposed in the first encapsulation member 150a of the first package 100a. In the present embodiment, as shown in FIG. 2, the flexible conductor 170 includes an insulating flexible circuit board 172 and a copper pattern 174 formed on one surface of the flexible circuit board 172. As described above, the flexible circuit board 172 having the copper pattern 174 formed on one surface thereof has a shape in which the copper pattern 174 is rolled in a cylindrical shape so that the copper pattern 174 is disposed on the outer surface. At this time, both ends of the flexible circuit board 172 are attached to each other by, for example, an adhesive.

다른 실시예에서, 상기 플렉서블 전도체(170)는, 도 3에 도시된 바와 같이, 일면 상에 구리패턴(174)이 형성된 플렉서블 서킷 보드(172)가 단면이 지그재그로 구부려진 형상을 가질 수 있다. 이때, 상기 지그재그로 구부려진 플렉서블 서킷 보드(172)의 상단면 및 하단면 각각에는 상기 구리패턴(174)이 배치된다.In another embodiment, the flexible conductor 170 may have a shape in which a flexible circuit board 172 having a copper pattern 174 formed on one surface thereof is bent in a zigzag cross section. At this time, the copper pattern 174 is disposed on each of the top and bottom surfaces of the zigzag flexible circuit board 172.

이와 같은 플렉서블 전도체(170)에 있어서, 하측에 배치된 구리패턴(174) 부분은 상기 제1기판(110a)의 제1접속패드(114a)와 연결되며, 상측에 배치된 구리패턴(174) 부분은 상기 제1봉지부재(150a)의 표면으로 노출된다.In the flexible conductor 170, the lower portion of the copper pattern 174 is connected to the first connection pad 114a of the first substrate 110a and the upper portion of the copper pattern 174 is disposed. Is exposed to the surface of the first encapsulation member 150a.

한편, 상기 플렉서블 전도체(170)는 상기 제1봉지부재(150a)의 형성 전에 상기 제1기판(110a)의 제1접속패드(114a) 상에 우선 배치될 수 있으며, 그리고, 상기 제1봉지부재(150a)는, 예를 들어, 상기 플렉서블 전도체(170)의 상측 부분이 노출되는 두께로 형성되거나, 또는, 상기 플렉서블 전도체(170)를 완전히 덮는 두께로 형성된 후, 상기 플렉서블 전도체(170)의 상측 부분이 노출되도록 그라인딩된다.Meanwhile, the flexible conductor 170 may be first disposed on the first connection pad 114a of the first substrate 110a before the first encapsulation member 150a is formed and the first encapsulation member. For example, 150a may be formed to a thickness at which an upper portion of the flexible conductor 170 is exposed, or may be formed to a thickness completely covering the flexible conductor 170, and then an upper side of the flexible conductor 170. The part is ground to be exposed.

도시하지 않았으나, 상기 제1봉지부재(150a)는 제1플렉서블 전도체(170)가 배치된 제1기판(110a) 상에 상기 플렉서블 전도체(170)를 완전히 덮는 두께로 형성된 후, 인접한 다수의 플렉서블 전도체들(170)의 상측 부분들을 동시에 노출시키도록 선택적으로 식각될 수도 있다.Although not shown, the first encapsulation member 150a is formed to have a thickness completely covering the flexible conductor 170 on the first substrate 110a on which the first flexible conductor 170 is disposed, and then a plurality of adjacent flexible conductors. It may optionally be etched to simultaneously expose the upper portions of the fields 170.

계속해서, 상기 제2패키지(100b)는 제2기판(110b)과 상기 제2기판(110b) 상에 배치된 제2반도체칩(120b)과 상기 제2반도체칩(120b)을 밀봉하는 제2봉지부재(150b)를 포함한다. Subsequently, the second package 100b seals the second semiconductor chip 120b and the second semiconductor chip 120b disposed on the second substrate 110b and the second substrate 110b. The sealing member 150b is included.

상기 제2기판(110b)은 인쇄회로기판인 것으로 이해될 수 있으며, 상면에 배치된 제2본드핑거들(112b) 및 하면에 배치된 제1볼랜드들(116b)을 포함한다. 상기 제2반도체칩(120b)은, 예를 들어, 에지 패드 타입 칩이며, 상기 제2기판(110b)의 상면 상에 제2접착부재(130b)를 매개로 하여 페이스-업 타입(face-up type)으로 부착된다. The second substrate 110b may be understood as a printed circuit board and includes second bond fingers 112b disposed on an upper surface and first borlands 116b disposed on a lower surface thereof. The second semiconductor chip 120b is, for example, an edge pad type chip, and is face-up type on the upper surface of the second substrate 110b via the second adhesive member 130b. type).

상기 제2패키지(100b)는 상기 제2반도체칩(120b)의 제2본딩패드(122b)와 이에 인접하여 배치된 상기 제2기판(110b)의 제2본드핑거(112b)를 전기적으로 연결하는 제2연결부재(140b)를 더 포함한다. 상기 제2연결부재(140b)는, 예를 들어, 전도성 와이어가 이용될 수 있고, 도시하지 않았으나, 패턴 필름 등도 이용 가능하다. The second package 100b electrically connects the second bonding pad 122b of the second semiconductor chip 120b and the second bond finger 112b of the second substrate 110b disposed adjacent thereto. It further includes a second connecting member (140b). For example, a conductive wire may be used as the second connection member 140b. Although not shown, a pattern film may be used.

상기 제2패키지(100b)는 상기 제2기판(110b) 하면의 제2볼랜드들(116b) 상에 각각 부착된 제2접속부재들(160b)을 더 포함한다. 상기 제2접속부재(160b)로서는, 예를 들어, 솔더 볼이 이용될 수 있다. 또한, 상기 제2접속부재(160b)로서는 상기 제1봉지부재(150a) 내에 삽입된 플렉서블 전도체(170)와 동일하거나 유사한 구조를 갖는 다른 플렉서블 전도체 또한 이용 가능하다. The second package 100b further includes second connection members 160b attached to the second borlands 116b on the bottom surface of the second substrate 110b. As the second connection member 160b, for example, a solder ball may be used. In addition, other flexible conductors having the same or similar structure as the flexible conductor 170 inserted into the first encapsulation member 150a may also be used as the second connection member 160b.

본 실시예에서, 상기 제2접속부재(160b)는 상기 제1패키지(100a)에서의 제1봉지부재(150a)의 표면으로 노출된 플렉서블 전도체(170) 부분과 전기적으로 연결된다. 보다 명확하게, 상기 제2접속부재(160b)는 상기 제2패키지(100b)와 제1패키지(100a)간의 전기적 연결을 위해 제1봉지부재(150a)의 표면으로 노출된 플렉서블 전도체(170)의 상측 부분에 배치된 구리패턴(174) 부분과 전기적으로 연결된다. In the present embodiment, the second connection member 160b is electrically connected to a portion of the flexible conductor 170 exposed to the surface of the first encapsulation member 150a in the first package 100a. More specifically, the second connection member 160b is formed of the flexible conductor 170 exposed to the surface of the first encapsulation member 150a for electrical connection between the second package 100b and the first package 100a. It is electrically connected to a portion of the copper pattern 174 disposed on the upper portion.

상기 제2봉지부재(150b)는 상기 제2반도체칩(120b) 및 제2연결부재(140b)를 포함한 상기 제2기판(110b)의 상면을 덮도록 형성된다. 상기 제2봉지부재(150b)로서는, 예를 들어, EMC가 이용될 수 있다. The second encapsulation member 150b is formed to cover the top surface of the second substrate 110b including the second semiconductor chip 120b and the second connection member 140b. As the second encapsulation member 150b, for example, EMC may be used.

한편, 전술한 본 발명의 제1실시예에 따른 스택 패키지(100)에 있어서, 상기 제2패키지(100b)는 제2볼랜드(116b)에의 제2접속단자(160b)의 부착없이 구성될 수 있으며, 이 경우, 상기 제1패키지(100a)에서의 제1봉지부재(150a)의 표면으로 노출된 플렉서블 전도체(170) 부분은 상기 제2패키지(100b)의 제2볼랜드(116b)에 직접 연결된다.Meanwhile, in the stack package 100 according to the first embodiment of the present invention, the second package 100b may be configured without attaching the second connection terminal 160b to the second borland 116b. In this case, the portion of the flexible conductor 170 exposed to the surface of the first encapsulation member 150a in the first package 100a is directly connected to the second borland 116b of the second package 100b. .

전술한 바와 같은 본 발명의 스택 패키지는 제1패키지에 플렉서블 전도체를 삽입하여 상기 제1패키지와 제2패키지간의 전기적 연결을 달성한 POP 구조를 갖는데, 제1패키지에 프리-솔더 또는 구리-포스트를 삽입하여 구성한 종래의 그것에 비해 구성요소들간 CTE의 미스매치가 감소되며, 이로 인해, 상기 제1패키지의 휨 발생이 감소됨은 물론 크랙 발생 또한 억제된다. The stack package of the present invention as described above has a POP structure in which a flexible conductor is inserted into a first package to achieve an electrical connection between the first package and the second package, and the pre-solder or copper-post is attached to the first package. The mismatch of CTEs between components is reduced compared to the conventional one formed by inserting, thereby reducing the occurrence of warpage of the first package as well as suppressing the occurrence of cracks.

예를 들어, 본 발명의 스택 패키지는 제1봉지부재 물질인 EMC와 솔더간, 또는, EMC와 구리-포스트간의 CTE 미스매치가 감소되어 종래 대비 50% 이상 휨이 개선되며, 또한, 플렉서블 전도체가 EMC와 솔더간, 또는, EMC와 구리-포스트간의 CTE 미스매치에 기인하는 스트레스를 감소시킴으로써 종래 대비 20∼50% 정도 크랙 발생이 억제된다. For example, the stack package of the present invention can reduce the CTE mismatch between the first encapsulation material, EMC and solder, or EMC and copper-post, thereby improving warpage by 50% or more, and the flexible conductor By reducing stress caused by CTE mismatches between EMC and solder, or between EMC and copper-posts, the generation of cracks is suppressed by 20-50% compared to the conventional method.

따라서, 본 발명의 스택 패키지는 구성요소들간 CTE의 미스매치에 기인하는 제1패키지의 휨 및 크랙 발생이 감소됨으로써 향상된 신뢰성을 갖게 된다. Accordingly, the stack package of the present invention has improved reliability by reducing warpage and crack occurrence of the first package due to mismatch of CTE between components.

도 4는 본 발명의 제2실시예에 따른 스택 패키지를 도시한 단면도이다. 여기서, 도 1과 동일한 부분은 동일한 도면부호로 나타낸다. 4 is a cross-sectional view illustrating a stack package according to a second embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

도시된 바와 같이, 제1패키지(100a)의 제1봉지부재(150a)에 제1기판(110a)의 상면에 배치된 제1접속패드들(114a)을 각각 노출시키는 제1홀들(H1)이 형성되어 있고, 플렉서블 전도체들(170)은 상기 제1홀들(H1) 내에 각각 삽입되어 대응하는 제1접속패드(114a)와 각각 연결되도록 배치되어 있으며, 그리고, 각각 플렉서블 전도체(170)가 삽입된 제1홀들(H1) 내에는 언더필(180)이 형성되어 있다. 상기 제1홀(H1)은, 예를 들어, 상기 제1봉지부재(150a)의 형성 후에 드릴링 공정 또는 식각 공정을 통해 형성된 것으로 이해될 수 있다. As shown, the first holes H1 exposing the first connection pads 114a disposed on the upper surface of the first substrate 110a to the first encapsulation member 150a of the first package 100a. The flexible conductors 170 are formed to be inserted into the first holes H1 and connected to the corresponding first connection pads 114a, respectively, and the flexible conductors 170 are inserted. An underfill 180 is formed in the first holes H1. The first hole H1 may be understood to be formed through, for example, a drilling process or an etching process after the formation of the first encapsulation member 150a.

상기 플렉서블 전도체(170)는, 예를 들어, 원기둥 형상의 단면을 갖도록 마련되어 있으며, 상기 언더필(180)은 이러한 원기둥 형상의 단면을 갖는 플렉서블 전도체(170)의 내측에도 형성되어 있다. 상기 플렉서블 전도체(170)는 단면이 원기둥 형상을 갖는 구조 이외에, 도시하지 않았으나, 지그재그로 절곡된 단면을 갖도록 구부려진 형상을 가질 수도 있다. The flexible conductor 170 is provided to have, for example, a cylindrical cross section, and the underfill 180 is also formed inside the flexible conductor 170 having such a cylindrical cross section. Although not shown, the flexible conductor 170 may have a bent shape to have a cross section bent in a zigzag form, in addition to the structure having a cylindrical cross section.

그 밖에, 본 발명의 제2실시예에 따른 스택 패키지(200)에서의 나머지 구성요소들은 전술한 제1실시예에 따른 스택 패키지(100)에서의 그것들과 동일하며, 여기서는 동일한 부분들에 대한 중복 설명은 생략하도록 한다.In addition, the remaining components in the stack package 200 according to the second embodiment of the present invention are the same as those in the stack package 100 according to the first embodiment described above, where duplicates of the same parts are provided. The description is omitted.

도 5는 본 발명의 제3실시예에 따른 스택 패키지를 도시한 단면도이다. 여기서, 도 1과 동일한 부분은 동일한 도면부호로 나타낸다. 5 is a cross-sectional view illustrating a stack package according to a third embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

도시된 바와 같이, 제1패키지(100a)의 제1봉지부재(150a)에 인접한 한 쌍의 제1접속패드들(114a)을 동시에 노출시키는 제2홀(H2)이 형성되어 있고, 상기 제2홀(H2) 내에 플렉서블 전도체(170)가 삽입되어 있으며, 그리고, 상기 플렉서블 전도체(170)가 삽입된 제2홀(H2) 내에 언더필(180)이 형성되어 있다. 이때, 상기 언더필(180)은 상기 제1 플렉서블 전도체(170) 내측에도 형성되어 있다. As illustrated, a second hole H2 is formed to simultaneously expose a pair of first connection pads 114a adjacent to the first encapsulation member 150a of the first package 100a. The flexible conductor 170 is inserted into the hole H2, and the underfill 180 is formed in the second hole H2 into which the flexible conductor 170 is inserted. In this case, the underfill 180 is also formed inside the first flexible conductor 170.

본 실시예에서, 상기 플렉서블 전도체(170)는 플렉서블 서킷 보드(172)의 일면 상에 형성된 구리패턴(174)이 상기 제2홀(H1)의 일측벽 및 이에 대향하는 타측벽 상에 상호 이격하여 각각 ㄷ자 모양 및 미러 ㄷ자 모양으로 배치되는 형상을 갖도록 마련되어 있다. In the present exemplary embodiment, the flexible conductor 170 has a copper pattern 174 formed on one surface of the flexible circuit board 172 so as to be spaced apart from each other on one side wall of the second hole H1 and the other side wall opposite thereto. It is provided so that it may have a shape arrange | positioned in a U shape and a mirror U shape, respectively.

그 밖에, 본 발명의 제3실시예에 따른 스택 패키지(300)에서의 나머지 구성요소들은 전술한 제1실시예에 따른 스택 패키지(100)에서의 그것들과 동일하며, 여기서는 동일한 부분들에 대한 중복 설명은 생략하도록 한다.In addition, the remaining components in the stack package 300 according to the third embodiment of the present invention are the same as those in the stack package 100 according to the first embodiment described above, and the overlapping of the same parts here. The description is omitted.

도 6은 본 발명의 제4실시예에 따른 스택 패키지를 도시한 단면도이다. 여기서, 도 1과 동일한 부분은 동일한 도면부호 나타낸다. 6 is a cross-sectional view illustrating a stack package according to a fourth embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

도시된 바와 같이, 제1패키지(100a)의 제1반도체칩(120a)과 제2패키지(100b)의 제2반도체칩(120b)은 와이어 본딩 방식이 아닌 플립 칩 본딩 방식에 의해 각각 제1기판(110a)과 제2기판(110b) 상에 페이스-타운 타입(face-down type)으로 배치되어 있다. As shown, the first semiconductor chip 120a of the first package 100a and the second semiconductor chip 120b of the second package 100b are each a first substrate by flip chip bonding instead of wire bonding. The face-down type is disposed on the 110a and the second substrate 110b.

이때, 상기 제1기판(110a)의 제1본드핑거들(112a) 및 상기 제2기판(110b)의 제2본드핑거들(112b)은 상기 제1반도체칩(120a)의 제1본딩패드(122a) 및 상기 제2반도체칩(120b)의 제2본딩패드(122b)에 대응하는 위치에 배치되어 있으며, 상기 제1반도체칩(120a)의 제1본딩패드(122a)와 상기 제1기판(110a)의 제1본드핑거(112a) 및 상기 제2반도체칩(120b)의 제2본딩패드(122b)와 상기 제2기판(110b)의 제2본드핑거(112b)는, 예를 들어, 범프와 같은 제1 및 제2 연결부재(140a, 140b)에 의해 상호 전기적으로 연결되어 있다. 상기 제1 및 제2 연결부재(140a, 140b)로서 상기 범프 이외에 솔더 등도 이용 가능하다. In this case, the first bond fingers 112a of the first substrate 110a and the second bond fingers 112b of the second substrate 110b are formed on the first bonding pads of the first semiconductor chip 120a. 122a) and the second bonding pad 122b of the second semiconductor chip 120b, respectively, and are disposed at a position corresponding to the first bonding pad 122a and the first substrate of the first semiconductor chip 120a. The first bond finger 112a of 110a and the second bonding pad 122b of the second semiconductor chip 120b and the second bond finger 112b of the second substrate 110b are bumps, for example. It is electrically connected to each other by the first and second connecting members (140a, 140b) such as. Solder or the like may be used as the first and second connection members 140a and 140b in addition to the bumps.

그 밖에, 본 발명의 제4실시예에 따른 스택 패키지(400)에서의 나머지 구성요소들은 전술한 제1실시예에 따른 스택 패키지(100)에서의 그것들과 동일하며, 여기서 동일한 부분들에 대한 중복 설명은 생략하도록 한다.In addition, the remaining components in the stack package 400 according to the fourth embodiment of the present invention are the same as those in the stack package 100 according to the first embodiment described above, where duplicates of the same parts are provided. The description is omitted.

도 7은 본 발명의 제5실시예에 따른 스택 패키지를 도시한 단면도이다. 여기서, 도 1과 동일한 부분들은 동일한 도면부호로 나타낸다. 7 is a cross-sectional view illustrating a stack package according to a fifth embodiment of the present invention. Here, the same parts as in Fig. 1 are designated by the same reference numerals.

도시된 바와 같이, 제2패키지(100b1, 100b2)가 제1패키지(100a) 상에 적어도 하나 이상, 예를 들어, 두 개가 스택되어 있다. 상기 스택된 제2패키지들(100b1, 100b2) 중에서 최상부에 배치되는 최상부 제2패키지(100b2)는 이전 실시예들의 그것들과 동일한 구조를 갖지며, 반면, 상기 최상부 제2패키지(100b2)를 제외하고 그 하부에 배치되는 나머지 제2패키지(100b1)들은 상기 제1패키지(100a)와 동일한 구조, 즉, 제2봉지부재(150b) 내에 상부에 배치되는 다른 제2패키지와의 전기적 연결을 위해 플렉서블 전도체(170)가 설치되어 있는 구조를 갖는다.As shown, at least one, for example, two, second packages 100b1 and 100b2 are stacked on the first package 100a. The top second package 100b2 disposed at the top of the stacked second packages 100b1 and 100b2 has the same structure as those of the previous embodiments, except for the top second package 100b2. The remaining second packages 100b1 disposed under the flexible conductors have the same structure as that of the first package 100a, that is, an electrical connection with another second package disposed above the second encapsulation member 150b. It has a structure in which 170 is provided.

상기 플렉서블 전도체(170)는, 전술한 바와 같이, 일면에 구리패턴이 형성된 플렉서블 서킷 보드가 상기 구리패턴이 외측면에 배치되게 원기둥 모양으로 말려져 있는 형상을 갖는다. 도시하지 않았으나, 상기 플렉서블 전도체(170)는 일면 상에 구리패턴이 형성된 플렉서블 서킷 보드가 단면이 지그재그로 절곡되게 구부려진 형상을 가질 수도 있다.As described above, the flexible conductor 170 has a shape in which a flexible circuit board having a copper pattern formed on one surface thereof is rolled in a cylindrical shape such that the copper pattern is disposed on an outer surface thereof. Although not shown, the flexible conductor 170 may have a shape in which a flexible circuit board having a copper pattern formed on one surface thereof is bent so as to be bent in a zigzag cross section.

본 실시예에서, 상기 플렉서블 전도체(170)는 제1패키지(100a) 및 상기 제1패키지(100a) 상에 스택되는 둘 이상의 제2패키지들(100b1, 100b2) 중에서 최상부 제2패키지(100b2)를 제외한 하부에 배치되는 나머지 제2패키지(100b1)에 각각 설치되어, 상기 제1패키지(100a)와 제2패키지(100b1) 사이 및 제2패키지들(100b1, 100b2)) 사이를 전기적으로 연결시킨다. In the present exemplary embodiment, the flexible conductor 170 may include a topmost second package 100b2 among the first package 100a and two or more second packages 100b1 and 100b2 stacked on the first package 100a. It is installed in each of the remaining second package (100b1) except the lower, it is electrically connected between the first package (100a) and the second package (100b1) and the second packages (100b1, 100b2).

이때, 상기 플렉서블 전도체(170)의 일측 부분은 대응하는 접속패드(114a, 114b)와 연결되며, 상기 일측 부분과 대향하고 상기 봉지부재(150a, 150b)의 표면으로 노출된 타측 부분은 제2패키지(110b1, 110b2)의 제2접속부재(160b)와 전기적으로 연결된다. In this case, one side portion of the flexible conductor 170 is connected to the corresponding connection pads 114a and 114b, and the other side portion facing the one side portion and exposed to the surfaces of the encapsulation members 150a and 150b is a second package. It is electrically connected to the second connection member 160b of 110b1 and 110b2.

그 밖에, 본 발명의 제5실시예에 따른 스택 패키지(500)에서의 나머지 구성요소들은 전술한 제1실시예에 따른 스택 패키지(100)에서의 그것들과 동일하며, 여기서 동일한 부분들에 대한 중복 설명은 생략하도록 한다.In addition, the remaining components in the stack package 500 according to the fifth embodiment of the present invention are the same as those in the stack package 100 according to the first embodiment described above, where duplicates of the same parts are provided. The description is omitted.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

100,200,30,400,500 : 스택 패키지
100a : 제1패키지 100b,100b1,100b2 : 제2패키지
110a : 제1기판 110b : 제2기판
112a : 제1본드핑거 112b : 제2본드핑거
114a : 제1접속패드 114b : 제2접속패드
116a : 제1볼랜드 116b : 제2볼랜드
120a : 제1반도체칩 120b : 제2반도체칩
122a : 제1본딩패드 122b : 제2본딩패드
130a : 제1접착부재 130b : 제2접착부재
140a : 제1연결부재 140b : 제2연결부재
150a : 제1봉지부재 150b : 제2봉지부재
160a : 제1접속단자 160b : 제2접속단자
170 : 플렉서블 전도체 172 : 플렉서블 서킷 보드
174 : 구리패턴 180 : 언더필
H1 : 제1홀 H2 : 제2홀 100,200,30,400,500: stack package
100a: first package 100b, 100b1,100b2: second package
110a: first substrate 110b: second substrate
112a: first bond finger 112b: second bond finger
114a: first connection pad 114b: second connection pad
116a: First Borland 116b: Second Borland
120a: first semiconductor chip 120b: second semiconductor chip
122a: first bonding pad 122b: second bonding pad
130a: first adhesive member 130b: second adhesive member
140a: first connecting member 140b: second connecting member
150a: first sealing member 150b: second sealing member
160a: first connection terminal 160b: second connection terminal
170: flexible conductor 172: flexible circuit board
174: copper pattern 180: underfill
H1: Hall 1 H2: Hall 2

Claims (19)

상면에 제1본드핑거들 및 제1접속패드들이 배치되고 하면에 제1볼랜드들이 배치된 제1기판과, 상기 제1기판의 상면 상에 배치되고 상기 제1본드핑거들과 전기적으로 연결된 제1본딩패드들을 구비한 제1반도체칩과, 상기 제1반도체칩을 밀봉하도록 상기 제1기판의 상면 상에 형성되고 상기 제1접속패드들을 노출시키는 홀들을 구비한 제1봉지부재,를 갖는 제1패키지;
상기 제1패키지 상에 스택되며, 상면에 제2본드핑거들이 배치되고 하면에 제2볼랜드들이 배치된 제2기판과, 상기 제2기판의 상면 상에 배치되고 상기 제2본드핑거들과 전기적으로 연결된 제2본딩패드들을 구비한 제2반도체칩과, 상기 제2반도체칩을 밀봉하도록 상기 제2기판의 상면 상에 형성된 제2봉지부재,를 갖는 제2패키지; 및
상기 제1봉지부재의 홀들 내에 상기 제1패키지와 제2패키지를 전기적으로 연결하도록 설치된 플렉서블 전도체;
를 포함하는 것을 특징으로 하는 스택 패키지. A first substrate having first bond fingers and first connection pads disposed on an upper surface thereof and first borlands disposed on a lower surface thereof; a first substrate disposed on an upper surface of the first substrate and electrically connected to the first bond fingers; A first encapsulation member having a first semiconductor chip having bonding pads, and a first encapsulation member formed on an upper surface of the first substrate to seal the first semiconductor chip and having holes exposing the first connection pads; package;
A second substrate stacked on the first package and having second bond fingers disposed on an upper surface thereof and second borlands disposed on a lower surface thereof; A second package having a second semiconductor chip having second bonding pads connected thereto, and a second encapsulation member formed on an upper surface of the second substrate to seal the second semiconductor chip; And
A flexible conductor installed in the holes of the first encapsulation member to electrically connect the first package and the second package;
Stack package comprising a. 제 1 항에 있어서,
상기 제1볼랜드에 부착된 제1접속단자를 더 포함하는 것을 특징으로 하는 스택 패키지. The method of claim 1,
And a first connection terminal attached to the first borland. 제 1 항에 있어서,
상기 플렉서블 전도체는, 그의 일부분이 상기 제1봉지부재로부터 노출되고, 상기 노출된 부분이 상기 제2볼랜드에 직접 연결된 것을 특징으로 하는 스택 패키지. The method of claim 1,
And wherein the flexible conductor is partially exposed from the first encapsulation member and the exposed portion is directly connected to the second borland. 제 3 항에 있어서,
상기 제2볼랜드에 부착되고 상기 제1봉지부재 내에 설치된 상기 플렉서블 전도체와 연결된 제2접속단자를 더 포함하는 것을 특징으로 하는 스택 패키지. The method of claim 3, wherein
And a second connection terminal attached to the second ball land and connected to the flexible conductor installed in the first encapsulation member. 제 4 항에 있어서,
상기 플렉서블 전도체는, 그의 일부분이 상기 제1봉지부재로부터 노출되고, 상기 노출된 부분이 상기 제2접속단자에 연결된 것을 특징으로 하는 스택 패키지. The method of claim 4, wherein
The flexible conductor may include a portion of which is exposed from the first encapsulation member, and the exposed portion is connected to the second connection terminal. 제 5 항에 있어서,
상기 제2접속단자는 솔더볼 또는 다른 플렉서블 전도체를 포함하는 것을 특징으로 하는 스택 패키지. The method of claim 5, wherein
And the second connection terminal comprises solder balls or other flexible conductors. 제 1 항에 있어서,
상기 플렉서블 전도체는 일면 상에 구리패턴이 형성된 플렉서블 서킷 보드가 상기 구리패턴이 외측면에 배치되게 원통형으로 말려진 형상을 갖는 것을 특징으로 하는 스택 패키지.The method of claim 1,
The flexible conductor is a stack package, characterized in that the flexible circuit board having a copper pattern formed on one surface has a shape in which the copper pattern is rolled in a cylindrical shape so as to be disposed on the outer surface. 제 1 항에 있어서,
상기 플렉서블 전도체는 일면 상에 구리패턴이 형성된 플렉서블 서킷 보드가 단면이 지그재그로 구부려진 형상을 갖는 것을 특징으로 하는 스택 패키지.The method of claim 1,
The flexible conductor is a stack package, characterized in that the flexible circuit board having a copper pattern formed on one surface has a shape in which a cross section is bent in a zigzag cross section. 제 1 항에 있어서,
상기 홀들은 상기 제1봉지부재 내에 상기 제1접속패드들을 각각 노출시키면서 상기 플렉서블 전도체가 각각 삽입되도록 형성된 것을 특징으로 하는 스택 패키지.The method of claim 1,
And the holes are formed such that the flexible conductors are respectively inserted while exposing the first connection pads in the first encapsulation member. 제 9 항에 있어서,
상기 플렉서블 전도체들이 삽입된 상기 홀들 내에 형성된 언더필을 더 포함하는 것을 특징으로 하는 스택 패키지.The method of claim 9,
And an underfill formed in the holes into which the flexible conductors are inserted. 제 1 항에 있어서,
상기 홀들은 인접하는 한 쌍의 제1접속패드를 동시에 노출시키도록 형성된 것을 특징으로 하는 스택 패키지.The method of claim 1,
And the holes are formed to simultaneously expose a pair of adjacent first connection pads. 제 11 항에 있어서,
상기 플렉서블 전도체는,
일면 및 이에 대향하는 타면을 갖는 플렉서블 서킷 보드와 상기 플렉서블 서킷 보드의 일면 상에 형성된 구리패턴을 포함하고,
상기 구리패턴이 상기 홀의 일측벽 및 이에 대향하는 타측벽 상에 상호 이격하여 ㄷ자 모양 및 미러 ㄷ자 모양으로 배치된 형상을 갖는 것을 특징으로 하는 스택 패키지.The method of claim 11,
The flexible conductor,
A flexible circuit board having one surface and the other surface opposite thereto and a copper pattern formed on one surface of the flexible circuit board,
The copper pattern is a stack package, characterized in that having a shape arranged in a U-shape and a mirror U-shaped spaced apart from each other on one side wall and the opposite side wall of the hole. 제 11 항에 있어서,
상기 플렉서블 전도체가 삽입된 상기 홀들 내에 형성된 언더필을 더 포함하는 것을 특징으로 하는 스택 패키지.The method of claim 11,
And an underfill formed in the holes into which the flexible conductor is inserted. 제 1 항에 있어서,
상기 제1본딩패드를 구비한 제1반도체칩 및 상기 제2본딩패드를 구비한 제2반도체칩은 각각 상기 제1본드핑거가 배치된 제1기판의 상면 및 상기 제2본드핑거가 배치된 제2기판의 상면 상에 페이스 업 타입으로 배치된 것을 특징으로 하는 스택 패키지.The method of claim 1,
Each of the first semiconductor chip having the first bonding pad and the second semiconductor chip having the second bonding pad may include a top surface of the first substrate on which the first bond finger is disposed and a second bond finger on which the second bond chip is disposed. A stack package, characterized in that it is disposed in the face up type on the upper surface of the two substrates. 제 14 항에 있어서,
상기 상기 제1반도체칩의 제1본딩패드와 상기 제1기판의 제1본드핑거 사이 및 상기 제2반도체칩의 제2본딩패드와 상기 제2기판의 제2본드핑거 사이를 전기적으로 연결하는 연결부재를 더 포함하는 것을 특징으로 하는 스택 패키지.The method of claim 14,
A connection electrically connecting between the first bonding pad of the first semiconductor chip and the first bond finger of the first substrate and between the second bonding pad of the second semiconductor chip and the second bond finger of the second substrate. The stack package further comprises a member. 제 15 항에 있어서,
상기 연결부재는 전도성 와이어 또는 패턴 필름을 포함하는 것을 특징으로 하는 스택 패키지.The method of claim 15,
The connection member stack package, characterized in that it comprises a conductive wire or pattern film. 제 1 항에 있어서,
상기 제1본딩패드를 구비한 제1반도체칩 및 상기 제2본딩패드를 구비한 제2반도체칩은 각각 상기 제1본드핑거가 배치된 제1기판의 상면 및 상기 제2본드핑거가 배치된 제2기판의 상면 상에 페이스 다운 타입으로 배치된 것을 특징으로 하는 스택 패키지.The method of claim 1,
Each of the first semiconductor chip having the first bonding pad and the second semiconductor chip having the second bonding pad may include a top surface of the first substrate on which the first bond finger is disposed and a second bond finger on which the second bond chip is disposed. 2. A stack package, characterized in that it is disposed in a face down type on an upper surface of a substrate. 제 17 항에 있어서,
상기 제1반도체칩의 제1본딩패드와 제1기판의 제1본드핑거 사이 및 상기 제2반도체칩의 제2본딩패드와 제2기판의 제2본드핑거 사이를 전기적으로 연결하는 연결부재를 더 포함하는 것을 특징으로 하는 스택 패키지. The method of claim 17,
A connection member electrically connecting between the first bonding pad of the first semiconductor chip and the first bond finger of the first substrate and between the second bonding pad of the second semiconductor chip and the second bond finger of the second substrate. Stack package comprising a. 제 18 항에 있어서,
상기 연결부재는 범프 또는 솔더를 포함하는 것을 특징으로 하는 스택 패키지.The method of claim 18,
The connection member stack package, characterized in that it comprises a bump or solder.
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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20060186540A1 (en) * 2005-02-23 2006-08-24 International Business Machines Corporation Method to create flexible connections for integrated circuits
KR20080058929A (en) * 2006-12-22 2008-06-26 삼성전자주식회사 Stacked semiconductor package formed with plug-and-socket wire connections
US20080315396A1 (en) * 2007-06-22 2008-12-25 Skyworks Solutions, Inc. Mold compound circuit structure for enhanced electrical and thermal performance
KR20100113676A (en) * 2009-04-14 2010-10-22 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060186540A1 (en) * 2005-02-23 2006-08-24 International Business Machines Corporation Method to create flexible connections for integrated circuits
KR20080058929A (en) * 2006-12-22 2008-06-26 삼성전자주식회사 Stacked semiconductor package formed with plug-and-socket wire connections
US20080315396A1 (en) * 2007-06-22 2008-12-25 Skyworks Solutions, Inc. Mold compound circuit structure for enhanced electrical and thermal performance
KR20100113676A (en) * 2009-04-14 2010-10-22 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

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