KR101035575B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, wherein a silicon oxide film is formed below a semiconductor substrate on which a high frequency device is to be formed, and a device isolation film using a deep trench is formed to completely block the high frequency device region electrically and physically. Provided is a method of manufacturing a semiconductor device capable of preventing noise and crosstalk between devices due to an oxide film and a region of a high frequency device that is three-dimensionally blocked by using an isolation film.

Silicon oxide, high frequency device, deep trench, field oxide

Description

Method of manufacturing a semiconductor device             

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 20 silicon oxide film

30: pad oxide film 40: pad nitride film

50: field oxide film 53: sidewall oxide film

56, 74: polysilicon film 60: device isolation film

70 well 72 gate oxide film

80 gate electrode 82 sidewall spacer

84 source / drain 90 interlayer insulating film

95: contact plug 100: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for electrical insulation of a high frequency device.

Conventional microwave circuits are mainly dominated by Hybrid Microwave ICs (HMICs). However, due to the rapid development of ultra-high frequency semiconductor technology since the 1980s, high-frequency semiconductor devices have gradually increased active and passive devices on a single semiconductor substrate. (Monolithic Microwave Integrated Circuit) has begun.

The MMIC is a circuit in which all active devices and passive devices are implemented on a single substrate, and a semiconductor used as a substrate of active devices is also used in the manufacture of a passive device, and all the high frequencies necessary for operating a microwave circuit on one substrate without a separate connection means are used. By implementing the semiconductor device, it has the advantage of being smaller in size and weight in several tens to hundreds of times compared to HMIC.

Manufacturing RF (Radio Frequency) semiconductor devices on existing silicon semiconductor substrates is highly compatible between processes, ensures stabilization of processes, and secures superiority in price competitiveness by using large-caliber substrates. However, since the silicon substrate is not an insulating layer, if a passive element such as an inductor or a capacitor is formed on the silicon substrate, the quality factor (hereinafter referred to as 'Q') of the passive element is low. . That is, Q is lowered due to energy loss caused by the EM field generated in the passive element on the silicon substrate without being blocked.

Therefore, in order to obtain high Q using the silicon semiconductor substrate, the distance between the passive element and the silicon substrate is far from each other. According to a general CMOS process, the distance between the passive element and the silicon substrate is formed within 5 μm, which is a limitation in improving Q. There is.

Conventionally, in the case of the RF device, since the device is separated using a potential difference, a signal generated during switching of a digital block (logic element area) may not be completely blocked, which may cause noise. Cut-off frequency (Ft) and Fmax (Mac Oscillation Frequency) can be reduced to adversely affect the operation of the device.

Accordingly, the present invention provides a method of manufacturing a semiconductor device that can completely block all regions where a high frequency device is formed in order to solve the above problems.

Providing a semiconductor substrate in which a first region in which a high frequency element is to be formed and a second region in which a logic element is to be formed are provided, forming a silicon oxide film in the semiconductor substrate in the first region; Forming a first device isolation film on the semiconductor substrate in a second region, forming a second device isolation film connected to the silicon oxide film on the semiconductor substrate in the first region, and forming a high frequency device transistor in the first region. And forming a transistor for logic elements in the second region.

Preferably, forming a silicon oxide film in the semiconductor substrate of the first region, forming a photoresist pattern that opens the first region, and using the photoresist pattern as an ion implantation mask, ions of 600 to 5000 KeV Performing an ion implantation process of implanting oxygen ions at a dose of 1E12 to 1E19atoms / cm 2 as an implantation energy, and performing a heat treatment process to form the silicon oxide film, wherein the heat treatment process is performed at 700 to 1200 ° C. carried out using a from 10 to 900 minutes in the furnace N ₂ / O ₂ atmosphere at a temperature, or may be performed using a 10 to 600 seconds in the RTP N ₂ / O ₂ atmosphere at a temperature of 700 to 1200 ℃.

Preferably, forming a first device isolation film on the semiconductor substrate in the second region, and forming a second device isolation film connected to the silicon oxide film on the semiconductor substrate in the first region may include a pad on the semiconductor substrate. Forming an oxide film and a pad nitride film, patterning the pad nitride film, the pad oxide film, and the semiconductor substrate in the second region to form a shallow trench, and forming a field oxide film so as to embed the shallow trench in the entire structure And then etching the pad nitride film to a predetermined thickness on the pad nitride film, and patterning the field oxide film, the pad nitride film, the pad oxide film, and the semiconductor substrate in the first region to form a deep trench. And forming a sidewall oxide film on the sidewalls and the bottom of the deep trench by performing a sidewall oxidation process. And embedding the polysilicon film so as to fill the deep trench, and then performing a planarization process using the pad nitride film as a stop film to form the first device separator in the second region, and the first region in the first region. The method may include forming the second device isolation layer that is deeper than the device isolation layer.

Preferably, the pad oxide layer may have a thickness of about 800 to 1200 Å and the deep trench may be formed to have a depth of about 3000 to 80000 Å to expose the silicon oxide layer of the first region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Like numbers refer to like elements in the figures.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a first region A in which a high frequency (RF) element is to be formed and a second region B in which a logic element is to be formed are defined in the semiconductor substrate 10. The silicon oxide film 20 is formed in the semiconductor substrate 10 in the first region A. FIG.                     

After the photoresist is coated on the semiconductor substrate 10, a photolithography process using a mask is performed to form a photoresist pattern (not shown) that opens the first region A. FIG. An ion implantation process using the photosensitive film pattern as an ion implantation mask is performed to form an oxygen ion layer in the semiconductor substrate 10. After removing the photoresist pattern, it is preferable to form a silicon oxide film 20 through a reaction between the semiconductor substrate 10 and the oxygen ion layer by performing a heat treatment process. It is preferable to form the silicon oxide film 20 deeper than the well region to be formed by a subsequent process.

In the ion implantation process, oxygen ions (O, O ₂ ) are preferably injected at a dose of 1E12 to 1E19 atoms / cm ₂ with ion implantation energy of 600 to 5000 KeV. The heat treatment step is preferably carried out for 10 to 900 minutes in an N ₂ / O ₂ atmosphere at a temperature of 700 to 1200 ℃ when using a furnace. That when using RTP, in N ₂ / O ₂ atmosphere at a temperature of 700 to 1200 ℃ 10 to about 600 seconds are preferred embodiments. If the temperature is higher than the above-mentioned temperature, the semiconductor substrate 10 is subjected to heat stress, and if it is lower than this, sufficient reaction between oxygen ions and silicon does not occur. In addition, the thickness of the oxide film to be formed may vary greatly depending on the process time and temperature described above. In this embodiment, it is preferable to form the silicon oxide film 20 to a thickness of 10 to 50000 microns.

By forming BOX (Buried Oxide) in the semiconductor substrate 10 of the first region A through ion implantation and heat treatment, it is possible to completely block the flow of electrons moving to the lower region of the well.                     

It is preferable to remove the oxide film on the surface of the semiconductor substrate 10 generated during the heat treatment process through a predetermined cleaning process. As a washing process, it is preferable to remove using HF aqueous solution (HF Wet Dip), or to carry out by dry etching (Dry Etch).

Referring to FIG. 1B, the pad oxide film 30 and the pad nitride film 40 are sequentially formed on the semiconductor substrate 10. A pad trench is formed by patterning the pad nitride film 40, the pad oxide film 30, and the semiconductor substrate 10 in the second region B. The trench trench is filled using the field oxide film 50, and then planarized to leave the field oxide film 50 on the pad nitride film 40.

In the patterning process, a photoresist is applied on the pad nitride layer 40, and then a photolithography process is performed using a mask to form a photoresist pattern (not shown) that opens the device isolation region (field region) in the second region (B). do. An etching process using the photoresist pattern as an etching mask is performed to remove the pad nitride layer 40 and the pad oxide layer 30, and then a portion of the semiconductor substrate 10 is continuously etched to form a shallow trench in the second region B. FIG. It is preferable to form The photoresist strip process is performed to remove the photoresist pattern.

After depositing the field oxide film 50 so that the trench is embedded in the entire structure in which the trench trench is formed, a planarization process is performed to remove the field oxide film 30 on the pad nitride film 40, but the pad nitride film 40 is disposed on the pad nitride film 40. It is effective to allow the field oxide film 30 of a predetermined thickness to remain. The planarization process is preferably carried out using a chemical mechanical polishing or a full surface etching process. The thickness of the field oxide film 30 remaining on the pad nitride film 40 is preferably about 800 to 1200 Å so that the thickness of the field oxide film 30 may be used as a hard mask film during the subsequent deep trench formation.

1C and 1D, the deep trench is formed by patterning the field oxide film 50, the pad nitride film 40, the pad oxide film 30, and the semiconductor substrate 10 in the first region A. FIG. Sidewall oxidation is performed to form sidewall oxide films 53 on the deep trench sidewalls and underneath. The device isolation layer 60 is formed by filling and planarizing the deep trench in which the sidewall oxide layer 53 is formed with the first polysilicon layer 56. The remaining field oxide film 50, the pad nitride film 40 and the pad oxide film 30 are removed.

The deep trench is formed by applying a photoresist on the field oxide layer 50 and then performing a photolithography process using a mask to form a photoresist pattern (not shown) that opens the deep trench region of the first region A. FIG. An etching process using the photoresist pattern as an etching mask is performed to remove the field oxide film 50. The deep trench is etched using the photoresist pattern and the field oxide layer 50 as an etching mask to etch the pad nitride layer 40, the pad oxide layer 30, and the semiconductor substrate 10 to form a deep trench. It is preferable to form a deep trench by etching the semiconductor substrate 10 until the silicon oxide film 20 formed in the semiconductor substrate 10 is exposed. It is desirable to perform certain stripping and cleaning processes to remove residues on the pad nitride and to remove the etch byproducts inside the deep trenches. The deep trench formed by the above-described process is preferably formed to a depth of about 3000 to 80000 mm 3. Most preferably, the deep trench is formed to a depth of 3000 to 50000 mm 3.

A sidewall oxide film 53 is formed on the sidewalls and the bottom of the deep trench through a wet or dry oxidation process, but preferably, the thickness is about 50 to 1500Å. This is because the oxidation of the oxide film and the silicon substrate is performed better than the sidewall of the nitride film, so that the thickness of the formed film can be different through sufficient oxidation. In this embodiment, it is desirable to allow sufficient sidewall oxidation.

The first polysilicon film 56 is applied so that the deep trench is embedded, and then the planarization process using the pad nitride film 40 as a stop film is performed to remove the first polysilicon film 56 on the pad nitride film 40. It is preferable. The planarization process is preferably performed by a chemical mechanical polishing process (CMP) or an entire surface etching process. In the second region B, a first device isolation layer 60b buried with the field oxide film 50 is formed, and in the first region A, the first side isolation film 53 and the first polysilicon film 56 are buried. The second device isolation layer 60a is formed. The filling of the deep trench with the first polysilicon film is because the gap filling ability is good and the oxidation can be easily performed in a subsequent process so that the polysilicon can be isolated.

It is preferable to remove the pad nitride film 40 remaining on the semiconductor substrate 10 through the nitride film strip process. It is preferable to remove the remaining pad oxide layer 30 through a predetermined etching process. A portion of the device isolation layer 60 protrudes onto the semiconductor substrate 10.

The second device isolation layer 60a using the deep trench and the lower silicon oxide film 20 may electrically insulate the high frequency device region to completely block the high frequency devices or between the logic devices and the high frequency devices. . In addition, noise may be prevented due to physical device isolation. In addition, cross talk between devices can be prevented.

Referring to FIG. 1E, the well 70 is formed in the first region A and the second region B by performing an ion implantation process. After forming the gate oxide film 72 and the second polysilicon film 74 on the entire structure, the gate electrode 80 is formed by patterning the second polysilicon film 74 and the gate oxide film 72. Predetermined gate ion implantation is performed in each region to form a high frequency device gate electrode 80a in the first region A, and the gate electrode 80b and 80c for logic device PMOS and NMOS in the second region B. ).

The well 70 preferably forms a P-wall 70a by forming a first ion implantation mask that opens the first region A, and then performing a predetermined ion implantation. At this time, the lower part of the well of the first region A is insulated by the silicon oxide film 20, and both sides thereof are insulated by the second device isolation layer 60a and are electrically isolated in three dimensions. Can be formed.

A second ion implantation mask that opens the N well 70b region of the second region B to form an N well 70b, and a second opening of the P well 70c region of the second region B. 3 ion implantation masks are formed to form P wells 70C.

It is preferable to form the gate oxide film 72 on the semiconductor substrate 10 on which the P wells and the N wells 70b and 70c are formed. It is effective to improve the characteristics of the gate oxide film 72 by performing a heat treatment process using NO gas to nitride the surface of the gate oxide film.                     

After forming the second polysilicon layer 74 on the entire structure, a gate mask pattern is formed to etch the second polysilicon layer 74 and the gate oxide layer 72 to form the gate electrode 80. After forming a first mask that opens the first region A, first gate ion implantation is performed to form a gate electrode 80a for high frequency device implanted with N + ions. PMOS and NMOS gate electrodes 80b for logic devices in which N + or P + ions are implanted by forming second and third masks for opening the NMOS and PMOS regions of the second region B, respectively, and implanting ions respectively. 80c).

Referring to FIG. 1F, sidewall spacers 82 are formed on sidewalls of the gate electrode 80. Source / drain 84 may be formed on both sides of the gate electrode 80. After the interlayer insulating film 90 is deposited on the entire structure, the interlayer insulating film 90 is patterned to form contact holes. The metallization process is performed to form the contact plug 95 and the metallization 100.

The sidewall spacers 82 may be formed by forming an insulating film on the entire structure, and then etching the entire surface to remove the insulating film in an area except the sidewall of the gate electrode 80. The source / drain 84 is preferably formed by implanting high concentration N-type (N +) ions into the semiconductor substrate 10 on both sides of the high-frequency device gate electrode 80a in the first region A. High concentration P type (P +) ions or high concentration N type (N +) ions are preferably formed in the semiconductor substrate 10 on both sides of the logic element PMOS and NMOS gate electrodes 80b and 80c of B).

The interlayer insulating film 90 is preferably formed using a PMD (Pre Metal Dielectric) film. By removing a portion of the interlayer insulating film 90 on the gate electrode 80 and the source / drain 84 through the patterning process, forming a contact hole to expose the gate electrode 80 and the source / drain 84. desirable.

In the metallization process, it is preferable to form the contact plug 95 by forming the contact plug 95 by planarizing the contact hole by using a conductive material film, depositing a conductive metal film thereon, and then patterning the contact hole 95 to form the metal wiring 100. Do. As the conductive material film, a polysilicon film, tungsten or aluminum film can be used. Moreover, copper, aluminum, tungsten can be used for a conductive metal film. The above-described process is applicable to MMIC to which GaAs or the like is applied, and can be applied to Bi CMOS directing.

As described above, the present invention can form a silicon oxide film under the semiconductor substrate on which the high frequency device is to be formed, and form a device isolation layer using a deep trench to completely block the high frequency device region electrically and physically.

In addition, the occurrence of noise and crosstalk between the devices can be prevented due to the high-frequency device region blocked in three dimensions by using the silicon oxide film and the device isolation film.

Claims (4)

(a) providing a semiconductor substrate defining a first region where a high frequency element is to be formed and a second region where a logic element is to be formed; (b) forming a silicon oxide film in the semiconductor substrate of the first region; (c) forming a first device isolation film on the semiconductor substrate in the second region, and forming a second device isolation film on the semiconductor substrate in the first region and connected with the silicon oxide film; And (d) forming a transistor for a high frequency device in the first region and forming a transistor for a logic device in the second region. According to claim 1, wherein step (b), Forming a photoresist pattern that opens the first region; Performing an ion implantation process using the photoresist pattern as an ion implantation mask and implanting oxygen ions at a dose of 1E12 to 1E19 atoms / cm 2 at an ion implantation energy of 600 to 5000 KeV; And Performing a heat treatment process to form the silicon oxide film, The heat treatment step is a step 700 to a temperature of 1200 ℃ in N ₂ / O ₂ atmosphere, carried out using a furnace 10 to 900 minutes, or at a temperature of 700 to 1200 ℃ in N ₂ / O ₂ atmosphere using a 10 to 600 seconds RTP The manufacturing method of the semiconductor device performed by carrying out. The method of claim 1, wherein step (c) comprises: Forming a pad oxide film and a pad nitride film on the semiconductor substrate; Patterning the pad nitride film, the pad oxide film, and the semiconductor substrate in the second region to form a shallow trench; Applying a field oxide layer to fill the trench trench over the entire structure, and then etching the field oxide layer to a predetermined thickness on the pad nitride layer; Patterning the field oxide film, the pad nitride film, the pad oxide film, and the semiconductor substrate in the first region to form a deep trench; Performing a sidewall oxidation process to form a sidewall oxide film on the sidewalls and the bottom of the deep trench; And Embedding the polysilicon layer to fill the deep trench, and then performing a planarization process using the pad nitride layer as a stop layer to form the first device separator in the second region, and the first device in the first region. Forming the second device isolation layer that is deeper than the separation film. The method of claim 3, wherein And leaving the field oxide film 800 to 1200 막 thick on the pad nitride film and the deep trench formed at a depth of 3000 to 80000 Å so that the silicon oxide film of the first region is exposed.

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