KR101008676B1 - Printed Circuit Board Manufacturing Method - Google Patents

Abstract

Disclosed is a method of manufacturing a printed circuit board. Forming a first circuit pattern, forming a bump in the first circuit pattern, laminating an insulating material on the first circuit pattern such that the first circuit pattern is filled by the insulating material and the insulating material is penetrated by the bump, the insulating material A method of manufacturing a printed circuit board comprising: forming a second circuit pattern on the substrate, and pressing the second circuit pattern to embed the second circuit pattern in an insulating material, while simultaneously manufacturing a micro circuit pattern and a high density circuit pattern. The process costs and time can be reduced, and the insulation reliability between patterns can be improved.

Printed Circuit Board, Buried Pattern, Fine Pattern

Description

Manufacturing Method for Printed Circuit Board {Method For Manufacturing Printed Circuit Board}

The present invention relates to a printed circuit board manufacturing method.

With the development of the electronic industry, the demand for high functionalization, miniaturization, price competitiveness and short delivery time of electronic components is increasing rapidly. To respond to this trend, package substrate makers are applying a semi-additive process (SAP) to cope with the trend of thinning and high density of substrates.

The semi-additive method can implement a high density circuit pattern, but the number of processes increases when the circuit pattern and the via are formed, and additional costs are added to the manufacturing process. Desmearing and chemical copper plating of the substrate surface and the inside of the processing hole are costly and time consuming.

According to the prior art, a processing hole is formed in a double-sided copper-clad laminate, a desmear treatment is performed on the inner wall of the processing hole and the substrate surface, and chemical copper plating is performed. Then, the electroplating is performed on the chemical copper plating layer to form circuit patterns and vias. In the conventional method, the inside of the processing hole is plated for interlayer connection after forming the processing hole. In such a process of plating the inner wall of the processing hole, the thickness of the substrate surface is increased, thereby making it difficult to form a microcircuit.

The present invention provides a method of manufacturing a printed circuit board that can reduce the time and cost required for the manufacturing process while manufacturing a thinner and denser substrate.

According to an aspect of the present invention, forming a first circuit pattern, forming a bump in the first circuit pattern, the first circuit pattern so that the first circuit pattern is embedded by the insulating material and the insulating material is penetrated by the bump A method of manufacturing a printed circuit board is provided, which is performed by laminating an insulating material on the substrate, forming a second circuit pattern on the insulating material, and pressing the second circuit pattern so that the second circuit pattern is embedded in the insulating material.

The forming of the bumps on the first circuit pattern may be performed by printing silver ink on the first circuit pattern.

The forming of the first circuit pattern may include providing a carrier having a metal layer laminated on one surface thereof, laminating a photosensitive material on the metal layer, forming a plating resist by selectively exposing and developing the photosensitive material, and forming a plating resist on the metal layer. It can be carried out by forming a conductive material.

In this case, the metal layer stacked on the carrier may include a first metal layer formed on the carrier and a second metal layer formed on the first metal layer.

The first metal layer may be made of a material containing copper (Cu), and the second metal layer may be made of a material containing nickel (Ni).

The forming of the second circuit pattern on the insulating material may include forming a conductive layer on the insulating material and the bump, removing a carrier, forming an etching resist on the conductive layer, and etching the conductive layer and the first metal layer. It can be carried out as.

The forming of the conductive layer on the insulating material and the bump may be performed by pressing the conductive layer on the insulating material so that the conductive layer is electrically connected to the bump through a pressing process.

In addition, after the step of forming the second circuit pattern, the step of removing the second metal layer may be further performed.

Removing the second metal layer may be performed by supplying an etching solution to etch the second metal layer.

Meanwhile, the forming of the second circuit pattern on the insulating material may include forming a seed layer on the insulating material and the bump, removing a carrier, forming a plating resist on the seed layer and the metal layer, and forming a conductive material on the seed layer. It may be carried out by removing the plating resist, etching the seed layer and the metal layer.

Herein, the step of forming the seed layer on the insulating material and the bump may be performed by pressing the seed layer on the insulating material so that the seed layer is electrically connected to the bump through a pressing process.

And comprising: first circuit forming a pattern, comprising: providing a metal layer is laminated carrier to a surface, the method comprising: depositing a photosensitive material on the metal layer, selectively exposing the photosensitive material to form an etching resist, by development, the metal layer Etching may be performed.

In this case, the forming of the second circuit pattern on the insulating material may include forming a conductive layer on the insulating material and the bump, removing a carrier, forming an etching resist on the conductive layer and the first circuit pattern, and forming the conductive layer. Etching may be performed.

The forming of the conductive layer on the insulating material and the bump may be performed by pressing the conductive layer on the insulating material so that the conductive layer is electrically connected to the bump through a pressing process.

According to the embodiment of the present invention, while implementing a fine circuit pattern and a high density circuit pattern, it is possible to reduce the cost and time required for the manufacturing process, and to improve the insulation reliability between the patterns.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, an embodiment of a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings, and in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate explanations will be omitted.

1 is a flowchart illustrating a method of manufacturing a printed circuit board according to a first embodiment of the present invention, and FIGS. 2 to 11 are flowcharts illustrating a process of manufacturing a printed circuit board according to the first embodiment of the present invention. 2 to 11, the first circuit pattern 10, the second circuit pattern 20, the bump 30, the insulating material 40, the carrier 50, the metal layer 52, and the first metal layer 54. ), The second metal layer 56, the plating resist 60, the conductive layer 62, and the etching resist 64 are shown.

According to the first exemplary embodiment of the present invention, as shown in FIGS. 2 to 4, the first circuit pattern 10 is formed on the carrier 50 (S100).

First, as shown in FIG. 2, a carrier 50 having a metal layer 52 stacked on one surface thereof is provided (S111). The carrier is a support on which the first circuit pattern 10 can be formed. The carrier supports the first circuit pattern so that the lamination process of the insulating material 40 can proceed after the first circuit pattern is formed. According to the present embodiment, the first metal layer 54 and the second metal layer 56 are formed on the carrier. The first metal layer 54 may be formed on the carrier, and the second metal layer 56 may be formed on the first metal layer by electroplating.

The first metal layer 54 and the second metal layer 56 may be formed of different materials. The first metal layer 54 may be removed by an etching solution when the conductive layer 62 is etched in forming the second circuit pattern 20 to be described later. That is, the first metal layer 54 may be made of a material that can be etched by the same etching solution as the second circuit pattern 20. In the present embodiment, the first metal layer may be made of a material including copper (Cu) as in the second circuit pattern.

In the present embodiment, the second metal layer 56 serves as a seed layer when the first circuit pattern 10 is formed. In addition, in the step of forming the second circuit pattern 20 serves to block the first circuit pattern 10 from etching from the etching solution. Accordingly, the second metal layer 56 may be formed of a material different from that of the second circuit pattern 20 and the first metal layer 54, so that the second metal layer 56 may be etched in an etching solution in which the first metal layer 54 is etched. It must not be etched by In the present embodiment, the second metal layer 56 may be made of a material including nickel (Ni).

Then, a photosensitive material is laminated on the carrier 50, that is, on the second metal layer 56 of the carrier (S112). Then, the photosensitive material is selectively exposed and developed by using a photo mask or the like to remove a part. That is, the plating resist 60 is formed on the second metal layer 56 as shown in FIG. 3 by performing a photolithography method (S113). The plating resist is formed corresponding to the shape of the first circuit pattern 10 to be formed on the second metal layer 56. That is, the second metal layer of the portion corresponding to the first circuit pattern is not covered by the plating resist 60 and is exposed to the outside.

Then, a conductive material is formed on the second metal layer 56 (S114). As shown in FIG. 3, electroplating is performed in a state in which a plating resist 60 that selectively covers the second metal layer 56 is formed. In the electrolytic plating process, a conductive material may be formed on the second metal layer 56 not covered by the plating resist.

After the conductive material is formed on the second metal layer 56 through electrolytic plating, the plating resist 60 is peeled off. By removing the plating resist, the first circuit pattern 10 may be formed on the second metal layer 56 as shown in FIG. 4. In the present embodiment, the conductive material may be copper (Cu).

Then, bumps 30 are formed on the first circuit pattern 10 as shown in FIG. 5 (S120). The bumps electrically conduct the first circuit pattern and the second circuit pattern 20 to be described later. The bumps 30, which serve as electrical conduction, may be formed of a conductive material. According to the present embodiment, the process of forming the bumps 30 in the first circuit pattern may be performed by printing silver (Ag) ink on the first circuit pattern 10. The silver ink is printed on a part of the first circuit pattern, that is, the bump 30, which is designed for interlayer conduction. As the silver ink is cured, the conductive bumps 30 may be formed on the first circuit pattern as shown in FIG. 5. In this embodiment, although silver ink is used, various materials of conductive materials such as solder ink may be used.

Then, as shown in FIG. 6, the insulating material 40 is laminated on the first circuit pattern 10 (S130). By stacking the insulating material 40, the first circuit pattern is embedded in the insulating material. Between each pattern of the first circuit pattern 10 may be filled with an insulating material (40). In this embodiment, the insulating material 40 may be laminated in a semi-cured state. Therefore, the first circuit pattern may be buried by an insulating material. And while the insulating material is laminated, the insulating material is penetrated by the conductive bumps 30. As shown in FIG. 6, the insulating material 40 penetrates through the bump 30, and an upper end of the bump 30 is exposed to the outside of the insulating material.

Then, as illustrated in FIGS. 7 to 9, the second circuit pattern 20 is formed on the insulating material 40 (S140). As shown in FIG. 7, the conductive layer 62 is laminated on the insulating material and the bumps 30 (S141). The conductive layer 62 is formed to cover the insulating material and the bumps exposed to the outside of the insulating material. The conductive layer is a metal layer to be the second circuit pattern 20. In the present embodiment, the conductive layer 62 may be a copper foil layer. The conductive layer may be formed by prepressing the copper foil layer on the insulating material 40 at high temperature and high pressure. In the process of pressing the conductive layer onto the insulating material, the conductive layer may be electrically connected to the conductive bumps.

In this embodiment, the press process may be performed at a pressure of 5 ~ 30 kgf / cm ² and a temperature of 150 ℃ or more. The carrier bonded to the first metal layer may be separated from the first metal layer 54 during a high temperature and high pressure press process. That is, after the process of stacking the conductive layer 62, the carrier 50 may be removed (S142).

Then, the etching resist 64 is formed on the conductive layer 62 as shown in FIG. 8 (S143). The etching resist can be formed by performing a photolithography process on the photosensitive insulating material. Etch resist 64 selectively covers conductive layer 62.

Next, as illustrated in FIG. 9, the conductive layer 62 and the first metal layer 54 which are not covered by the etching resist 64 are etched (S144). According to the present embodiment, both the conductive layer 62 and the first metal layer 54 are made of copper (Cu) material. The conductive layer 62 and the first metal layer 54 may be etched by supplying an etching solution in which the copper (Cu) metal layer may be etched. By performing the etching process, the conductive layer 62 not covered by the etching resist 64 may be selectively etched, and the first metal layer 54 may be removed.

Here, the etching solution in which the copper (Cu) metal layer may be etched may not etch the second metal layer 56 made of nickel (Ni). Even if the first metal layer 54 is removed, the second metal layer is not etched by the etching solution. Therefore, the first circuit pattern 10 is prevented from being etched by the second metal layer 56.

After the etching process is finished, the second resist pattern 20 may be formed on the insulating material 40 as shown in FIG. 9 by peeling off the etching resist 64.

Next, as shown in FIG. 10, the second circuit pattern 20 is embedded in the insulating material 40 by pressing the second circuit pattern 20 (S150). As shown in FIG. 9, the second circuit pattern is exposed to the insulating material. The press process is performed while the second circuit pattern is exposed. Since the second circuit pattern is embedded in the insulating material, insulation reliability between the patterns may be improved.

Then, as illustrated in FIG. 11, the second metal layer 56 covering the first circuit pattern 10 is removed (S160). The second metal layer 56 made of a material different from that of the first metal layer 54 protects the first circuit pattern without being etched in the process of forming the second circuit pattern 20.

According to the present exemplary embodiment, the second metal layer 56 of nickel (Ni) material may be removed by an etching solution that cannot etch the first circuit pattern 10 and the second circuit pattern 20 of copper (Cu) material. Can be. By using an etching solution to selectively etch only the second metal layer 56, the second metal layer may be removed as shown in FIG.

According to the first embodiment of the present invention, the first circuit pattern 10 is formed of a high density pattern of 10/10 to 15/15 um (Line / Space) by the SAP (Semi Additive Process) method, and the second circuit pattern 20 ) Can be formed in a 20/20 ~ 25 / 25um (Line / Space) in a subtractive manner. The fine pattern of the first circuit pattern 10 may be used for the mounting surface of the electronic device that requires the implementation of the fine circuit pattern, and the second circuit pattern 20 may be used for the bump or solder ball joint surface for connection to the outside.

According to the first embodiment of the present invention, a circuit pattern may be formed in each of a semi additive process (SAP) or a subtractive method according to a portion to which a printed circuit board is applied. Therefore, it is possible to reduce the number of expensive desmear and chemical copper processes required by the SAP method while realizing fine circuit patterns and high density circuit patterns. In addition, the process time required for the electroplating process can be reduced.

In addition, as shown in FIG. 11, the first circuit pattern 10 and the second circuit pattern 20 may be embedded in the insulating material 40 to provide a printed circuit board that is thin and has improved insulation reliability.

Hereinafter, a method of manufacturing a printed circuit board according to a second embodiment of the present invention will be described with reference to FIGS. 12 to 22.

12 is a flowchart illustrating a method of manufacturing a printed circuit board according to the second embodiment of the present invention, and FIGS. 13 to 22 are flowcharts illustrating a process of manufacturing a printed circuit board according to the second embodiment of the present invention. 13 to 22, the first circuit pattern 10, the second circuit pattern 20, the bump 30, the insulating material 40, the carrier 50, the metal layer 52, and the plating resist 60 are described. Seed layer 70 and plating resist 72 are shown.

According to the second embodiment of the present invention, as shown in FIGS. 13 to 15, the first circuit pattern 10 is formed on the carrier 50 (S210).

According to the present exemplary embodiment, as shown in FIG. 13, a carrier 50 having a metal layer 52 stacked on one surface thereof is provided (S211). The carrier is a support on which the first circuit pattern 10 can be formed, as described in the first embodiment, and supports the first circuit pattern so that the lamination process of the insulating material 40 can proceed after the first circuit pattern is formed. .

Then, a photosensitive material is laminated on the carrier 50, that is, on the metal layer 52 of the carrier (S212). Then, the photosensitive material is selectively exposed and developed by using a photo mask or the like to remove a part. That is, by performing a photolithography method, the plating resist 60 is formed on the metal layer 52 of the carrier (S213). The plating resist is formed corresponding to the shape of the first circuit pattern 10 to be formed on the metal layer 52. That is, the metal layer 52 of the portion corresponding to the first circuit pattern is not covered by the plating resist 60 and is exposed to the outside.

Then, a conductive material is formed on the metal layer 52 (S214). As shown in FIG. 14, electroplating is performed in a state where a plating resist 60 selectively covering the metal layer is formed. In the electrolytic plating process, a conductive material may be formed on the metal layer not covered by the plating resist.

After the conductive material is formed on the metal layer 52 through electrolytic plating, the plating resist is peeled off. By removing the plating resist 60, the first circuit pattern 10 may be formed on the metal layer as shown in FIG. 15. In the present embodiment, the conductive material may be copper (Cu).

Then, as illustrated in FIG. 16, the conductive bumps 30 are formed on the first circuit pattern 10 (S220). Next, as shown in FIG. 17, the insulating material 40 is laminated on the first circuit pattern 10 so that the first circuit pattern is embedded in the insulating material 40 (S230). The bumps 30 pass through the insulating material and are exposed to the outside. In the present embodiment, forming the bump 30 on the first circuit pattern (S220) and laminating an insulating material on the first circuit pattern (S230) may be performed by the same process as in the first embodiment of the present invention. have. Materials of the conductive bumps 30 and the insulating material may also be used in the same manner as in the first embodiment.

Then, as shown in FIGS. 18 to 21, the second circuit pattern 20 is formed on the insulating material 40 (S240). In the present embodiment, the second circuit pattern may be formed in a semi-additive process (SAP).

As illustrated in FIG. 18, the seed layer 70 is formed on the insulating material 40 and the bump 30 (S241). The seed layer is formed to cover the insulating material and the bumps exposed to the outside of the insulating material. The seed layer is also electrically connected to the bumps. The seed layer 70 is a base layer on which the second circuit pattern 20 is formed in the electroplating process. In the second embodiment of the present invention, the seed layer 70 may be a thin copper foil layer (about 1 to 3 μm) on which the second circuit pattern 20 made of copper (Cu) may be formed during the electroplating process. . In this embodiment, the seed layer 70 may be formed by pressing the copper foil layer on the insulating material at a high temperature and high pressure as described in the first embodiment.

In addition, as described in the first embodiment, the carrier 50 bonded to the metal layer 52 may be separated from the metal layer 52 in the press process of high temperature and high pressure. That is, after the process of stacking the seed layer 70, the carrier 50 may be removed (S242).

Then, as shown in FIG. 19, a plating resist 72 is formed on the seed layer 70 and the metal layer 52 (S243). The plating resist 72 may be formed by performing a photolithography process on the photosensitive insulating material. The plating resist covers the metal layer 52 as a whole and selectively covers the conductive layer.

The plating resist 72 is formed so that the seed layer 70 corresponding to the shape of the second circuit pattern 20 is opened. Electrolytic plating is performed to form a conductive material on the seed layer 70 not covered by the plating resist (S244). The conductive material formed on the seed layer becomes the second circuit pattern 20. Thus, the conductive material may be copper (Cu).

After the electroplating process is completed, the plating resist 72 is removed as shown in FIG. 20 (S245). As the plating resist is peeled off, the seed layer 70 and the metal layer 52 are exposed to the outside.

Next, as illustrated in FIG. 21, the seed layer 70 and the metal layer 52 exposed to the outside are etched (S246). The seed layer 70 formed between the patterns of the second circuit patterns 20 is flash etched. Then, the metal layer 52 covering the first circuit pattern 10 is etched. According to the second embodiment of the present invention, an etching solution may be supplied to etch the seed layer 70 and the metal layer 52, which are metallic materials. In the state in which the seed layer and the metal layer are etched, the first circuit pattern is embedded in the insulating material 40, but the second circuit pattern 20 is formed on the insulating material 40.

Next, as shown in FIG. 22, the second circuit pattern 20 is buried in the insulating material by pressing the second circuit pattern 20 formed on the insulating material 40 (S250). As shown in FIG. 21, the second circuit pattern is exposed to the insulating material 40. The press process is performed while the second circuit pattern is exposed. Since the second circuit pattern is embedded in the insulating material, insulation reliability between the patterns may be improved.

According to the second embodiment of the present invention, the first circuit pattern 10 and the second circuit pattern 20 may be formed as a high density fine pattern of 10/10 to 15/15 um (Line / Space) by a SAP (Semi Additive Process) method. Can be formed. By forming a fine circuit pattern, a fine pitch that is advantageous for mounting and wire bonding of an electronic device may be realized.

In addition, as shown in FIG. 22, the first circuit pattern and the second circuit pattern may be embedded in the insulating material 40, thereby providing a printed circuit board having a reduced thickness and improved insulation reliability.

Hereinafter, a method of manufacturing a printed circuit board according to a third embodiment of the present invention will be described with reference to FIGS. 23 to 32.

23 is a flowchart illustrating a method of manufacturing a printed circuit board according to the third embodiment of the present invention, and FIGS. 24 to 32 are flowcharts illustrating a process of manufacturing a printed circuit board according to the third embodiment of the present invention. 24 to 32, the first circuit pattern 10, the second circuit pattern 20, the bump 30, the insulating material 40, the carrier 50, the metal layer 52, and the etching resist 80. , Conductive layer 82 and etching resist 84 are shown.

According to the third embodiment of the present invention, as shown in FIGS. 24 to 26, the first circuit pattern 10 is formed on the carrier (S310).

According to the present exemplary embodiment, as shown in FIG. 24, a carrier 50 having a metal layer 52 stacked on one surface thereof is provided (S311). The carrier is a support on which the first circuit pattern 10 can be formed, as described in the first embodiment, and supports the first circuit pattern so that the lamination process of the insulating material can proceed after the first circuit pattern 10 is formed. .

Then, the photosensitive material is laminated on the carrier 50, that is, on the metal layer 52 of the carrier (S312). Then, the photosensitive material is selectively exposed and developed by using a photo mask or the like to remove a part. That is, by performing a photolithography method, an etching resist 80 is formed on the metal layer 52 of the carrier as shown in FIG. 25 (S313). The etching resist 80 covers the metal layer of the portion corresponding to the first circuit pattern 10.

In the third embodiment of the present invention, the first circuit pattern 10 is formed by selectively etching the metal layer 52. In the state where the etching resist 80 is formed on the metal layer 52, the etching solution is supplied to selectively etch the metal layer (S314). The metal layer covered by the etch resist 80 remains in the carrier 50 without being etched. Accordingly, by removing the etching resist 80, the first circuit pattern 10 may be formed on the carrier 50 as shown in FIG. 26.

Then, as illustrated in FIG. 27, the conductive bumps 30 are formed on the first circuit pattern 10 (S320). Next, as shown in FIG. 28, the insulating material 40 is laminated on the first circuit pattern so that the first circuit pattern is embedded in the insulating material 40 (S330). The bumps 30 pass through the insulating material and are exposed to the outside. In the present embodiment, the step of forming bumps on the first circuit pattern (S320) and the step of stacking the insulating material 40 on the first circuit pattern 10 (S330) are performed in the same process as in the first embodiment of the present invention. Can be performed. Materials of the conductive bumps and the insulating material 40 may also be used in the same manner as in the first embodiment.

Then, as shown in FIGS. 29 to 31, the second circuit pattern 20 is formed on the insulating material 40 (S340). As shown in FIG. 29, the conductive layer 82 is laminated on the insulating material and the bumps 30 (S341). The conductive layer 82 is formed to cover the insulating material and the bumps exposed to the outside of the insulating material. The conductive layer is a metal layer to be the second circuit pattern 20. In the present embodiment, the conductive layer may be a copper foil layer. The conductive layer 82 may be formed by pressing the copper foil layer on the insulating material 40 at high temperature and high pressure as described in the first embodiment of the present invention. The conductive layer may be electrically connected to the bump through the pressing process.

In a third embodiment of the present invention, the press process may be performed at a pressure of 5 ~ 30 kgf / cm ² and a temperature of 150 ℃ or more. The carrier 50, which is bonded to the insulating material 40 and the first circuit pattern 10, may be separated from the insulating material and the first circuit pattern 10 in the press process of high temperature and high pressure. That is, after the process of stacking the conductive layer 82, the carrier may be removed (S342).

Then, an etching resist 84 is formed on the conductive layer 82 and the first circuit pattern 10 as shown in FIG. 30 (S343). As described in the first embodiment, the etching resist 84 may be formed by performing a photolithography process on the photosensitive insulating material laminated on the conductive layer 82. The first circuit pattern 10 and the insulating material 40 are both covered by the etching resist 84. On the other hand, the etching resist 84 partially covers the conductive layer 82. That is, the etching resist 84 covers the portion of the conductive layer 82 to be formed and left as the second circuit pattern 20.

As shown in FIG. 30, the etching solution is supplied while the etching resist 84 is formed to selectively etch the conductive layer 82 (S344). Portions of the first circuit pattern 10, the insulating material 40, and the conductive layer 82 covered by the etching resist 84 are not etched. After the etching process is finished, the second circuit pattern 20 may be formed on the insulation 40 by removing the etching resist 84.

Then, as shown in FIG. 32, the second circuit pattern 20 is embedded in the insulating material 40 by pressing the second circuit pattern 20 (S350). As shown in FIG. 31, the second circuit pattern is exposed to the insulating material. The press process is performed while the second circuit pattern is exposed. Since the second circuit pattern is embedded in the insulating material, insulation reliability between the patterns may be improved.

According to the third embodiment of the present invention, the number of expensive desmear and chemical copper processes required by the SAP method can be reduced by forming the first circuit pattern 10 and the second circuit pattern 20 in the subtractive method. have. In addition, the process time required for the electroplating process can be reduced.

The first circuit pattern 10 formed according to the third embodiment of the present invention is formed through an etching process. Therefore, the width of the upper part of the pattern exposed to the outside is wider under the pattern embedded in the insulating material 40 due to the nature of the etching process. That is, the cross section of the circuit pattern is formed in a trapezoidal shape by side etching. Since the upper area of the first circuit pattern 10 is formed to be wide, the bonding area of the wire bonding may be increased during wire bonding. Therefore, the reliability of wire bonding can be improved.

In addition, as shown in FIG. 32, the first circuit pattern 10 and the second circuit pattern 20 may be embedded in the insulating material 40 to provide a printed circuit board that is thin and has improved insulation reliability.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

1 is a flow chart showing a printed circuit board manufacturing method according to a first embodiment of the present invention.

2 to 11 are flowcharts showing a printed circuit board manufacturing process according to the first embodiment of the present invention.

12 is a flow chart showing a printed circuit board manufacturing method according to a second embodiment of the present invention.

13 to 22 are flowcharts illustrating a printed circuit board manufacturing process according to the second embodiment of the present invention.

23 is a flowchart showing a method of manufacturing a printed circuit board according to the third embodiment of the present invention.

24 to 32 are flow charts showing a printed circuit board manufacturing process according to the third embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: first circuit pattern 20: second circuit pattern

30: bump 40: insulation material

50: carrier 52: metal layer

54: first metal layer 56: second metal layer

60: plating resist 62: conductive layer

64: etching resist 70: seed layer

72: plating resist 80: etching resist

82: conductive layer 84: etching resist

Claims (15)

Forming a first circuit pattern; Forming bumps on the first circuit pattern; Stacking the insulating material on the first circuit pattern such that the first circuit pattern is filled by an insulating material and the insulating material is penetrated by the bumps; Forming a second circuit pattern on the insulating material; And Pressurizing the second circuit pattern so that the second circuit pattern is embedded in the insulating material, Forming the first circuit pattern, Providing a carrier having a metal layer laminated on one surface thereof; Forming a plating resist on the metal layer; And Forming a conductive material on the metal layer; The metal layer is A first metal layer formed on the carrier; And Printed circuit board manufacturing method comprising a second metal layer formed on the first metal layer. The method of claim 1, Forming bumps on the first circuit pattern is performed by printing silver ink on the first circuit pattern. delete delete The method of claim 1, The first metal layer is a printed circuit board manufacturing method, characterized in that made of a material containing copper (Cu). The method of claim 1, The second metal layer is a printed circuit board manufacturing method, characterized in that made of a material containing nickel (Ni). The method of claim 1, Forming a second circuit pattern on the insulating material, Forming a conductive layer on the insulating material and the bumps; Removing the carrier; Forming an etching resist on the conductive layer; And etching the conductive layer and the first metal layer. The method of claim 7, wherein Forming a conductive layer on the insulating material and the bump, And pressing the conductive layer against the insulating material so that the conductive layer is electrically connected to the bump through a pressing process. The method of claim 7, wherein After pressing the second circuit pattern, Removing the second metal layer further comprises a printed circuit board manufacturing method. 10. The method of claim 9, Removing the second metal layer, And etching the second metal layer by supplying an etching solution. Forming a first circuit pattern; Forming bumps on the first circuit pattern; Stacking the insulating material on the first circuit pattern such that the first circuit pattern is filled by an insulating material and the insulating material is penetrated by the bumps; Forming a second circuit pattern on the insulating material; And Pressurizing the second circuit pattern so that the second circuit pattern is embedded in the insulating material, Forming the first circuit pattern, Providing a carrier having a metal layer laminated on one surface thereof; Forming a plating resist on the metal layer; And Forming a conductive material on the metal layer; Forming a second circuit pattern on the insulating material, Forming a seed layer on the insulating material and the bumps; Removing the carrier; Forming a plating resist on the seed layer and the metal layer; Forming a conductive material in the seed layer; Removing the plating resist; And etching the seed layer and the metal layer. The method of claim 11, Forming a seed layer on the insulating material and the bump, And pressurizing the seed layer on the insulating material so that the seed layer is electrically connected to the bump through a pressing process. Forming a first circuit pattern; Forming bumps on the first circuit pattern; Stacking the insulating material on the first circuit pattern such that the first circuit pattern is filled by an insulating material and the insulating material is penetrated by the bumps; Forming a second circuit pattern on the insulating material; And Pressurizing the second circuit pattern so that the second circuit pattern is embedded in the insulating material, Forming the first circuit pattern, Providing a carrier having a metal layer laminated on one surface thereof; Forming an etching resist on the metal layer; Etching the metal layer; Forming a second circuit pattern on the insulating material, Forming a conductive layer on the insulating material and the bumps; Removing the carrier; Forming an etching resist on the conductive layer and the first circuit pattern; Etching the conductive layer, a printed circuit board manufacturing method. delete The method of claim 13, Forming a conductive layer on the insulating material and the bump, And pressing the conductive layer against the insulating material so that the conductive layer is electrically connected to the bump through a pressing process.

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