KR100993481B1 - How to Control Data Access on a Memory Card Host - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access control technique of a memory card host, and more particularly, to a method for coping with errors occurring when a memory card host reads and writes data to a memory card. The present invention relates to an access control technique for increasing the compatibility. According to the present invention, an SD card that supports high-speed data read / write satisfies a performance problem such as a data transfer rate and improves compatibility of a plurality of SD cards manufactured by various manufacturers.

Memory card, SD card, data access

Description

Method for control data access of memory card host}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access control technology of a memory card host. In particular, the present invention relates to improving the compatibility of data access to memory cards manufactured by various manufacturers in response to errors occurring when the memory card host reads or writes data to the memory card. The present invention relates to an access control technique.

High-capacity SD card (Secure Digital Card) is defined in the specification to support up to 32GB in size of storage media and Class2 (2MB / s) or more in data read / write speed. However, the speed of Class2, the data read / write speed in the specification, is the minimum speed and, in fact, must support high speed for good performance.

In SD cards that support normal speeds, CRC errors rarely occur when reading or writing data. However, CRC errors occur on certain SD cards that support high speeds. This is most likely due to lack of setup time or hold time margins between the clock and data as the SD card supports high speed.

Margin shortage can be achieved by adjusting the resistance value, capacitor value, and artwork in hardware circuits, but it is difficult to secure margin for all SD cards. This is because different manufacturers have different internal resistance values or capacitor capacities and different SD card applications.

When CRC error occurs in data read / write when high capacity SD card is operating at high speed, memory card host generates data read / write error when data read / write is performed several times or same error continues for a certain time. . Therefore, the memory card host does not support data read / write for a specific SD card, and thus a user may not use a specific SD card.

SUMMARY OF THE INVENTION An object of the present invention is to provide an access control technique for improving the compatibility of data access to memory cards manufactured by various manufacturers in response to errors occurring while the memory card host performs data read / write on the memory card.

According to another aspect of the present invention, there is provided a data access control method of a memory card host, the method comprising: (a) initiating a data read operation in a state in which an operation state of a memory card is set to a data transfer state; (b) transitioning the operating state of the memory card to the standby state if an error occurs after the data read operation is performed; (c) the memory card host changing and applying the margin value of the digital waveform to the driver stage register of the memory card; And (d) performing a data read operation by shifting the operation state of the memory card to the data transfer state while the margin value of the digital waveform is applied to the driver stage register.

In the data access control method of the memory card host according to the present invention, (e) when an error occurs again in the data read operation, the memory card host changes the SD clock speed in the transfer state after changing the operation state of the memory card to the transfer state. step; And (f) initiating a data read operation with respect to the memory card after the SD clock speed is changed and after the operation state of the memory card is changed to the data transfer state.

Step (b) according to the present invention is characterized in that it comprises a step of the memory card host to issue a command of the CMD7 to the memory card to transition the operating state of the memory card to the standby state.

Step (c) according to the present invention is characterized in that the memory card host comprises the step of using the command of CMD4 to change the margin value of the digital waveform to the driver stage register of the memory card.

The step (e) according to the present invention includes the step of the memory card host giving a command of the CMD12 to the memory card to transition the operation state to the transfer state and changing the SD clock speed using the command of CMD6 in the transfer state. It is characterized by.

The data access control method of the memory card host according to the present invention includes (a) a margin value of a digital waveform at the memory card and the memory card host when an error occurs when the memory card host performs a read operation on the data recorded in the memory card. Determining whether logic to change the number is implemented; (b) if the logic is implemented, the memory card host applies a margin value of the digital waveform differently from the previous value to execute a data read operation; (c) the memory card host changing the SD clock speed when an error occurs in a data read operation; And (d) the memory card host performing a data read operation on the memory card at the changed SD clock speed.

According to the present invention, step (a) comprises: determining whether a driver stage register for changing a margin value of a digital waveform is implemented in a memory card; And determining whether logic for changing the margin value of the digital waveform is implemented in the memory card host.

Step (c) according to the present invention is characterized in that the memory card host comprises the step of changing the SD clock speed using the command of CMD6.

A data access control method of a memory card host according to the present invention includes the steps of: (a) initiating a data write operation when the operating state of the memory card is a data receiving state; (b) if an error occurs during a data write operation, the memory card host transitions the operating state of the memory card to the programming state and then to the transfer state; (c) the memory card host changing a margin value of a digital waveform implemented therein when the operating state of the memory card is in the transfer state; (d) the memory card host transitioning the operation state of the memory card from the transfer state to the data reception state and starting a data write operation; And (e) if a CRC error occurs during the data write operation, the memory card host transitions the operation state of the memory card back to the transfer state, changes the SD clock speed in the transfer state, and then performs a data write operation again. It is configured to include.

Step (b) according to the present invention is characterized in that it comprises the step of the memory card host transitions to the transfer state after the transition of the operating state of the memory card to the programming state by using the command of the CMD12.

Step (d) according to the present invention is characterized in that the memory card host comprises a step of transitioning the operating state of the memory card from the transfer state to the data reception state by using a command of the CMD56.

Step (e) according to the present invention is characterized in that it comprises a step of changing the SD clock speed using the command of CMD6 after the memory card host transitions the operating state of the memory card back to the transfer state.

In the data access control method of the memory card host according to the present invention, (a) the memory card host performs a data write operation after changing a margin value of an internally implemented digital waveform when an error occurs in a data write operation on the memory card. Making; And (b) when the CRC error occurs in the data write operation, the memory card host transitioning the operation state of the memory card to the transfer state, changing the SD clock speed, and executing the data write operation.

Step (b) according to the present invention is characterized in that the memory card host comprises the step of changing the SD clock speed using the command of CMD6 after transitioning the operating state of the memory card to the transfer state.

According to the present invention, an SD card that supports high-speed data read / write satisfies a performance problem such as a data transfer rate and improves compatibility of a plurality of SD cards manufactured by various manufacturers.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is an exemplary view showing the configuration of a memory card host and a memory card for explaining the present invention.

The memory card 100 connected to the memory card host 200 is a high capacity SD card. The memory card host 200 issues a command to the memory card 100 to perform data read / write. When an error occurs when performing data read / write, the memory card host 200 should properly perform data read / write in response to this error. Accordingly, the memory card host 200 correctly performs data read / write operations on the memory card 100 manufactured by various manufacturers, so that the memory card host 200 may not operate properly according to the characteristics of the various memory cards 100. It can increase compatibility.

2 is an exemplary view illustrating a transition of a read state of a memory card when the memory card host according to the present invention issues a data read command to the memory card.

When the memory card host starts reading data to the memory card, the memory card is placed in the data transfer state 10. The memory card host starts a data read operation in the data transfer state 10 of the memory card.

When an error occurs in the data read operation, the memory card host issues a command of CMD7 to the memory card to transition the operating state of the memory card from the data transfer state 10 to the standby state 20.

The memory card host changes the attribute values of the digital waveforms to the driver stage registers (hereinafter referred to as DSR registers) of the memory card by using the command of CMD4. The DSR register consists of 16 bits as shown in Table 1. For example, the initial value of the DSR register is set to 0x404 (20ns, 10ns), and the memory card host performs data read in high speed mode and sets the DSR register value to 0x808 (5ns, 2ns) when a read error occurs. do.

DSR 7 6 5 4 3 2 One 0 tswitch-on max X X X X 5ns 20ns 100ns 500 ns tswitch-on min X X X X 2ns 10ns 50ns 200ns

After the memory card host changes and applies the DSR register value of the memory card in the standby state 20, the memory card host transitions the operation state of the memory card to the transfer state 30 and then transitions back to the data transfer state 10 to resume the data read operation. To start.

When a read error occurs again after executing a data read operation, the memory card host issues a command of the CMD12 to the memory card to transition the operating state of the memory card to the transfer state 30.

The memory card host changes the SD clock speed using the command of CMD6 after the operating state of the memory card is placed in the transfer state 30.

The memory card host accesses the memory card at the changed SD clock speed after the operating state of the memory card is in the data transfer state 10 and starts a data read operation.

3 is a flow chart showing a flow of a coping operation when a memory card host according to the present invention encounters a read error in a memory card.

If a read error occurs when the memory card host starts a data read operation with respect to the memory card, the memory card host determines whether the DSR register is implemented in the memory card (S101). This operation is preceded by the DSR register implemented in the memory card because the specification recommends that each memory card manufacturer implement it.

If the DSR register is implemented in the memory card, in an embodiment, the memory card host changes the attribute value of the digital waveform by changing 0x404 (20ns, 10ns) set as an initial value to the DSR register to 0x808 (5ns, 2ns). S102).

After changing the value in the DSR register, the memory card host performs a data read operation on the memory card (S103). If an error occurs again in the data read operation (S104), the memory card host enters the SD clock speed change mode (S107).

If the memory card does not have a DSR register, the memory card host may have a rise time, a fall time, and a driving current that can internally change the digital waveform properties corresponding to the DSR register. It is determined whether logic for changing the value of) is implemented (S105).

If logic is implemented inside the host, the memory card host changes the attribute value of the digital waveform (S106) and then performs a data read operation (S103). If an error occurs again in the data read operation (S104), the memory card host enters the SD clock speed change mode (S107).

In the SD clock speed change mode, the memory card host checks a time number for changing the SD clock speed (S108). If the time number is valid (S109), the memory card host changes the SD clock speed (S110) and performs a data read operation on the memory card based on the changed SD clock speed (S103).

In the SD clock speed change mode, the memory card host changes the SD clock speed by using a command of CMD6 (S107). Most CRC errors that occur when reading data at high speed are timing margin issues, so changing the SD clock rate will not cause an error in most cases. In addition, a time number that changes the SD clock speed can be programmed to ensure stability.

For example, if an error occurs while performing a data read operation at an SD clock rate of 50 MHz, and the memory card does not implement logic to change the properties of the digital waveforms in the DSR register and the host, program the maximum number of time numbers to 2. If the time number is set to 1 in one state, the SD clock speed is changed from 50 MHz to 25 MHz, and then data read operation is executed. If the data read operation fails, the time number is set to 2 and the SD clock rate is read from 25 MHz to 12.5 MHz.

4 is an exemplary view illustrating a transition of a write state of a memory card when the memory card host according to the present invention issues a write command to the memory card.

The memory card host starts a data write operation to the memory card when the operating state of the memory card is the data reception state 40.

If an error occurs during the data write operation, the memory card host issues a command of CMD12 to transition the operating state of the memory card to the programming state 50 and then to the transfer state 60.

The memory card host sets a value for changing the attributes of the digital waveform in the logic when the operating state of the memory card controls the attributes of the digital waveform therein in the transfer state 60.

The memory card host starts a data write operation after the operation state of the memory card transitions from the transfer state 60 to the data reception state 40 using the command of CMD56.

If a CRC error occurs in the data write operation even after changing the attribute value of the digital waveform, the memory card host transitions the operation state of the memory card back to the transfer state 60 and then uses the CMD6 command to change the SD clock speed. . The memory card host then transitions the operation state of the memory card to the data reception state 40 and resumes the data write operation based on the changed SD clock speed.

The memory card host may program the SD clock speed in a data write operation like a data read operation to change the SD clock speed step by step so that the data write operation may be performed without error.

5 is a flowchart showing a flow of a coping operation when a memory card host generates a write error in the memory card.

When the memory card host performs a data write operation on the memory card, the memory card host determines whether or not logic for changing a property of a digital waveform such as a rise time, a fall time, and a driving current is implemented when a CRC error occurs (S201). If implemented, after setting the attribute value of the digital waveform suitable for high-speed data writing (S202), the data writing operation is performed (S203).

If a CRC error occurs in the data write operation (S204), the memory card host enters the SD clock speed change mode (S205) and changes the SD clock speed using a command of CMD6. At this time, a time number for changing the SD clock speed can be programmed to ensure stability.

For example, if an error occurs while performing a data write operation at an SD clock rate of 50 MHz, and the memory card host does not implement logic that can change the properties of the digital waveform inside, the maximum number of time numbers is programmed to 2. Set the time number to 1 to change the SD clock speed from 50MHz to 25MHz and then perform a data write operation. If a CRC error occurs, the SD clock speed is changed once more. At this time, the SD clock speed operates from 25MHz to 12.5MHz.

In the SD clock speed change mode, the memory card host checks a time number for changing the SD clock speed (S206). If the time number is valid (S207), the memory card host changes the SD clock speed (S208) and performs a data write operation on the memory card based on the changed SD clock speed (S203).

Although the present invention has been described in more detail with reference to the examples, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

1 is an exemplary view showing a configuration of a memory card host and a memory card for explaining the present invention;

2 is an exemplary diagram illustrating a transition of a read state of a memory card when the memory card host issues a data read command to the memory card;

3 is a flow chart illustrating a flow of a coping operation when a memory card host generates a read error in a memory card;

4 is an exemplary diagram illustrating a transition state of a write state of a memory card when the memory card host issues a data write command to the memory card;

5 is a flow chart illustrating a flow of a coping operation when a memory card host generates a write error in a memory card.

Claims (14)

(a) the memory card host starting a data read operation with the operating state of the memory card set to the data transfer state; (b) transitioning an operating state of a memory card to a standby state when an error occurs after the data read operation is performed; (c) the memory card host changing and applying a margin value of a digital waveform to a driver stage register of the memory card; And (d) performing a data read operation by changing the operating state of the memory card to a data transfer state while the margin value of the digital waveform is changed in the driver stage register; Data access control method of the memory card host comprising a. The method according to claim 1, (e) if the error occurs again in the data read operation, changing the SD clock speed in the transfer state after changing the operating state of the memory card to a transfer state; And (f) the memory card host starting a data read operation to the memory card after the SD clock speed is changed and then the operating state of the memory card is transitioned to a data transfer state; And a data access control method of a memory card host. The method according to claim 1, The step (b) includes the step of the memory card host issuing a command of the CMD7 to the memory card to transition the operating state of the memory card to the standby state, characterized in that the data access control of the memory card host Way. The method according to claim 1, The step (c) is characterized in that the memory card host comprises the step of using the command of CMD4 to change the margin value of the digital waveform to the driver stage register of the memory card; How to control data access. The method according to claim 2, The step (e) includes the step of the memory card host issuing a command of the CMD12 to the memory card to transition the operating state to the transfer state and changing the SD clock speed using the command of CMD6 in the transfer state. And a data access control method of the memory card host. (a) when an error occurs when a memory card host performs a read operation on data recorded in the memory card, determining whether the memory card and the memory card host have logic for changing a margin value of a digital waveform; step; (b) if the logic is implemented, the memory card host executing a data read operation by applying a margin value of a digital waveform different from a previous value; (c) changing the SD clock speed by the memory card host when an error occurs in the data read operation; And (d) the memory card host performing a data read operation on the memory card at the changed SD clock speed; Data access control method of the memory card host comprising a. The method according to claim 6, In step (a), Determining whether a driver stage register for changing a margin value of a digital waveform is implemented in the memory card; And Determining whether logic for changing a margin value of a digital waveform is implemented in the memory card host; And a data access control method of a memory card host. The method according to claim 6, The step (c) is characterized in that the memory card host comprises the step of changing the SD clock speed using a command of CMD6. (a) the memory card host starting a data write operation when the operating state of the memory card is in a data receiving state; (b) when the error occurs during the data write operation, the memory card host transitioning the operating state of the memory card to a programming state and then to a transfer state; (c) the memory card host changing a margin value of a digital waveform implemented therein when the operating state of the memory card is in a transfer state; (d) the memory card host transitioning an operation state of the memory card from a transfer state to a data reception state and starting a data write operation; And (e) If a CRC error occurs during the data write operation, the memory card host transitions the operation state of the memory card back to the transfer state, then changes the SD clock speed in the transfer state and then performs the data write operation again. step; Data access control method of the memory card host comprising a. The method according to claim 9, The step (b) is characterized in that the memory card host comprises the step of transitioning the operating state of the memory card to the programming state after the transition to the transfer state by using a command of the CMD12; Access control method. The method according to claim 9, And the step (d) comprises the step of the memory card host transitioning an operation state of the memory card from a transfer state to a data reception state using a command of CMD56. Access control method. The method according to claim 9, The step (e) comprises the step of changing the SD clock speed by the command of the CMD6 after the memory card host transitions the operating state of the memory card back to the transfer state How to control data access on the host. (a) the memory card host performing a data write operation after changing a margin value of an internally implemented digital waveform when an error occurs in a data write operation on the memory card; And (b) when the CRC error occurs in the data write operation, the memory card host transitioning the operation state of the memory card to a transfer state, changing the SD clock speed, and then performing a data write operation; Data access control method of the memory card host comprising a. 14. The method of claim 13, The step (b) is characterized in that the memory card host comprises the step of changing the SD clock speed using the command of CMD6 after the transition of the operating state of the memory card to the transfer state Data access control methods.

Images