KR100966976B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

The present invention provides a semiconductor manufacturing method for improving the profile and the CD uniformity (Critical Dimension Uniformity) of the pattern for the pad. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first mask pattern on an etched layer, forming a second mask pattern on an etched layer, and forming a first mask pattern and a second mask pattern. Forming a spacer on sidewalls, and etching the etched layer based on the etch mask from which the second mask pattern is removed.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a pattern formation method using a SPT (Spacer Patterning Technology) process.

The pattern size is reduced according to the high integration of semiconductor devices. Accordingly, various manufacturing equipment and process methods for forming a fine pattern have been proposed. Referring to the Rayleigh equation as a representative example, a fine pattern in a semiconductor device is shown. The size of is proportional to the wavelength of light used in the exposure process and inversely proportional to the size of the lens. Therefore, a method of reducing the wavelength of light or increasing the size of the lens used in the exposure process has been mainly used for forming a fine pattern.

This method requires the development of new manufacturing equipment, increases equipment investment costs, and causes difficulties in operating the equipment. Therefore, a double patterning technology for printing a circuit pattern by performing an exposure process for photoresist patterning twice using different masks as a method of forming a fine pattern conforming to high integration even using existing equipment. ) And SPT (Spacer Patterning Technology) method using a spacer as an etching mask for generating a fine pattern has been proposed. Hereinafter, look at the manufacturing process according to the SPT in detail.

1A to 1E are cross-sectional views illustrating a SPT (Spacer Patterning Technology) method of a semiconductor device according to the prior art, and particularly, a method of forming a control gate of a flash memory device. In general, a flash memory device includes a cell string to which a plurality of (16 or 32) control gates are connected, and a source selection line (SSL) and a drain selection line (SSL) at both ends of the cell string. A switching transistor is provided to connect to the DSL (Drain Selection Line).

Referring to FIG. 1A, an etched layer 110 is formed on the semiconductor substrate 100, and a sacrificial layer 120 is formed on the etched layer 110.

Here, the etched layer 110 may have a laminated structure of the polysilicon 110a and the nitride film 110b, and the sacrificial film 120a may be formed of a TEOS (Tetra Ethyl Ortho Silicate) oxide film. The thickness at which the sacrificial layer 120a is stacked determines the height of the spacer which plays an important role in the SPT process.

Next, a hard mask layer 160, a bottom antireflection coating (BARC) film 170, and a first photoresist pattern 180 are formed on the sacrificial layer 120a. When the exposure process is performed, it is difficult to generate the fine first photoresist pattern 180 as defined in the mask due to the difference in refractive index between the photoresist and the hard mask layer formed under the photoresist. Therefore, the lower anti-reflection film 170 is used to prevent the photo-resist pattern 180 from being damaged due to the difference in refractive index between the photoresist and the hard mask layer.

In general, an anti-reflection film is a very thin layer of light absorption photosensitive material used to stably form a microcircuit, which is used in a semiconductor optical lithography process, and has a mutual adhesion interface with a high resolution photoresist material used in a conventional process. And optical properties should be well matched. The anti-reflection film adjusts the reflectance of the substrate in the corresponding wavelength band to form a photoresist pattern without standing wave phenomenon or notching, improves CD uniformity characteristics, and improves adhesion between the substrate and the photoresist pattern. Anti-reflective coatings play an important role in the DUV process because they are very helpful. The anti-reflection film is largely divided into a top antireflection coating (TARC) film formed on the top of the photoresist film and a bottom antireflection coating (BARC) film formed on the bottom of the photoresist film. A protective film is mainly used to create a fine circuit pattern.

Referring to FIG. 1A, the lower anti-reflection film 170 and the hard mask layer 160 are etched using the first photoresist pattern 180 as a mask. Thereafter, the sacrificial layer 120a is etched based on the patterned hard mask layer 160 to form the sacrificial layer pattern 120. After the formation of the sacrificial layer pattern 120, the first photoresist layer pattern 180, the anti-reflection layer 170, and the hard mask layer 160 are removed.

As shown in FIG. 1B, a spacer material layer is formed on the entire surface including the sacrificial film pattern 120 and an etch-back process is performed to form the spacer 130 on the side wall of the sacrificial film pattern 120. ). Here, the spacer 130 is preferably formed of polysilicon, and the spacer 130 defines the control gate.

Referring to FIG. 1C, the sacrificial layer pattern 120 is removed by performing a wet process, leaving only the spacers 130.

Referring to FIG. 1D, a second photoresist layer pattern 140 for defining a gate of the switching transistor is formed in a peripheral region deviating from the center region in which the plurality of control gates are formed in the semiconductor substrate 100.

Switching transistors connected to SSL and DSL in the peripheral area are typically present at both ends of the cell string, and thus are more likely to have poorer focus than a plurality of control gates formed in the center area when performing an exposure process. In addition, as the defocus increases in the surrounding area, the manufacturing margin of DOF (depth of focus) is insufficient, while the switching transistor for connecting each selection line (SSL, DSL) is a channel. As it is associated with the turn-on of the s), accurate control of the critical dimension (CD) of the position and size of the pattern in space is required. In addition, since the size (width) of the switching transistor and the selection line is very large compared to each of the plurality of control gates included in the cell string, it is difficult to form the spacer 130 for forming the fine pattern circuit. For this reason, it is necessary to form a separate second photosensitive film pattern 140 in the peripheral region.

Referring to FIG. 1E, the etching target layer 110 is etched using the spacer 130 and the second photoresist pattern 140 as a mask to define a plurality of control gates and gates of switching transistors located at both ends of the SSL, DSL, and cell strings. The etched layer patterns 155a and 155b are formed.

Although not shown, in a subsequent process, a third photoresist pattern (not shown) is formed to expose the outermost portion of the semiconductor substrate on which the etched layer patterns 155a and 155b are formed. Here, the third photoresist pattern (not shown) is a cutting mask for separating the spacer portion of the line end region generated during the deposition of the spacer material layer. A portion of the etched layer patterns 155a and 155b at the end of the line is removed using the third photoresist pattern (not shown) as a mask to separate the respective lines, and then the third photoresist pattern (not shown) is removed.

In forming the pad-type photoresist pattern 140 defining the gate of the switching transistor in the above-described SPT process, a lower anti-reflection film is formed before the photoresist pattern 140 is formed so as not to damage the photoresist pattern 140. However, due to the spacer 130 already formed, the lower anti-reflection film cannot be formed. As shown in FIG. 1D, when the anti-reflection film is not formed in the state where the spacer 130 is formed, there is a problem in that a profile and a pattern defect of the photoresist pattern 140 occur.

If the anti-reflection film is deposited in a state where the spacer 130 is formed, the anti-reflection film may be deposited to a predetermined thickness in the peripheral region without the spacer 130, but the anti-reflection film may be deposited in the minute regions between the spacers 130. There is a problem in that it is not formed and is deposited with a high thickness. In this case, the anti-reflection film may be deposited to improve the profile and CD uniformity of the photoresist pattern 140. However, after the formation of the pad-type photoresist layer 140, the step of removing the anti-reflection layer by using the photoresist layer pattern 140 as a mask during the etching of the etching target layer 110 should be added and the thickness of the photoresist layer pattern 140 should be increased. Therefore, there is a problem that the process margin is not secured.

In addition, when the anti-reflection film is removed, an etching gas based on CF ₄ is used. In the anti-reflection film removal process using the etching gas, the spacer 130 receives an attack and the height thereof is reduced to decrease the height There is a problem that the etching selectivity is insufficient to etch each layer (110).

In the method of manufacturing a semiconductor device according to the related art described above, it is difficult to apply an anti-reflection film when the photosensitive film pattern 140 having a pad shape is formed, and a notching phenomenon occurs due to reflection of light, The photoresist pattern is defective, scum is generated in a narrow region between the patterns, and adhesion to the substrate is lowered, thereby causing a pattern lifting phenomenon.

According to the present invention, a pad pattern is formed by applying an anti-reflection film prior to formation of an etched layer pattern through a cell mask process, thereby improving the profile and CD uniformity of the pad pattern and improving the photoresist pattern. An object of the present invention is to provide a method for manufacturing a semiconductor device that prevents scum and pattern lifting from occurring and improves device characteristics.

The present invention provides a method of forming a first mask pattern on an etched layer, forming a second mask pattern on the etched layer, forming a spacer on sidewalls of the first mask pattern and the second mask pattern, And etching the etched layer based on the etch mask from which the second mask pattern is removed.

Preferably, the first mask pattern and a spacer formed on sidewalls of the first mask pattern among the spacers are formed to form a gate pattern of a switching transistor for connecting a source select line and a drain select line to both ends of a cell string. Characterized in that it is used as an etching mask.

Preferably, the spacers formed on the sidewalls of the second mask pattern among the spacers are used as the etching mask for forming a plurality of control gate patterns in the cell string.

Preferably, the first mask pattern is formed of a polysilicon film, and the second mask pattern is formed of a TEOS film.

Preferably, the spacer is formed of a polysilicon film.

The forming of the first mask pattern may include forming a polysilicon film on the etched layer, forming an antireflection film on the polysilicon film, and patterning a photoresist film formed on the antireflection film. And etching the anti-reflection film and the polysilicon film based on the patterned photoresist.

The forming of the second mask pattern may include forming a TEOS film on the etched layer and the first mask pattern, forming an anti-reflection film on the TEOS film, and forming a photoresist film on the anti-reflection film. Patterning, and etching the anti-reflection film and the TEOS film based on the patterned photoresist.

In addition, the present invention sequentially forming a coarse mask pattern for forming a gate pattern of the switching transistor and a fine mask pattern for forming a control gate pattern in the cell string, and sidewalls of the coarse mask pattern and the fine mask pattern It provides a method of manufacturing a semiconductor device comprising the step of forming a spacer in the STI process.

Preferably, the step of sequentially forming the coarse mask pattern and the fine mask pattern to form a first anti-reflection film on the hard mask layer, the hard mask layer based on the coarse photoresist pattern formed on the first anti-reflection film Patterning the sacrificial layer, forming and planarizing a sacrificial layer covering the patterned hard mask layer, forming a second antireflection layer on the sacrificial layer, and forming the sacrificial layer on the basis of the fine photoresist pattern formed on the second antireflection layer. Patterning.

Preferably, the sparse mask pattern has the same etching selectivity as the spacer, but the etching selectivity is different from the fine mask pattern.

Preferably, the performing of the STI process may include forming spacers on sidewalls of the coarse mask pattern and the fine mask pattern, removing the fine mask pattern, and based on the spacers and the coarse mask pattern. Etching the layer to be etched.

Furthermore, the present invention may further include forming an etched layer on an upper portion of the semiconductor substrate, forming a pad pattern on the etched layer located at an edge portion of the semiconductor substrate, and planarizing a sacrificial layer on the entire top including the pad pattern. Forming a sacrificial layer pattern by etching the sacrificial layer, wherein the pad pattern is not etched, forming spacers on sidewalls of the sacrificial layer pattern and the pad pattern, and removing the sacrificial layer pattern A method of manufacturing a semiconductor device, the method comprising: leaving only a spacer, and forming the etched layer pattern by etching the etched layer using the spacer and the pad pattern provided with the mask as a mask.

Preferably, the etched layer is formed in a laminated structure of a polysilicon layer and a nitride film.

Preferably, the pad pattern defines a gate for SSL (Source Selection Line) and a gate for drain selection line (DSL).

Preferably, the anti-reflection film is included in forming the photoresist pattern for forming the pad pattern.

Preferably, the CD of the pad pattern is smaller than the CD of the target pattern.

Preferably, the sacrificial film is formed of a TEOS film.

Preferably, the anti-reflection film is included in forming the photoresist pattern for forming the sacrificial layer pattern.

Preferably, the sacrificial layer pattern is characterized in that the progress to the wet process using the HF solution.

Preferably, the sacrificial layer pattern is formed in a line / space shape, and the line: space ratio is 1: 3.

In the method of manufacturing a semiconductor device according to the present invention, a pad pattern is formed by applying an anti-reflection film prior to formation of an etched layer pattern through a cell mask process, thereby forming a profile and CD uniformity of the pad pattern. There is an effect that can improve.

In addition, the present invention may improve the characteristics of the semiconductor device by preventing the occurrence of scum and pattern lifting of the photoresist pattern.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. In particular, the present invention provides a cell string connected to a plurality of control gates, and a switching transistor connected to a source selection line (SSL) and a drain selection line (DSL) at both ends of the cell string. The manufacturing method of the semiconductor element provided with the example is demonstrated to an example.

Referring to FIG. 2A, an etched layer 210 is formed on the semiconductor substrate 200, a polysilicon layer 220a and a first anti-reflection film 250a are formed on the etched layer 210, and the first A first photoresist layer pattern 260a defining a pad pattern is formed on the antireflection layer 250a. Here, the etched layer 210 may be formed in a laminated structure of the polysilicon 210a and the nitride film 210b.

Referring to FIG. 2B, the polysilicon layer 220a is etched using the first photoresist layer pattern 260a as a mask to form a pad pattern 220 defining a gate of a switching transistor for connecting with SSL or DSL. . Since the spacer is formed on the sidewall of the pad pattern 220 through a subsequent spacer forming process, the pad pattern 220 is formed to be smaller than the gate size of the switching transistor (by the thickness of the spacer).

At this time, by forming the first anti-reflection film (BARC film, 250a) and performing the exposure process, during the manufacturing process of the semiconductor device according to the present invention, defects or notching phenomena that the first photoresist pattern 260a may have in the past. It can be prevented. That is, since the photoresist pattern forming process was performed after the anti-reflection film was formed on the flat etched layer, the reflectance of the etched layer was reduced to prevent the defect of the pad pattern, and the scum and lifting of the photoresist pattern Can be prevented.

Referring to FIG. 2C, the sacrificial layer 230 formed on the pad pattern 220 and the etched layer 210 is planarized by performing a CMP process.

Here, the sacrificial film 230 is preferably formed of a TEOS film, and since the sacrificial film 230 is a film that determines the height of the spacer that plays an important role in the SPT process, the sacrificial film 230 is preferably formed to have a predetermined height or more. If the height of the sacrificial layer 230 is low, it may be difficult to form the spacer to a desired height and thickness through a subsequent process. For example, a spacer formed on the side of the mask pattern may be deposited at a thickness of about 30 nm at a time. If the mask pattern is not high enough, the spacer is thinner.

In addition, when the sacrificial layer 230 is deposited at a predetermined thickness, a step may occur due to the pad pattern 220, and the step may cause defocus in a subsequent process, thereby causing a cell to be generated later. There is a problem that a plurality of fine control gate patterns in the string are degraded. Therefore, it is preferable to remove the step by performing the chemical mechanical polishing (CMP) process.

Next, a hard mask 240 and a second anti-reflection film 250b are formed on the planarized sacrificial film 230.

Here, the hard mask 240 is formed of polysilicon, and since the etching selectivity is insufficient to etch the sacrificial layer 230 below the photoresist pattern, it is preferable to apply polysilicon to the hard mask 240.

Next, a second photoresist layer pattern 260b defining a word line is formed on the second antireflection layer 250b.

Here, the second photoresist layer pattern 260b may be formed in a line / space shape, and the ratio of line: space is 1: 3.

Referring to FIG. 2D, the second anti-reflection film 250b and the hard mask 240 are etched using the second photoresist pattern 260b as a mask.

Next, the sacrificial layer pattern 230a is formed by etching the lower sacrificial layer 230 using the remaining second photoresist layer pattern 260b, the etched second anti-reflection layer 250b, and the hard mask 240 as a mask. .

At this time, since the TEOS film, which is the sacrificial layer 230, and the polysilicon, which is the pad pattern 220, have an etching selectivity difference, the pad pattern 220 is almost left without being etched.

As shown in FIGS. 2C and 2D, the second anti-reflection film 250b may also be used to form a defective second photosensitive film pattern 260b through an exposure process, which may be caused by a difference in refractive index of the hard mask 240. It can prevent.

Next, the second photoresist layer pattern 260, the etched second anti-reflection layer 250, and the hard mask 240 are removed.

Referring to FIG. 2E, a polysilicon layer, which is a spacer forming material, is deposited on the entire surface including the sacrificial layer pattern 230a and the pad pattern 220.

Next, an spacer 270 is formed on sidewalls of the sacrificial film pattern 230a and the pad pattern 220 by performing an etch-back process until the sacrificial film pattern 230a is exposed.

In this case, spacers 270 are formed on the sidewalls of the pad pattern 220 to increase the CD of the pad pattern 220 and form a gate pattern larger than the size of the pad pattern.

2F, the sacrificial layer pattern 230a is removed to leave only the spacers 270 for forming the plurality of control gate patterns in the cell string.

Here, the removal process of the sacrificial layer pattern 230a is preferably a wet method using HF, and the nitride layer 210b, which is a lower material, is resistant to the HF solution and is not removed. In addition, the pad pattern 220 having different etching selectivity and the same etching selectivity as the spacer 270 is not removed.

Referring to FIG. 2G, the etched layer 210 below is etched using the spacer pattern 270 and the pad pattern 220 having the spacer 270 formed on the sidewalls as a mask. At this time, the nitride film 210b and the polysilicon 210a are sequentially etched.

In this case, the pad pattern 220 used as a mask is polysilicon, and since the same lower material is etched, the uniformity of etching may be improved than when other materials are used as a mask.

Next, the pad pattern 220 in which the spacer 270 is formed on the sidewalls of the spacer 270 is removed to define a gate of the switching transistor for connecting the plurality of control gate patterns and the source select line or the drain select line. Each layer pattern 215a and 215b is formed.

Although not shown, a subsequent process will be described. A third photoresist pattern (not shown) exposing the outermost portion of the semiconductor substrate 200 on which the etched layer patterns 215a and 215b are formed is formed. Here, the third photoresist layer pattern (not shown) is a cutting mask for separating the spacer portion of the line end region generated when the spacer material layer is deposited.

Next, a portion of the etched layer pattern 215 at the end of the line is removed using the third photoresist pattern (not shown) as a mask to separate each line, and then the third photoresist pattern (not shown) is removed.

As described above, in contrast to forming a photoresist pattern for generating a sparse gate pattern after forming a spacer, which is an etch mask for generating a fine gate pattern, in the present invention, polysilicon, which is an etch mask for generating a sparse gate pattern, is formed. A film is first formed and then a spacer for forming a fine gate pattern is formed. As a result, a gate pattern in a semiconductor device having two different sizes can be formed using only two exposure processes, thereby increasing the complexity of the process, and forming a lower anti-reflection film (BARC), and then performing each exposure process. The accuracy has been increased to form photoresist patterns of different sizes used in the device.

In this way, the method of manufacturing a semiconductor device according to the present invention forms a pad pattern by applying an anti-reflection film before forming an etched layer pattern through a cell mask process, thereby forming a profile and a CD uniformity of the pad pattern ( Critical Dimension Uniformity is improved and the characteristics of the device can be improved by preventing the occurrence of scum and pattern lifting of the photoresist pattern.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (20)

Forming a first mask pattern on the etched layer; Forming a second mask pattern on the etched layer; Forming spacers on sidewalls of the first mask pattern and the second mask pattern; And Removing the second mask pattern and etching the etched layer based on an etch mask composed of the first mask pattern and the spacer. Method for manufacturing a semiconductor device comprising a. The method of claim 1, Spacers formed on sidewalls of the first mask pattern and the spacers of the first mask pattern and the spacer may be used as the etching mask to form a gate pattern of a switching transistor for connecting a source select line and a drain select line to both ends of a cell string. Method for manufacturing a semiconductor device, characterized in that. The method of claim 2, The spacer formed on the sidewall of the second mask pattern of the spacer is used as the etching mask for forming a plurality of control gate patterns in the cell string. The method of claim 1, And the first mask pattern is formed of a polysilicon film, and the second mask pattern is formed of a TEOS film. The method of claim 1, The spacer is a method of manufacturing a semiconductor device, characterized in that formed of a polysilicon film. The method of claim 1, Forming the first mask pattern is Forming a polysilicon film on the etched layer; Forming an anti-reflection film on the polysilicon film; Patterning a photoresist film formed on the anti-reflection film; And And etching the anti-reflection film and the polysilicon film based on the patterned photoresist. The method of claim 1, Forming the second mask pattern is Forming a TEOS film on the etched layer and the first mask pattern; Forming an anti-reflection film on the TEOS film; Patterning a photoresist film formed on the anti-reflection film; And Etching the anti-reflection film and the TEOS film based on the patterned photoresist. Sequentially forming a coarse mask pattern for forming a gate pattern of the switching transistor and a fine mask pattern for forming a control gate pattern in the cell string; And Forming an spacer on sidewalls of the coarse mask pattern and the fine mask pattern, and then performing an STI process; The sparse mask pattern has the same etching selectivity as the spacer, but the etching selectivity is different from the fine mask pattern. The method of claim 8, Forming the sparse mask pattern and the fine mask pattern sequentially Forming a first anti-reflection film on the hard mask layer; Patterning the hard mask layer based on the coarse photoresist pattern formed on the first anti-reflection film; Forming and planarizing a sacrificial layer covering the patterned hard mask layer; Forming a second anti-reflection film on the sacrificial film; And And patterning the sacrificial film on the basis of the fine photoresist pattern formed on the second anti-reflection film. delete The method of claim 8, Performing the STI process is Forming spacers on sidewalls of the sparse mask pattern and the fine mask pattern; Removing the fine mask pattern; And And etching the etched layer based on the spacers and the sparse mask pattern. Forming an etched layer on the semiconductor substrate; Forming a pad pattern on the etched layer on the edge portion of the semiconductor substrate; Forming a planarized sacrificial layer over the entire surface including the pad pattern; Etching the sacrificial layer to form a sacrificial layer pattern, wherein the pad pattern is not etched; Forming a spacer on sidewalls of the sacrificial layer pattern and the pad pattern; Removing the sacrificial layer pattern to leave only the spacers; And Forming an etched layer pattern by etching the etched layer using the spacer and a pad pattern provided with the spacer as a mask Method of manufacturing a semiconductor device comprising a. 13. The method of claim 12, The etching layer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of a polysilicon layer and a nitride film. 13. The method of claim 12, The pad pattern defines a gate for a source selection line (SSL) and a gate for a drain selection line (DSL). 13. The method of claim 12, The method of manufacturing a semiconductor device, characterized in that it comprises an anti-reflection film when forming a photosensitive film pattern for forming the pad pattern. 13. The method of claim 12, The CD of the pad pattern is formed smaller than the CD of the target pattern. 13. The method of claim 12, And the sacrificial film is formed of a TEOS film. 13. The method of claim 12, The method of manufacturing a semiconductor device, characterized in that it comprises an anti-reflection film when forming a photosensitive film pattern for forming the sacrificial film pattern. The method of claim 13, The sacrificial layer pattern is a manufacturing method of a semiconductor device, characterized in that to proceed in a wet process using a HF solution. The method of claim 13, The sacrificial layer pattern may be formed in a line / space shape, and the line: space ratio is 1: 3.

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