KR100955175B1 - Vertical semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a vertical semiconductor device and a method of manufacturing the same.

Method of manufacturing a vertical semiconductor device of the present invention comprises the steps of forming a silicon pillar on a silicon substrate; Forming a gate electrode material on the silicon pillar surface; And removing a gate electrode material on the upper surface of the silicon pillar to form a surrounding gate electrode. As described above, the present invention forms a spacer on the surface of the pillar without isotropic etching of the pillar when forming the surrounding gate electrode. By using the process of thinning the pillars even if the thinning can minimize the collapse of the pillars. This enables the fabrication of more highly integrated vertical semiconductor devices.

Description

Vertical semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical semiconductor device, and more particularly, to a manufacturing method of a vertical semiconductor device having an improved method of forming a surrounding gate electrode, and a semiconductor device formed using the method.

As the degree of integration of semiconductor devices increases, the channel length of the transistors gradually decreases. However, the reduction in the channel length of such transistors has a problem of causing short channel effects such as a drain induced barrier lowering (DIBL) phenomenon, a hot carrier effect, and a punch through.

In order to solve this problem, various methods have been proposed, such as a method of reducing the depth of the junction region or a method of increasing the channel length by forming a recess in the channel region of the transistor.

However, as the integration density of semiconductor memory devices, especially DRAMs, is approaching gigabit, smaller transistor sizes are required. That is, a transistor of a gigabit DRAM device requires an element area of 8F2 (F: minimum feature size) or less, and further requires an element area of about 4F2. Therefore, the current planar transistor structure in which the junction regions are formed on both sides of the gate electrode in which the gate electrode is formed on the semiconductor substrate, does not satisfy the required device area even when the channel length is scaled.

In order to solve this problem, a vertical channel transistor structure has been proposed.

FIG. 1 is a view illustrating a pillar before a surrounding gate electrode is formed in a conventional vertical semiconductor device, and FIG. 2 is a view illustrating a surround gate formed on a lower outer circumferential surface of the pillar.

Referring to FIG. 1, the silicon substrate 106 is etched by a predetermined depth using the hard mask pattern 101 as an etch mask to form a pillar upper portion 103 as an active region of the silicon substrate 106. Next, after forming the spacer nitride film on the entire surface of the resultant product, the spacer nitride film 102 is etched back to form the spacer 102 on the sidewalls of the hard mask pattern 101 and the pillar 103.

Next, the silicon substrate 106 is etched to a predetermined depth by using the hard mask pattern 101 and the spacer 102 as an etching mask to form a pillar lower portion integrally connected to the pillar upper portion 103. Next, the pillar bottom 104 is isotropically etched to form a channel portion 104 having a thin thickness. At this time. The etching degree of the bottom of the pillar is such that the thickness of the subsequent surrounding gate electrode.

Next, referring to FIG. 2, an oxide film (gate oxide film) 108 is formed on the surface of the channel part 104, and then a gate electrode material such as polysilicon is deposited on the resultant. Subsequently, by using the oxide film 108 as an etch mask, the gate electrode material is etched back to form a surrounding gate electrode 109 surrounding the channel portion 104 and having a shape perpendicular to the substrate surface. .

However, as shown in FIG. 1, when a locally thick silicon pillar (small in cross-sectional area) exists in the pillar, particularly when the thin silicon pillar is present in the lower portion of the pillar, the pillar may have a structurally unstable shape. In other words, when the lower pillar is made of thin pillars, the larger the upper pillar is, the more likely the pillar is to collapse or break. In such a case, impurities are formed on the wafer during the subsequent process, thereby causing a decrease in yield.

In addition, as the degree of integration increases, the cross-sectional area of the pillar must be further reduced. As the cross-sectional area of the pillar decreases, the isotropic etching of the pillar increases the possibility that the pillar breaks.

Therefore, forming a rounding gate by isotropically etching the pillars has a limit to high integration of a vertical transistor having excellent characteristics.

An object of the present invention is to provide a vertical semiconductor device having better characteristics by improving a method of forming a surrounding gate electrode in a vertical semiconductor device.

The vertical semiconductor device manufacturing method of the present invention

Forming silicon pillars on the silicon substrate;

Forming a gate electrode on a surface of the silicon pillars; And

Removing the gate electrodes on the upper surfaces of the silicon pillars to form a surrounding gate electrode.

The method of manufacturing a vertical semiconductor device of the present invention further includes forming a storage node connected to the upper portions of the silicon pillars.

In the method of manufacturing a vertical semiconductor device of the present invention, the gate electrode is formed of any one selected from Ti, TiN, TaN, W, Al, Cu, WSix, and a combination thereof.

In the method of manufacturing a vertical semiconductor device of the present invention, the gate electrode is removed by an isotropic etching method.

The silicon pillar forming step in the vertical semiconductor device manufacturing method of the present invention

Forming a pad oxide film on the silicon substrate; Forming a hard mask pattern on the pad oxide layer; And etching the pad oxide layer and the silicon substrate using the hard mask pattern as an etching mask.

The gate electrode forming step in the vertical semiconductor device manufacturing method of the present invention

Forming a gate oxide film on surfaces of the silicon pillars;

Depositing the gate electrode material on the gate oxide film; And

And removing the gate electrode material deposited between the silicon pillars to separate the electrodes between the silicon pillars.

In the method of manufacturing a vertical semiconductor device of the present invention, the gate electrode material is any one selected from Ti, TiN, TaN, W, Al, Cu, WSix, and combinations thereof.

In the method of manufacturing a vertical semiconductor device of the present invention, the gate electrode material deposition step is characterized in that the deposition of polycrystalline silicon on the gate oxide film using a chemical vapor deposition method.

In the method of manufacturing a vertical semiconductor device of the present invention, the gate electrode material deposition step may include doping phosphorus (Ph) or boron (B) on the polycrystalline silicon when the polycrystalline silicon is deposited.

In the method of manufacturing a vertical semiconductor device of the present invention, the surrounding gate electrode forming step is

Forming a buried bitline by ion implanting impurities into a silicon substrate between the electrode pillars;

Forming a nitride film on the electrode separated gate electrode;

Etching the buried bit line in the first direction using the nitride film as an etching mask to form a device isolation trench;

Filling the trench and forming a first insulating film to a height less than a top surface of the silicon pillar; And

And removing the nitride film and the gate electrode exposed by the first insulating film.

In the method of manufacturing a vertical semiconductor device of the present invention, the impurity ion implantation is characterized by implanting phosphorus (Ph) and arsenic (As).

In the method of manufacturing a vertical semiconductor device of the present invention, the nitride film is formed by low pressure chemical vapor deposition (LP CVD) or atomic layer deposition (Si CVD) using SiH ₂ Cl ₂ and NH ₃ as source gases.

In the vertical semiconductor device manufacturing method of the present invention, the nitride film has a thickness in the range of 50 kPa to 200 kPa.

In the method of manufacturing a vertical semiconductor device of the present invention, the nitride film and the gate electrode material may be removed using an isotropic etching method.

The vertical semiconductor device manufacturing method of the present invention

Removing the first insulating film;

Filling the trench and forming a second insulating layer to a height below the surrounding gate electrode;

Removing the nitride film exposed by the second insulating film; And

And forming a word line on the second insulating layer to connect the surrounding gate electrodes in a second direction.

The vertical semiconductor device of the present invention is characterized in that it is a semiconductor device formed using the above-described manufacturing method.

The present invention minimizes the phenomenon that the pillar collapses even when the pillar is formed thinly by forming a gate electrode on the surface of the pillar using a process of forming spacers without isotropic etching of the pillar when forming the surrounding gate electrode in manufacturing a vertical semiconductor device. This enables the fabrication of more highly integrated vertical semiconductor devices.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 to 18 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device according to the present invention.

First, referring to FIG. 3, a pad oxide film 202 and a hard mask pattern 203 are formed on a silicon substrate 201. In this case, the hard mask pattern 203 includes a silicon substrate 201 and a material having an etching selectivity, for example, a nitride film.

Next, the pad oxide film 202 and the silicon substrate 201 are etched by a predetermined depth using the hard mask pattern 203 to form a pillar (silicon pillar) 204. This pillar 204 is later used as a source / drain and channel region and the top is connected to the cell's storage node (capacitor).

In this case, the hard mask pattern 203 may be formed using TEOS (Si (OC ₂ H ₅ ) ₄ : Tetra Ethoxy Ortho Silicate) or plasma CVD (Chemical Vapor Deposition) method using SiH ₄ as a source gas, or SiO ₂ or SiH _2. It is preferable to deposit a silicon nitride film containing Cl ₂ and NH ₃ as source gas by a low pressure chemical vapor deposition method. Alternatively, a general low pressure chemical vapor deposition method using TEOS as a raw material gas may be used. At this time, the thickness of the deposited SiO ₂ layer is preferably in the range of 500 kPa to 5000 kPa. In addition, it is preferable that the hard mask pattern 203 uses a material whose etching rate is less than half the etching rate of the silicon substrate 201.

Referring to FIG. 4, the gate oxide layer 205 and the gate electrode 206 are sequentially formed on the resultant product of FIG. 3.

In this case, since there are various crystal planes exposed on the silicon surface when forming the gate oxide layer 205, it is preferable to use an oxidation method in which the silicon oxidation rate is independent of the silicon crystal plane.

The gate electrode 206 is formed to have a thickness close to the thickness of the gate electrode to be left in the subsequent process, that is, the surrounding gate electrode to be formed. That is, in the present invention, since the portion of the gate electrode 206 deposited so as to surround the surface of the pillar 204 as a whole is used as the surrounding gate electrode, as shown in FIG. 4, the thickness of the gate electrode 206 is desired. It is formed to approximate the thickness of the surrounding gate electrode.

In this case, the gate electrode 206 may be formed of polycrystalline silicon using a vapor phase chemical vapor deposition method. In this case, phosphorous (Ph), boron (B), or the like may be doped into the polycrystalline silicon simultaneously with the deposition. In addition, since the threshold voltage of the surrounding gate type channel is very low, Ti, TiN, TaN, W, Al, Cu, WSix, or a metal material or a P-type polysilicon thereof may be used as the gate electrode 206. have.

Next, referring to FIG. 5, the gate electrode 206 is dry etched to remove the upper and lower gate electrodes, thereby separating the gate electrodes between the vertical transistors. Next, in order to recover the characteristics of the gate oxide film 205, it is preferable to perform a heat treatment or a sidewall oxidation process.

Next, ion implantation is performed in the silicon substrate 201 between the pillars 204 using N type impurities to form an electrode (BBL) 207 to be used as a bit line. At this time, Ph and As are mainly implanted with ions.

Next, referring to FIG. 6, a thin silicon nitride film 208 is deposited on the resultant of FIG. 5, an insulating film 209 is deposited on the entire surface thereof, and the insulating film 209 is etched to be flattened. In this case, the silicon nitride film 208 is a material gas of SiH ₂ Cl ₂ and NH ₃ by using a low pressure chemical vapor deposition (LP CVD) or atomic layer deposition (ALD: Atomic Layer Deposition) to be able to easily control the thickness. desirable. The thickness of the silicon nitride film 208 is preferably in the range of 50 GPa to 200 GPa.

In addition, a BPSG (Boro-phospho Silicate Glass) film is preferably used as the insulating film 209.

Next, referring to FIG. 7, a trench T for device isolation is formed by sequentially etching the insulating film 209 and the silicon substrate 201 using the nitride film 208 as an etching mask. FIG. 8 is a plan view of FIG. 7, in which an electrode 207 implanted with impurities is electrically connected in a first direction by electrically connecting a plurality of pillars 204 separated by a trench T and arranged in a matrix. BBL).

Next, referring to FIG. 9, the trench T etched in FIG. 8 is again applied to the insulating layer 210. At this time, before applying the trench T to the insulating film 210, it is preferable to proceed with a process of forming a thermal oxide film (not shown) by heat-treating the exposed silicon surface. This thermal oxidation is to oxidize the silicon in that contains a gas such as _{O 2, H 2 O, H} 2, O 3 in the range of 200 ℃ ~ 1000 ℃ atmosphere.

Subsequently, referring to FIG. 10, the insulation films 209 and 210 are etched by performing dry etching on the resultant of FIG. 9. At this time, the insulating film 210 buried in the trench T is etched only to a predetermined depth (depth to form a surrounding gate in a subsequent process).

Next, referring to FIG. 11, the nitride film 208 and the gate electrode 206 of the portion not embedded by the insulating film 210 in the resultant of FIG. 10 are sequentially removed. As a result, the upper portion of the pillar 204 (a portion downward from the uppermost surface of the pillar) is not surrounded by the gate electrode 206. That is, an offset portion is formed on the pillar 204 so that the storage node LPC and the surrounding gate electrode 206 to be formed on the top surface of the pillar 204 do not overlap by a subsequent process. As a method of etching the nitride film 208 and the gate electrode 206, an isotropic etching method such as wet etching is preferably performed.

Next, referring to FIG. 12, the silicon nitride film is again exposed to the gate oxide film 205 exposed in the resultant product of FIG. 11, that is, the sidewall of the hard mask pattern 203 and the sidewall not surrounded by the gate electrode 206 in the pillar 204. (211) is deposited. In this case, the thickness of the silicon nitride film 211 may be thicker than the previously deposited silicon nitride film 208.

Then, the insulating film 210 buried in the device isolation region is removed.

Next, referring to FIG. 13, after the insulating film 212 is entirely deposited on the resultant of FIG. 12, planarization is performed.

Next, referring to FIGS. 14 and 15, damascene for connecting the surrounding gate electrodes 206 in a second direction intersecting with the patterning of the bit line 207 extending in the first direction as in FIG. 15. After insulating the pattern 213 where the word line DWL is to be formed, the insulating layer 212 is etched as shown in FIG. 14.

Next, referring to FIG. 16, the nitride films 208 and 211 exposed by the insulating film 212, that is, the nitride films 208 and 211 deposited on the pillar sidewalls are removed from the resultant of FIG. 14. Next, after depositing a word line electrode material 214 for forming a damascene word line on the resultant, a planarization process such as chemical mechanical polishing (CMP) is performed until the oxide film 205 is exposed. In this case, an insulating layer may not be formed at an interface between the surrounding gate electrode 206 and the word line electrode material 214.

Next, referring to FIG. 17, a dry etching process is performed on the word line electrode material 214 to be removed to a predetermined depth. In this case, as shown in FIG. 17, the word line electrode material 214 is etched by the height of the surrounding gate electrode 206 so that the electrode material does not remain on the pillar 204.

Next, referring to FIG. 18, after forming the insulating film 215 on the resultant of FIG. 17, the insulating film 215 and the hard mask pattern 203 are removed and planarized. Next, an etch stopper (silicon nitride film) 216 and an insulating film 217 are formed on the resultant, and then the etching stopper 216 and the insulating film 217 are selectively removed to expose the surface of the pillar 204. To form. Then, the plug material (eg, silicon implanted with impurities) is embedded in the opening to form a contact plug 218 electrically connected to the pillar 204.

A storage node (not shown) is then formed on the contact plug 218.

As such, the present invention does not form a surrounding gate by isotropically etching the pillar as in the related art, and forms a surrounding gate by depositing a gate electrode material on the surface of the pillar using a spacer forming process and then partially removing the pillar. Even if the thinner is formed, the fall of the pillar can be minimized.

In the above-described embodiment, a method of forming a pillar, which is a silicon pillar, by etching the silicon substrate 201 using the hard mask pattern 203 is not limited thereto.

For example, by depositing gold (Au) on a silicon substrate using a catalyst and performing a VLS (Vapor-Liquid-Solid) process in a silane gas atmosphere to grow silicon pillars to a desired height on the silicon substrate. Elevated Source-Drain methods can also be used.

1 is a view illustrating a pillar before a surrounding gate electrode is formed in a conventional vertical semiconductor device.

2 is a view showing a surrounding gate is formed on the outer peripheral surface of the pillar in FIG.

3 to 18 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device in accordance with the present invention.

Claims (15)

Forming silicon pillars on the silicon substrate; Forming a gate electrode having electrodes separated from each other on the surfaces of the silicon pillars; Forming a buried bitline in the silicon substrate between the silicon pillars; Forming a first insulating film between the silicon pillars on the buried bit line to a height less than a top surface of the silicon pillar; And And removing a gate electrode on an upper surface of the silicon pillars exposed by the first insulating layer to form a surrounding gate electrode. The method of claim 1, And forming a storage node connected to the upper portions of the silicon pillars. The method of claim 1, Wherein the gate electrode is formed of any one selected from Ti, TiN, TaN, W, Al, Cu, WSix, and a combination thereof. The method of claim 1, And the gate electrode is removed by an isotropic etching method. The method of claim 1, wherein the forming of the silicon pillar Forming a pad oxide film on the silicon substrate; Forming a hard mask pattern on the pad oxide layer; And And etching the pad oxide layer and the silicon substrate by using the hard mask pattern as an etch mask. The method of claim 1, wherein the forming of the gate electrode is performed. Forming a gate oxide film on surfaces of the silicon pillars; Depositing the gate electrode material on the gate oxide film; And And removing the gate electrode material deposited between the silicon pillars to separate the electrodes between the silicon pillars. The method of claim 6, wherein the depositing of the gate electrode material is performed. And depositing polycrystalline silicon on the gate oxide film by using a chemical vapor deposition method. 8. The method of claim 7, wherein depositing the gate electrode material A method of manufacturing a vertical semiconductor device, characterized in that when the polycrystalline silicon is deposited, the polycrystalline silicon is doped with phosphorus (Ph) or boron (B). The method of claim 6, wherein the buried bit line forming step Forming a bit line region by ion implanting impurities into the silicon substrate between the electrode pillars; Forming a nitride film on the electrode separated gate electrode; And And etching the bit line region in the first direction using the nitride film as an etch mask to form a trench for device isolation. The method of claim 9, The impurity ion implantation method of manufacturing a vertical semiconductor device, characterized in that the implantation of phosphorus (Ph) and arsenic (As). The method of claim 9, The nitride film is a vertical semiconductor device manufacturing method characterized in that formed by low pressure chemical vapor deposition (LP CVD) or atomic layer deposition (LP CVD) using a source gas of SiH ₂ Cl ₂ and NH ₃ . The method of claim 9, The nitride film has a thickness in the range of 50 GPa to 200 GPa. The method of claim 9, The nitride film and the gate electrode material is removed is a vertical semiconductor device manufacturing method, characterized in that using an isotropic etching method. The method of claim 9, Removing the first insulating film; Filling the trench and forming a second insulating layer to a height below the surrounding gate electrode; Removing the nitride film exposed by the second insulating film; And And forming a word line on the second insulating layer to connect the surrounding gate electrodes in a second direction. A semiconductor device formed using the manufacturing method of claim 1.

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