KR100935584B1 - Semiconductor memory device with subbank with shared fuseset - Google Patents

Abstract

Disclosed are a semiconductor memory device capable of improving a bank's layout margin. The disclosed semiconductor memory device includes at least two subbanks stacked, and a shared block composed of a free decoder and a fuse set disposed between the stacked subbanks.

Subbank, Stack, Pre Decoder, Main Decoder, Fuseset

Description

Semiconductor Memory Device Having Sub-BanKs Shared Fuse-sets}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a multi-bank type semiconductor memory device including a plurality of subbanks.

In general, a semiconductor memory device is composed of a plurality of memory cells and a circuit for controlling them. Currently, semiconductor memory devices have introduced a bank concept to classify and control hundreds of thousands of memory cells into groups. The bank is an area in which memory cells are collected, and the plurality of memory cells are divided into banks to control signal transfer characteristics of the semiconductor memory device.

Recently, as the memory cells increase exponentially, a multi-bank method for classifying and controlling banks into sub-banks has been proposed.

1 is a plan view illustrating a bank having a general plurality of subbanks.

Referring to FIG. 1, the bank 12 is divided into an up / down bank around an imaginary half line HL, and each of the up bank and the down bank is 4, for example. It is divided into three subbanks (15). Each of the sub-banks 15 may be composed of a plurality of mats including a plurality of word lines and a plurality of bit lines intersected and a plurality of memory cells defined by the plurality of word lines. It extends in the y direction and x direction of a figure, respectively.

At this time, in each up / down bank, a plurality of global input / output lines (GIOs) for transferring data carried on the bit lines are disposed in a space between the sub banks 15 perpendicular to the bit lines. do. In addition, a main decoder 21, a pre-decoder 22, and a fuse set 23 are sequentially disposed at edges of the subbank 15 adjacent to the global input / output line GIO. The main decoder 21 and the free decoder 22 are used to decode the Yi signal for selecting the bit line, and the fuse set 23 is provided to replace the failure of the memory cell. Here, reference numeral 25 denotes an X hole that governs word line driving of the subbank.

However, as the degree of integration of the semiconductor memory device increases, the number of memory cells integrated in the bank increases, so that the block 12 for controlling the bank 12 and the bank 12 composed of the subbank 15, the subbank 15 ( (Not shown) is increasing in density.

As described above, since the size of the subbank 15 constituting the bank 12, that is, the bank 12, is increased in the limited semiconductor chip, the arrangement margin of the bank 12 is very insufficient. The distance between (15) is also becoming difficult to secure.

The spacing between the sub-banks 15 is an arrangement and formation space of the global input / output lines GIO, and the decrease in the spacing between the sub-banks 15 causes a decrease in the line width and spacing of the global input / output lines GIO. As such, the reduction in the spacing of the global input / output lines may cause crosstalk of the signal, and the reduction in the line width of the global input / output lines may cause the signal delay.

Accordingly, the technical problem of the present invention is to provide a semiconductor memory device capable of improving the allocation margin of a bank.

In addition, another technical problem of the present invention is to provide a semiconductor memory device capable of securing a formation space of a global input / output line through which data is inputted and outputted by improving a bank's layout margin.

The semiconductor memory device of the present invention for achieving the above-described technical problem of the present invention includes a shared block consisting of at least two sub-banks stacked, and a free decoder and a fuse set disposed between the stacked sub-banks.

In addition, a semiconductor memory device according to another exemplary embodiment of the present invention may include a plurality of banks divided around a peripheral area, a plurality of stack bank structures disposed at a predetermined interval within the banks, and disposed between the stack bank structures. It includes a plurality of global input and output lines. The stack bank structure may include at least two stacked subbanks, a shared block including a free decoder and a fuse set interposed between the subbanks, and a main decoder interposed between the subbank and the shared block.

According to the embodiments, subbanks located on the same bit line extension line in the half bank are stacked while sharing the pre decoder and the fuse set. As a result, it is possible to ensure as much as the area defined by the predecoder and the fuse set in the half bank and also in the bank.

In addition, since the predecoder and the fuse set of the present embodiment are alternately arranged in correspondence with the mat row constituting the sub-bank in the shared block space, it is possible to easily transfer control signals (repair Yi signals) to each other, so that The length can be reduced.

In addition, by stacking the subbanks, global input / output lines that have been disposed between the existing subbanks may be collected between the stack bank structures. Accordingly, it is not necessary to secure the spacing between subbanks. In addition, since the global input / output lines arranged in correspondence with the subbanks are arranged in correspondence with the stack bank structure, the number of global input / output lines may be reduced.

As a result, the layout space of the global input / output lines can be secured, and the number of global input / output lines can be reduced, thereby ensuring sufficient line width and spacing of the global input / output lines. Therefore, the signal transmission characteristic of the semiconductor memory device is greatly improved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 2, the semiconductor chip 100 may be divided into four banks 110, for example, in the case of a 512M DRAM. In this embodiment, it is assumed that the word line WL extends in the y direction of the drawing, and the bit line BL extends in the x direction of the drawing. The peripheral region 120 may include a first peripheral region 120a that isolates the banks 110 in the x direction of the drawing, and a second peripheral region 120b that isolates the banks 110 in the y direction of the drawing. Can be. In addition, the first peripheral area 120a may be divided into a center area CPERI and an edge area DPERIL. The center area CPERI is disposed at the center of the semiconductor chip 100, and commands for driving the DRAM are mainly input. The edge area DPERIL is disposed between the bank 110 and the bank 110 and mainly data pads (not shown) are disposed.

Each bank 110 may be divided into half banks, that is, up / down banks 110u and 110d around the virtual half line HL. Here, the half line HL may extend in parallel with the word line extension direction. The up / down banks 110u and 110d may be configured with four subbanks 130, respectively. Accordingly, one bank 110 may be composed of eight subbanks 130. The sub-bank 130 may include a plurality of mat 132 arrays including a plurality of word lines and a plurality of bit lines that are cross-arranged, and a plurality of memory cells defined by the sub-banks 130.

At this time, the sub-banks 130 arranged in the same row (r1, r2, or the same column) in one half bank (110u, 110d) are the main decoder 210, pre-decoder 220 and fuse set 230 Stacked with. In the present embodiment, stacked means that the sub-banks 130 are continuously arranged. In addition, the same row (or same column) may mean that they are on the same bit line extension line.

More specifically, as shown in FIG. 3, the subbanks 130 arranged in the same row (or the same column) in the same half banks 110u and 110d may each have their respective facings. The main decoder 210 is disposed. In addition, a shared block 240 is interposed between the main decoders 210. The shared block 240 is a block shared by both sub-banks 130 and includes a pre decoder 220 and a fuse set 230. As is known, the predecoder 220 is a circuit for pre-decoding a Yi signal for selecting the bit line BL, and the fuse set 230 is a Yi signal transfer line of the memory cells constituting the sub-bank 130. May include a repair Yi signal transmission line to replace the defective.

In this case, the predecoder 220 and the fuse set 230 are alternately arranged in the shared block 240 with respect to the vertical direction (for example, the word line extension direction) as shown in FIG. 4. Preferably, the predecoder 220 and the fuse set 230 are alternately arranged corresponding to each of the mat rows Mr1, Mr2, Mr3, ... as shown in FIG. Such a structure is advantageous for simultaneously controlling the subbanks 130 on both sides of the shared block 240. In addition, as the predecoder 220 and the fuse set 230 are alternately arranged in the shared block 240, the fuse set 230 of the present embodiment is provided with bad Yi signal information, which is transmitted to the pre decoder 220. And generate a repair Yi signal and provide the repair Yi signal back to the fuse set 230. Therefore, it is possible to reduce the length of the line for conveying the bad Yi signal information.

In addition, the conventional fuse set is configured to correspond to the entire mat row. However, since the fuse set 230 of the present embodiment is selectively arranged only in odd or even mat rows, the number may correspond to one-half the number of conventional fuse sets 230. However, in general, since the sub-bank 130 does not generate a bad Yi signal for its entire mat 132, reducing the number of fuse sets 230 to one half does not cause a problem in the repair operation. I do not. In the present embodiment, the stacked subbank 130, the main decoder 210 and the shared block 240 positioned therebetween will be collectively referred to as a stack bank structure 135.

Meanwhile, a plurality of global input / output lines GIO are disposed in a space parallel to the word line WL among the spaces between the stack bank structures 135. In this case, a predetermined number of global input / output lines GIO are allocated per stack bank structure 135, and the allocated global input / output lines GIO are involved in data input / output of the sub-banks 130 constituting the stack bank structure 135. . Therefore, since the global input / output lines GIO allocated per subbank 130 are allocated for each stack bank structure 135, the total number of global input / output lines GIO may be reduced. In addition, since it is not necessary to provide a space for arranging the global input / output lines GIO between the subbanks 130, the size of the subbank 130 and the arrangement area of the global input / output lines GIO are as much as the area secured thereby. It can contribute to the increase.

In the present embodiment, the two subbanks 130 are stacked to each other and share the predecoder 220 and the fuse set 230 therebetween. By such a configuration, the global input / output line GIO disposed between the subbanks 130 is moved and disposed between the stack bank structures 135.

Accordingly, as much as the area designated as the predecoder 220 and the fuse set 230 on the sub-bank is secured, the layout margin of the sub-bank 130 is improved. In addition, in the present embodiment, since the global input / output lines GIO are allocated for each stack bank structure 135 rather than for each subbank, there is no need to secure a gap between the subbanks 130 and the number of global input / output lines GIO is required. Can be reduced.

Therefore, since the area of the arrangement area of the global input / output line GIO is secured and the line width of the global input / output line GIO can be secured sufficiently, problems such as signal delay can be solved. In addition, the gap between the global input and output lines (GIO) is also sufficiently secured, thereby solving the crosstalk problem.

In addition, as shown in FIG. 5, a Y-control block 140 for controlling the Yi signal may be further disposed at one edge of the stack bank structure 135. Since the Y-control block 140 is composed of circuits for controlling Yi signals related to driving the bit line BL, the Y-control block 140 may be disposed at an edge of the stack bank structure 135 perpendicular to the bit line BL. Preferably, the Y-control block 140 is disposed on the surface of the stack bank structures 135 with the global input / output line GIO interposed therebetween.

In addition, an X hole composed of circuit parts for generating control signals for controlling word line driving in each quarter 135 in a portion perpendicular to the word line (y direction) of the space between the stack bank structures 135 ( X-hole 150 may be disposed.

According to the embodiments, subbanks located on the same bit line extension line in the half bank are stacked while sharing the pre decoder and the fuse set. As a result, it is possible to ensure as much as the area defined by the predecoder and the fuse set in the half bank and also in the bank.

In addition, since the predecoder and the fuse set of the present embodiment are alternately arranged in correspondence with the mat row constituting the sub-bank in the shared block space, it is possible to easily transfer control signals (repair Yi signals) to each other, so that The length can be reduced.

In addition, by stacking the subbanks, global input / output lines that have been disposed between the existing subbanks may be collected between the stack bank structures. Accordingly, it is not necessary to secure the spacing between subbanks. In addition, since the global input / output lines arranged in correspondence with the subbanks are arranged in correspondence with the stack bank structure, the number of global input / output lines may be reduced.

As a result, the layout space of the global input / output lines can be secured, and the number of global input / output lines can be reduced, thereby ensuring sufficient line width and spacing of the global input / output lines. Therefore, the signal transmission characteristic of the semiconductor memory device is greatly improved.

In the present embodiment, for example, the case in which the up / down banks are divided into four subbanks has been described as an example. However, the present invention is not limited thereto. Can be applied.

In addition, although the DRAM device has been described as an example in the present embodiment, the present invention may be applied to a graphic memory device, a flash memory device, and an SRAM device.

1 is a plan view illustrating a bank having a general plurality of subbanks.

2 is a plan view of a multi-bank type semiconductor memory device according to an embodiment of the present invention;

3 is a plan view showing a stack bank structure according to an embodiment of the present invention;

4 is an enlarged view of a portion “A” of FIG. 3; and

5 is a plan view of a multi-bank type semiconductor memory device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: bank 120: peripheral area

130: subbank 135: stack bank structure

210: main decoder 210: pre decoder

220: fuse set 240: shared block

Claims (14)

A stack bank structure in which two sub banks are stacked in a row; And And a shared block comprising a predecoder and a fuse set continuously arranged without gaps between the subbanks of the stack bank structure. The method of claim 1, And the sub-bank has a mat array composed of a plurality of mat rows and a plurality of mat columns. The method of claim 2, And the predecoder and fuse set are alternately disposed in the shared block to correspond to the mat row. The method according to claim 1 or 3, The predecoder predecodes the column related signals of the subbank. The method according to claim 1 or 3, And the fuse set includes a signal line for replacing a column-related signal line in which a failure occurs when the column-related signal line in the subbank is defective. The method of claim 3, wherein And the fuse set receives information on a bad column related signal line and provides the fuse signal as a control signal of the predecoder. The method of claim 1, And a main decoder configured to decode column-related signals of the subbank between each of the subbank and the shared block. A plurality of banks divided around the peripheral area; A plurality of stack bank structures constituting each bank; And A plurality of global input and output lines disposed between the stack bank structure, The stack bank structure, At least two subbanks stacked in series; A shared block composed of a free decoder and a fuse set interposed between the subbanks; And And a main decoder interposed between the subbank and the shared block. The method of claim 8, And the sub-bank has a mat array composed of a plurality of mat rows and a plurality of mat columns. The method of claim 9, And the predecoder and fuse set are alternately disposed in the shared block to correspond to the mat row. The method of claim 10, The predecoder predecodes the column related signals of the subbank, And the fuse set includes a signal line for replacing a column-related signal line in which a failure occurs when the column-related signal line of the sub-bank is defective. The method of claim 11, And the fuse set receives information on a bad column related signal line and provides the fuse signal as a control signal of the predecoder. The method of claim 8, And a control block disposed between the stack bank structure and the global input / output line to control all column related signals of the subbanks constituting the stack bank structure. The method of claim 8, The global input / output line is provided in predetermined number per the stack bank structure, The predetermined global input / output line manages data input and output of subbanks constituting the stack bank structure.

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