KR100895383B1 - Main driver of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main driver of a semiconductor device, and discloses a technique for reducing parasitic capacitance of a main driver. The present invention provides a pull-up-code control means for adjusting the impedance of pull-up data according to a plurality of pull-up codes, and a pull-up-data control for transferring the output of the pull-up code control means to an output terminal according to the input state of the pull-up data. Means, a pull-down-code control means for adjusting the impedance of the pull-down data according to a plurality of pull-down codes, and a pull-down-data control means for delivering the output of the pull-down-code control means to the output terminal in accordance with the input state of the pull-down-data. Including, wherein the pull-up data control means has a first drive element for receiving the pull-up data, the pull-down data control means has a second drive element for receiving the pull-down data.

Description

Main driver of semiconductor device

1 is a configuration diagram relating to a driver of a conventional semiconductor device.

FIG. 2 is a detailed circuit diagram of the main driver of FIG. 1. FIG.

3 is a detailed circuit diagram of a main driver of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main driver of a semiconductor device, and is a technique for reducing parasitic capacitance of a main driver.

BACKGROUND In general, semiconductor devices including integrated circuits, such as central processing units (CPUs), memories, and gate arrays, are used in various electrical products such as personal computers, servers, or workstations. Typically, an input circuit for receiving a signal through an input pad from the outside and an output circuit for outputting an internal signal to the outside through an output pad are provided. Here, the input / output pad is connected to a transmission line on a printed circuit board (PCB) substrate on which a semiconductor device is disposed.

On the other hand, as the operating speed of electrical products is increased, the swing width of signals interfaced between semiconductor devices is gradually decreasing. The reason is to minimize delays in signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases. In addition, the reflection of the signal due to impedance mismatching (hereinafter referred to as mismatching) at the interface stage is also serious.

The impedance mismatch described above occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, and the like. When impedance mismatch occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted.

Therefore, when the receiving semiconductor device receives a distorted output signal at the input terminal, problems such as setup / hold fail or input level determination miss may frequently occur.

As a result, the semiconductor device on the receiving side, which requires an increase in operating speed, has an impedance matching circuit called on-chip termination or on-die termination near a pad in the integrated circuit chip. Will be hired.

Typically, in the on-die termination apparatus, source termination by an output circuit is performed on the transmission side, and parallel termination is performed by a termination circuit connected in parallel to a receiving circuit connected to an input pad on the receiving side.

In particular, several new concepts have been added to control the data transfer speed of a double data rate (DDR) memory device more quickly. Of these, termination resistors are needed to facilitate signal transmission between the devices.

1 is a configuration diagram of a driver of a conventional semiconductor device.

The conventional driver includes a pre-driver 10 and a main driver 20. Here, the pre-driver 10 includes a pre-pull driver 11 and a pre-pull driver 12. The main driver 20 includes a pull-up driver 21 and a pull-down driver 22.

The pre-pull driver 11 receives the pull-up data UP_DATA latched by the output data latch unit (not shown) to pre-drive and output the pull-up data UP. The pre-pull driver 12 receives the pull-down data DN_DATA latched by the output data latch unit (not shown) to pre-drive and output the pull-down data DN.

In addition, the pull-up driver 21 drives the pull-up data UP applied from the pre-pull-up driver 11 to output the data DQ to the pad PAD. The pull-down driver 22 drives the pull-down data DN applied from the pre-pull driver 12 to output the data DQ to the pad PAD.

FIG. 2 is a detailed circuit diagram of the pull-up driver 21 and the pull-down driver 22 in the main driver 20 of FIG. 1.

The pull-up driving unit 21 includes a plurality of PMOS transistors P1 to P5, which are pull-up control units, a PMOS transistor P6, which is a pull-up bias unit, and a plurality of PMOS transistors P7 to P11, which are pull-up control units, and pull-up resistors R1 and R2. Include.

In addition, the pull-down driving unit 22 includes a plurality of NMOS transistors N1 to N5 as pull-down code control means, NMOS transistors N6 as pull-down bias units, and a plurality of NMOS transistors N7 to N11 as pull-down data control means and pull-down resistor R3, R4.

Here, the PMOS transistors P1 to P5 are connected between the power supply voltage VDD applying stage and the PMOS transistors P7 to P11, and pull-up codes Pcode <4> to Pcode <0> are applied through respective gate terminals.

The PMOS transistor P6 is connected between the power supply voltage VDD terminal and the pull-up resistor R1 to apply the pull-up data UP through the gate terminal. In addition, the PMOS transistors P7 through P11 are connected between the PMOS transistors P1 through P5 and the pull-up resistor R2 to apply the pull-up data UP through the common gate terminal.

In addition, the pull-up resistor R1 is connected between the PMOS transistor P6 and the output terminal of the data DQ. The pull-up resistor R2 is connected between the PMOS transistor P7 and the output terminal of the data DQ. Here, the data is not limited to "DQ", but the data "DQ", the data strobe signal "DQS", and the inverted signal "DQSB" of the DQS may be output together.

The NMOS transistors N1 to N5 are connected between the ground voltage VSS applying terminal and the NMOS transistors N7 to N11, and pull-down codes Ncode <4> to Ncode <0> are applied through the respective gate terminals.

In addition, the NMOS transistor N6 is connected between the ground voltage VSS applying terminal and the pull-down resistor R3, and the pull-down data DN is applied through the gate terminal. In addition, the NMOS transistors N7 to N11 are connected between the NMOS transistors N1 to N5 and the pull-down resistor R4 so that the pull-down data DN is applied through the common gate terminal.

In addition, pull-down resistor R3 is connected between NMOS transistor N6 and the output terminal of data DQ. And a pull-down resistor R4 is connected between the NMOS transistor N7 and the output terminal of the data DQ.

In general, pull-up resistors R1, R2 and pull-down resistors R3, R4 are used for the purpose of improving the linearity of the main driver 20. At this time, as the resistance values of the pull-up resistors R1 and R2 and the pull-down resistors R3 and R4 are larger, the main driver 20 exhibits better linear characteristics.

Here, as the resistance values of the pull-up resistors R1 and R2 and the pull-down resistors R3 and R4 increase, the sizes of the transistors included in the pull-up driver 21 and the pull-down driver 22 must also increase.

However, the conventional main driver 20 receives the pull-up data UP through the plurality of PMOS transistors P6 to P11 and the pull-down data DN through the plurality of NMOS transistors N6 to N11.

Accordingly, the conventional main driver 20 is divided into several transistors to which data is input. That is, the PMOS transistors P7 to P11 to which data is input are divided into a plurality of PMOS transistors P1 to P5 to which pull-up codes Pcode <4> to Pcode <0> are input. The NMOS transistors N7 to N11 to which data is input are divided into a plurality of NMOS transistors N1 to N5 to which pull-down codes Ncode <4> to Ncode <0> are input.

Therefore, not only does the layout area of the driver increase, but also the parasitic capacitance generated by the plurality of data input transistors increases, which is a major cause of impairing the high speed operation characteristics of the entire circuit.

If the resistance of the pull-up driver 21 and the pull-down driver 22 is reduced to reduce the size of the transistor, the parasitic capacitance is decreased, but the linearity of the main driver 20 is decreased. As a result, it is very difficult to simultaneously ensure the operation of speeding up the circuit while maintaining the linearity of the main driver 20.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to improve a transistor into which a data is input from a main driver to a 1-transistor structure, thereby reducing layout area and reducing parasitic capacitance.

The main driver of the semiconductor device of the present invention for achieving the above object, the pull-up code control means for adjusting the impedance of the pull-up data in accordance with a plurality of pull-up code; Pull-up-data control means for transferring the output of the pull-up-code control means to an output terminal according to the input state of the pull-up-data; Pull-down code control means for adjusting the impedance of pull-down data according to the plurality of pull-down codes; And pull-down-data control means for transmitting the output of the pull-down code control means to an output terminal according to the input state of the pull-down data, wherein the pull-up-data control means includes a first driving element to receive the pull-up data; The pull-down control means includes a second drive element for receiving the pull-down data.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a detailed circuit diagram of a main driver of a semiconductor device according to the present invention.

The main driver of the present invention includes a pull-up driver 100 and a pull-down driver 110.

The pull-up driving unit 100 includes a plurality of PMOS transistors P12 to P16 that are pull-up control units, a PMOS transistor P17 that is a pull-up bias unit, and a PMOS transistor P18 that is a pull-up control unit and pull-up resistors R5 and R6.

In addition, the pull-down driver 110 includes a plurality of NMOS transistors N12 to N16 that are pull-down code control means, an NMOS transistor N17 that is a pull-down bias portion, and an NMOS transistor N18 that is a pull-down data control means, and pull-down resistors R7 and R8. .

Here, the PMOS transistors P12 to P16 are connected between the power supply voltage VDD applying stage and the PMOS transistor P18 to receive pull-up codes Pcode <4> to Pcode <0> through respective gate terminals.

The PMOS transistor P17 is connected between the supply voltage VDD terminal and the pull-up resistor R5 to apply the pull-up data UP through the gate terminal. Here, the PMOS transistor P17 corresponds to a bias transistor. When the pull-up data UP is applied, the PMOS transistor P17 is always turned on to supply the bias voltage.

In addition, the PMOS transistor P18 is connected between the PMOS transistors P12 to P16 and the pull-up resistor R6 to apply the pull-up data UP through the gate terminal.

In addition, a pull-up resistor R5 is connected between the PMOS transistor P17 and the output terminal of the data DQ. The pull-up resistor R6 is connected between the PMOS transistor P18 and the output terminal of the data DQ. Here, the data is not limited to "DQ", but the data "DQ", the data strobe signal "DQS", and the inverted signal "DQSB" of the DQS may be output together.

The NMOS transistors N12 to N16 are connected between the ground voltage VSS applying terminal and the NMOS transistor N18 so that pull-down codes Ncode <4> to Ncode <0> are applied through the respective gate terminals.

In addition, the NMOS transistor N17 is connected between the ground voltage VSS applying terminal and the pulldown-resistance R7, and the pulldown-data DN is applied through the gate terminal. Here, the NMOS transistor N17 corresponds to a bias transistor. When the pull-down data DN is applied, the NMOS transistor N17 is always turned on to supply the bias voltage.

In addition, the NMOS transistor N18 is connected between the NMOS transistors N12 to N16 and the pull-down resistor R8 so that a pulldown-data DN is applied through the gate terminal.

In addition, pull-down resistor R7 is connected between NMOS transistor N17 and the output terminal of data DQ. And a pull-down resistor R8 is connected between the NMOS transistor N18 and the output terminal of the data DQ.

The main drivers 100 and 110 having such a configuration receive a pull-up data UP through one PMOS transistor P18 and a pulldown-data DN through one NMOS transistor N18.

For example, pins that output data DQ, data strobe signal DQS, and inverted signal DQSB of DQS in DDR3 may output a signal but simultaneously perform a function for receiving an externally input signal.

Therefore, the transmitting and receiving end connected to the pin from which the data DQ, the data strobe signal DQS, and the inverted signal DQSB of the DQS are outputted serves as an output amplifier stage when the signal is output.

However, in DDR3, when the data DQ, the data strobe signal DQS, and the inverted signal DQSB of the DQS are input through the transmit / receive pin, the transmit / receive end is terminated to a specific impedance value to increase the speed of the circuit. Therefore, it is important to minimize the parasitic capacitance of the transmission and reception stages in order to speed up the entire circuit.

To this end, in the present invention, the pull-up data control means to which the pull-up data UP is input includes one PMOS transistor P18. Then, the pulldown-data control means into which the pulldown-data DN is input includes one NMOS transistor N18.

Here, when the PMOS transistor P18, which is a data input transistor, is turned on, the impedance value of the data DQ is adjusted in correspondence to the number of turned on PMOS transistors P12 to P16. At this time, even when the PMOS transistors P12 to P16 are turned on, when the PMOS transistor P18 is turned off, the impedance value of the pull-up data UP is not transmitted to the data DQ.

In addition, when the NMOS transistor N18, which is a data input transistor, is turned on, the impedance value of the data DQ is adjusted according to the number of turned on NMOS transistors N12 to N16. At this time, even when the NMOS transistors N12 to N16 are turned on, when the NMOS transistor N18 is turned off, the impedance value of the pull-down data DN is not transferred to the data DQ.

Accordingly, when laying out the main driver of the present invention for the integration of the actual circuit, it is possible to eliminate the metal lines for connecting a plurality of transistors. As a result, not only can the layout size be reduced, but the parasitic transistor components due to the connection of complex metal lines can be eliminated.

This invention relates to an output amplification stage and on-die termination capable of reducing parasitic capacitance components. Accordingly, the present invention can be applied to any system requiring an output amplification stage having a central processing unit (CPU), a memory, a memory controller, or an on-die termination function. Examples include the data DQ of the DDR3, the data strobe signal DQS, and the transmitting end of the DQSB output pin.

As described above, the present invention improves the operation characteristics of the entire circuit by reducing the layout area and reducing the parasitic capacitance by improving the transistor into which data is input from the main driver into a 1-transistor structure. to provide.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

Pull-up control means for adjusting the impedance of pull-up data according to the plurality of pull-up codes; Pull-up-data control means for transferring an output of the pull-up-code control means to an output terminal according to the input state of the pull-up-data; Pull-down code control means for adjusting the impedance of pull-down data according to the plurality of pull-down codes; And A pull-down-data control means for transmitting an output of the pull-down code control means to the output terminal according to the input state of the pull-down data; The pull-up data control means includes a first drive element for receiving the pull-up data, and the pull-down data control means includes a second drive element for receiving the pull-down data. Main driver. The semiconductor device of claim 1, wherein the first driving device is a pull-up device. The main driver of claim 1, wherein the second driving element is a pull-down element. The method of claim 1, A pull-up bias unit configured to supply a bias voltage to the output terminal according to the pull-up data; And And a pull-down bias unit for supplying a bias voltage to the output terminal according to the pull-down data. The method of claim 4, wherein A first pull-up resistor connected between the pull-up bias unit and the output terminal; A second pull-up resistor connected between the first driving device and the output terminal; A first pull-down resistor connected between the pull-down bias unit and the output terminal; And And a second pull-down resistor connected between the second driving element and the output terminal. Code control means for adjusting an impedance of data in accordance with a plurality of codes; And And data control means for transmitting an output of the code control means to an output terminal according to the input state of the data, And the data control means receives the data through one driving element. 7. The main driver of claim 6, wherein the driving element is a pull-up element. The main driver of claim 6, wherein the driving element is a pull-down element. The main driver of claim 6, further comprising a bias unit configured to supply a bias voltage to the output terminal according to the data. The method of claim 9, A first resistor connected between the bias unit and the output terminal; And And a second resistor connected between the driving element and the output terminal.

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