KR100870500B1 - LCD and its driving method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof for improving display quality by preventing direct current afterimage and flicker.

The liquid crystal display device comprises: a liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with gate pulses and having a plurality of liquid crystal cells; A data driving circuit inverting the polarity of the data voltage in response to a polarity control signal and outputting the data voltage to the data lines in response to a source output enable signal; A gate driving circuit supplying the gate pulses to the gate lines; And inverting the polarity control signal in units of one frame period for a frame period other than a multiple times frame period of N (N is an integer greater than or equal to 8) and performing the polarity control signal during the multiple times frame period of N and the previous frame period. And a POL / SOE logic circuit for controlling the phase equally and controlling the pulse width of the source output enable signal to be longer than other frame periods during the multiple times of the N frame periods.

Description

Liquid Crystal Display and Driving Method

1 is an equivalent circuit diagram showing a liquid crystal cell of a liquid crystal display device.

2 is a waveform diagram showing an example of interlaced data;

3 is an experimental result screen showing a DC afterimage due to interlaced data.

4 is an experimental result screen showing a DC afterimage due to scroll data.

5 is a view for explaining a method of driving a liquid crystal display device according to a first embodiment of the present invention;

FIG. 6 is a waveform diagram showing first and second source output enable signals according to a first embodiment of the present invention; FIG.

7 is a view for explaining the principle that the DC residual image does not appear in the scroll data.

8 is a waveform diagram showing an experimental result of increasing light in an Nth frame period;

FIG. 9 is a waveform diagram illustrating an experimental result in which light is decreased in an Nth frame period by a second source enable signal; FIG.

10 is a view for explaining the principle that the DC residual image does not appear in the interlace data.

11 is a block diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 12 is a block diagram showing in detail the data driving circuit shown in FIG.

FIG. 13 is a circuit diagram showing details of the digital-to-analog converter shown in FIG. 12; FIG.

FIG. 14 is a block diagram showing details of the POL / SOE logic circuit shown in FIG. 11; FIG.

15 is a block diagram illustrating details of a logic unit illustrated in FIG. 14.

FIG. 16 is a waveform diagram illustrating a POL inversion signal and first and second polarity control signals shown in FIG. 15. FIG.

17 is a flowchart for explaining a method of driving a liquid crystal display according to a second embodiment of the present invention.

18 is a block diagram illustrating a liquid crystal display device according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: liquid crystal display panel 101: timing controller

102, 162: POL / SOE logic circuit 103: data driving circuit

104: gate driving circuit 105: system

106: line memory 111: shift register

112: data register 113, 114: latch

115: digital to analog converter 116: charge-sharing circuit

117: output circuit 121: P-decoder

122: N-decoder 123, 132, 133, 146: multiplexer

131: logic unit 141: frame counter

142: POL inversion unit 143: exclusive logical sum gate

144: SOE timing analysis unit 145: SOE adjustment unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to improve display quality by preventing direct current afterimage and flicker.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven in an inversion method in which polarities are inverted between neighboring liquid crystal cells and polarities are inverted in units of frame periods. However, if any one of the two polarities of the data voltage is supplied dominant for a long time, an afterimage occurs. This afterimage is referred to as "DC image sticking" because the liquid crystal cell is repeatedly charged with the same polarity. One example of such an example is when interlace data voltages are supplied to a liquid crystal display. The interlace method includes only the odd line data voltages to be displayed on the liquid crystal cells of the odd horizontal lines in the odd frame period, and includes only the data voltages to be displayed on the liquid crystal cells of the even horizontal lines in the even frame period.

2 is a waveform diagram illustrating an example of an interlaced data voltage supplied to a liquid crystal cell Clc. The liquid crystal cell Clc supplied with the data voltage as shown in FIG. 2 is any one of the liquid crystal cells arranged in the odd horizontal line.

Referring to FIG. 2, the liquid crystal cell Clc is supplied with a positive voltage during the odd frame period and a negative voltage during the even frame period. In the interlace method, since the high positive data voltage is supplied only to the liquid crystal cell Clc arranged on the odd horizontal line during the odd frame period, the positive data voltage is negatively divided like the waveform in the box during the four frame periods. It is predominant compared to that of the direct current afterimage. Figure 3 is an image showing the experimental results of the DC afterimage resulting from the interlace data. When the original image as shown in the left image of FIG. 3 is supplied to the liquid crystal display panel in an interlaced manner for a predetermined time, the amplitude of the data voltage whose polarity changes in units of frame periods varies in the odd frame and the even frame, and as a result, When a data voltage of an intermediate gray level, for example, 127 gray levels, is supplied to all the liquid crystal cells Clc of the liquid crystal display panel after the image, a direct current afterimage having a faint pattern of the original image appears as shown in the right image.

As another example of a DC residual image, when the same image is moved or scrolled at a constant speed, the voltage of the same polarity is repeatedly generated in the liquid crystal cell Clc according to the correlation between the size of the scrolled picture and the scroll speed (moving speed). Accumulation may cause a DC afterimage. This example is shown in FIG. 4. Figure 4 is an image showing the experimental results of the DC afterimage appearing when moving the diagonal pattern and the character pattern at a constant speed.

In a liquid crystal display device, not only the display quality of a moving image is deteriorated by the afterimage of DC, but also the display quality is deteriorated by a flicker phenomenon in which the luminance difference is periodically observed by the naked eye. Therefore, in order to improve the display quality of the liquid crystal display device, it is necessary to solve the DC afterimage and to prevent the flicker phenomenon.

Disclosure of Invention An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which are designed to solve the problems of the prior art and to improve display quality by preventing direct current afterimage and flicker.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a gate pulse and having a plurality of liquid crystal cells; A data driving circuit inverting the polarity of the data voltage in response to a polarity control signal and outputting the data voltage to the data lines in response to a source output enable signal; A gate driving circuit supplying the gate pulses to the gate lines; And inverting the polarity control signal in units of one frame period for a frame period other than a multiple times frame period of N (N is an integer greater than or equal to 8) and performing the polarity control signal during the multiple times frame period of N and the previous frame period. And a POL / SOE logic circuit for controlling the phase equally and controlling the pulse width of the source output enable signal to be longer than other frame periods during the multiple times of the N frame periods.
The pulses of the source output enable and the gate pulses overlap during the multiple times N frame periods.
The liquid crystal cell charges the data voltage for a frame period other than the multiple times frame period of N; The data voltage is charged after charging one of the common voltage and the charge share voltage during the multiple times frame period of N.
The common voltage is an equipotential voltage substantially equal to the voltage supplied to the common electrode of the liquid crystal cell, and the charge share voltage is an average voltage of the positive data voltage and the negative data voltage supplied to neighboring data lines.
When the pulse width of the source output enable signal generated during another frame period other than the multiple of N frame period is '1', the pulse of the source output enable signal generated during the multiple of N frame period is '1'. The width is about 1.36-1.71.
The liquid crystal display frames a reference polarity control signal inverted every one frame period for every frame period, a reference source output enable signal having a constant pulse width for all the frame periods, and a gate start pulse for instructing the start of the gate pulse. And a timing controller that occurs once at the beginning of the period.
The POL / SOE logic circuit has the same phase during the multiple times of the frame N and the previous frame period using the gate start pulse, the reference polarity control signal, the reference source output enable signal, and a clock signal. A logic unit for generating a polarity control signal and the source output enable signal having a wider pulse width during a multiple times frame period of N; A first multiplexer for selecting any one of the reference polarity control signal and the polarity control signal; And a second multiplexer for selecting any one of the reference source output enable signal and the source output enable signal.
The logic unit includes a frame counter for counting the gate start pulse to generate frame count information; A polarity inversion unit for generating a polarity inversion signal inverted at the beginning of the multiple times frame period of N using the output of the counter; An XOR gate generating an exclusive logic sum operation of the reference polarity control signal and the polarity inversion signal to generate the polarity control signal; A timing analyzer configured to detect a rising edge, a pulse width, and a falling edge of the reference source output enable signal using the clock signal to generate a timing analysis signal; A pulse width adjusting unit configured to generate a source output enable signal having a pulse width wider than that of the reference source output enable signal using the timing analysis signal; And selecting an output of the pulse width adjusting unit during the Nth th frame period in response to an output of the frame counter, and selecting the reference source output enable signal for another frame period other than the N th th frame period. And a third multiplexer for outputting a source output enable signal.
According to another exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a gate pulse, and having a plurality of liquid crystal cells; An image analysis circuit for detecting any one of interlace data and scroll data in the input image; A data driving circuit inverting the polarity of the data voltage in response to a polarity control signal and outputting the data voltage to the data lines in response to a source output enable signal; A gate driving circuit supplying the gate pulses to the gate lines; And when the one of the interlace data and the scroll data detected by the image analysis circuit is input, the polarity control signal for one frame period other than a multiple frame period of N (N is an integer of 8 or more). Inverting the unit and controlling the phase of the polarity control signal equally during the multiple times N frame period and the previous frame period, and changing the pulse width of the source output enable signal during the multiple times N frame period. A POL / SOE logic circuit for controlling longer than the frame period is provided.
In the driving method of the liquid crystal display according to the embodiment of the present invention, the polarity control signal is inverted in units of one frame period for another frame period other than N (N is an integer of 8 or more). Controlling the phase of the polarity control signal equally during the period and the previous frame period; Controlling a pulse width of a source output enable signal to be longer than another frame period during the multiple times frame period of N; Inverting the polarity of the data voltage in response to the polarity control signal and outputting the data voltage to the data lines in response to the source output enable signal; And supplying the gate pulse to the gate lines.
According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: detecting any one of interlace data and scroll data in an input image; When any one of the interlace data and the scroll data is input, the polarity control signal is inverted in units of one frame period for another frame period other than N (N is an integer of 8 or more). Controlling the phase of the polarity control signal equally during the period and the previous frame period; Controlling a pulse width of a source output enable signal to be longer than another frame period during the multiple times frame period of N; Inverting the polarity of the data voltage in response to the polarity control signal and outputting the data voltage to the data lines in response to the source output enable signal; And supplying the gate pulse to the gate lines.
Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 18.

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5 and 6, the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention inverts the polarity of the data voltage charged in the liquid crystal cell Clc in units of frame periods, but in units of N frame periods. The liquid crystal cell Clc is charged with a data voltage having the same polarity as that of the previous frame period.

'N' is preferably a multiple of 8 or more. As a result of experiment to confirm the DC residual image in both interlace data and scroll data by adjusting 'N', the DC image persistence in both interlace data and scroll data is shown when N is a frame period that appears periodically with 8 or more frame periods in between. Because it does not appear.

In addition, in the method of driving the liquid crystal display according to the first embodiment of the present invention, the first source output enable signal SOE is applied to the first pulse width W1 in the first to Nth frame periods. The second source output enable signal FGDSOE is generated at a second pulse width W2 wider than the first pulse width in the Nth frame period. The first and second source output enable signals SOE and FGDSOE are timing control signals indicating the output of the data driving circuit. Subsequently, in the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention, the first source output enable signal SOE is generated at the first pulse width W1 in the N + 1 to 2N-1 frame periods. The second source output enable signal FGDSOE is generated at the second pulse width W2 in the second N frame period.

During the high logic periods of the first and second source output enable signals SOE and FGDSOE, the data driving circuit includes a common voltage Vcom, which is an intermediate voltage between the positive data voltage and the negative data voltage, or the charge share voltage. generate a share voltage. The charge share voltage is connected to the positive data voltage by a short circuit between the data line to which the positive data voltage is supplied and the data line to which the negative data voltage is supplied adjacent to the data line in the high logic section of the source output enable signal SOE. This voltage is generated as an average value of the negative data voltages. During the low logic period of the first and second source output enable signals SOE and FGESOE, the data driving circuit generates a positive data voltage (+ Vdata) or a negative data voltage (-Vdata).

During the first to Nth frame periods and the N + 1 to 2N-1 frame periods, the high logic section of the first source output enable signal SOE and the gate pulse GP do not overlap or are in a very small time period. Overlaps. For this reason, the liquid crystal cell Clc has the positive data voltage during the first to Nth frame periods and the N + 1 to 2N-1 frame periods during the period in which the TFT is turned on by the gate pulse GP. After charging the + Vdata) or the negative data voltage (-Vdata), the TFT is turned off, and then the data voltages (+ Vdata, -Vdata) are held by the storage capacitor Cst.

The high logic period of the second source output enable signal FGDSOE and the gate pulse GP overlap each other for a relatively long time during the Nth and 2NN frame periods. Therefore, the liquid crystal cell Clc charges the common voltage Vcom or the charge share voltage during the period in which the TFT is turned on by the gate pulse GP during the Nth and the second Nth frame periods, and then the data voltage (+ Vdata, -Vdata). Subsequently, after the TFT is turned off, the liquid crystal cell Clc maintains the data voltages + Vdata and -Vdata by the storage capacitor Cst.

Assuming that data voltages (+ Vdata, -Vdata) of the same gray level are supplied to the liquid crystal cell Clc in all frame periods, the liquid crystal cell Clc causes the second source output enable signal for the Nth and the second Nth frame periods. The liquid crystal cell is charged during the Nth and 2N frame periods because the data voltages (+ Vdata and -Vdata) charged with the common voltage Vcom or the charge share voltage are charged by the overlap of the FGDSOE and the gate pulse GP. The amount is smaller than the charging amount of the first to Nth frame periods and the N + 1 to 2N-1th frame periods.

When the first pulse width W1 of the first source output enable signal SOE is 1, the second pulse width W2 of the second source output enable signal FGDSOE is approximately 1.36 to 1.71. This is because, as a result of the experiment, the DC pulse width is the optimal value in which no DC residual and flicker appear in both the interlace data and the scroll data. In this experiment, the first pulse width W1 of the first source output enable signal SOE is set to 2.24 μs, and the data voltage is controlled at the same polarity as the previous frame in units of N frames to drive the liquid crystal display panel while driving the second source. The second pulse width W2 of the output enable signal FGDSOE is adjusted to check the DC residual image and flicker in both the interlace data and the scroll data. In this experiment, the second pulse width (W2) of the second source output enable signal (FGDSOE) in which no DC residual and flicker appear in both the interlace data and the scroll data was found to be approximately 3.04 μs to 3.84 μs. If the second pulse width W2 of the second source output enable signal FGDSOE is narrower than 3.04 μs, the amount of charge reduction of the liquid crystal cell Clc is small in the Nth frame period and the 2N frame period. When the flicker was felt and the second pulse width W2 of the second source output enable signal FGDSOE is larger than 3.84 μs, the amount of charge of the liquid crystal cell Clc is reduced in the Nth frame period and the 2N frame period. Because of the large size, I could feel the screen brightness and flicker with the naked eye.

As a result, the driving method of the liquid crystal display according to the first exemplary embodiment of the present invention inverts the polarity of the data voltage every frame period, and controls the data voltage with the same polarity as the previous frame period in units of N frame periods. In the N frame period and the 2N frame period, the pulse width of the source output enable signal SOE is increased to lower the charge amount of the liquid crystal cell Clc.

In FIG. 6, "VClc (SOE)" and "VClc (FGDSOE)" are voltages of the liquid crystal cell Clc.

7 to 9 are diagrams for explaining the effect of preventing the afterimage and flicker when the scroll data is supplied to any liquid crystal cell (Clc).

Referring to FIG. 7, when a symbol or a character is moved at a speed of 8 pixels per frame, and the data voltage is controlled at the same polarity as the previous frame in units of 8 frame periods by using a polarity control signal (Polarity, POL) The arbitrary liquid crystal cell Clc charges the data voltage of a symbol or a character in the hatched frame periods and the voltages are changed to "++"-> "-"-> "++"-> "-". Change. Therefore, the present invention can prevent the after-imaged DC image after accumulating the voltage of the same polarity by periodically inverting the polarity of the voltage charged in the liquid crystal cell (Clc) in the scroll data moving the sign or character at a constant speed.

As can be seen from the optical waveform which is the output waveform of the photo diode disposed on the liquid crystal display panel, the data voltages of the same polarity are repeated during two frame periods in succession of eight frame periods. Data voltages of the same polarity are accumulated in the liquid crystal cell, and the voltage thereof becomes large. Due to the cumulative voltage having the same polarity, the luminance of the liquid crystal cell Clc may increase rapidly in the second frame period among the two frame periods consecutive in the eight frame periods as shown in FIGS. In order to prevent the flicker phenomenon, the method of driving the liquid crystal display according to the exemplary embodiment of the present invention charges the liquid crystal cell Clc by using the second source output enable signal FGDSOE in the Nth and 2NN frame periods. The amount is lowered to prevent sudden changes in luminance as shown in FIG.

FIG. 10 is a diagram for explaining a DC prevention afterimage and flicker prevention effect when interlace data is supplied to an arbitrary liquid crystal cell Clc.

Referring to FIG. 10, when interlace data is supplied to a certain liquid crystal cell Clc, a high data voltage is supplied to the liquid crystal cell Clc only in the N-1th frame period and the N + 1th frame period, and the Nth frame A relatively low black voltage or average voltage is supplied in the period and the N + 2th frame period. As a result, the positive data voltage supplied in the N-1th frame period and the negative data voltage supplied in the N + 1th frame period are neutralized so that voltages of polarities deflected in the liquid crystal cell Clc are not accumulated. Therefore, in the liquid crystal display according to the exemplary embodiment of the present invention, the DC residual image and the flicker do not appear even when interlace data is supplied.

11 to 15 illustrate a liquid crystal display device according to a first embodiment of the present invention.

Referring to FIG. 11, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a POL / SOE logic circuit 102, a data driving circuit 103, and a gate. The drive circuit 104 is provided.

In the liquid crystal display panel 100, liquid crystal molecules are injected between two glass substrates. The liquid crystal display panel 100 includes m × n liquid crystal cells Clc in which m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix by a cross structure. Include.

The lower glass substrate of the liquid crystal display panel 100 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes 1 of a liquid crystal cell Clc connected to a TFT, and The storage capacitor Cst and the like are formed. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 100. Meanwhile, the common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS). In the horizontal electric field driving method as in the mode, the pixel electrode 1 is formed on the lower glass substrate. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

The timing controller 101 receives a timing signal such as a vertical / horizontal synchronization signal (Vsync, Hsync), a data enable (Data Enable), a clock signal (CLK), and the like, and the data driving circuit 104 and the gate driving circuit 104. And control signals for controlling the operation timing of the POL / SOE logic circuit 102. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). , A source sampling clock (SSC), a source output enable signal SOE, and a first polarity control signal POL. The gate start pulse GSP indicates a starting horizontal line at which scanning starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate driving circuit and is a timing control signal for sequentially shifting the gate start pulse GSP, and is generated with a pulse width corresponding to the ON period of the TFT. The gate output signal GOE indicates the output of the gate driving circuit 104. The source start pulse SSP indicates the start pixel on one horizontal line in which the data control signal DDC is to be displayed. The source sampling clock SSC instructs the latching operation of data in the data driving circuit 103 based on a rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. The first polarity control signal Polar (POL) indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The first polarity control signal POL is generated as either a polarity control signal of one dot inversion in which logic is inverted in one horizontal period or a polarity control signal of two dot in version in which logic is inverted in two horizontal periods. The timing controller 101 generates timing control signals at a 120 Hz or 60 Hz frame frequency to adjust the operation timing of the POL / SOE logic circuit 102, the data driving circuit 103, and the gate driving circuit 104 on a 120 Hz or 60 Hz basis. To control. The frame frequency indicates the number of screens per second as a frequency corresponding to the vertical synchronization signal Vsync. The 120 Hz frame frequency allows 120 screens per second to be displayed on the LCD panel 100, and the 60 Hz frame frequency allows 60 screens per second to be displayed on the LCD panel 100. Flicker is hardly felt compared to a 60 Hz frame frequency when the liquid crystal display is driven at a 120 Hz frame frequency.

The POL / SOE logic circuit 102 receives the gate start pulse GSP and the first polarity control signal POL to receive a multiple number of frame periods of N in order to prevent afterimage and flicker. The second polarity control signal FGDPOL is generated, and either one of the first polarity control signal POL and the second polarity control signal FGDPOL and POL is selectively supplied to the data driving circuit 103. As shown in FIG. 16, the logic of the first polarity control signal POL is inverted in units of one horizontal period or two horizontal periods, and the logic is inverted in units of one frame period to invert the polarity of the data voltage every one frame period. The second polarity control signal FGDPOL has the same phase as the frame period preceding the N th frame period in order to control the polarity of the data voltage in the same polar pattern as the previous frame period in the N th frame period of N as shown in FIG. Is generated and the logic is reversed in units of one horizontal period or two horizontal periods. In addition, the POL / SOE logic circuit 102 receives the first source output enable signal SOE and the third clock signal CLK3 to adjust the pulse width in a multiple of N frame periods to prevent afterimages and flicker. Generate a second source output enable signal FGDSOE and selectively supply one of the first source output enable signal SOE and the second source output enable signal FGDSOE to the data driving circuit 103. do. The first source output enable signal SOE is generated with the first pulse width W1 in every frame period. The second source output enable signal SOE is generated at the second pulse width W2 in the N multiple frame period and at the first pulse width W1 in other frame periods other than the N multiple frame period.

The liquid crystal display according to the first exemplary embodiment of the present invention further includes a multiplexer connected between the timing controller 101 and the POL / SOE logic circuit 102 to generate a third clock signal CLK. The multiplexer selects the first clock signal CLK1 generated from the internal oscillator of the timing controller 101 or the second clock signal CLK2 supplied from the external oscillator according to the control signal supplied to its control terminal, and selects the selected clock. The signal CLK1 or CLK2 is supplied to the POL / SOE logic circuit 102 as the third clock signal CLK3. The control terminal of this multiplexer is connected to the option pin. The option pin is connected to the control terminal of the multiplexer and can be selectively connected to the ground voltage source (GND) or power supply voltage (Vcc) by the manufacturer. For example, when the option pin is connected to the ground voltage source GND, the multiplexer is supplied with a selection control signal SEL of "0" to its control terminal to output the first clock signal CLK1 as the third clock signal CLK3. When the opsen pin is connected to the power supply voltage Vcc, the multiplexer is supplied with a selection control signal SEL of '1' to its control terminal to output the second clock signal CLK2 as the third clock signal CLK3. do.

The data driving circuit 103 latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 103 converts the digital video data into analog positive / negative gamma compensation voltages according to the polarity control signals POL / FGDPOL to generate positive / negative analog data voltages and converts the data voltages into data. Supply to lines D1 to Dm.

The gate driving circuit 104 has a shift register and a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn, respectively. It consists of a plurality of gate drive integrated circuits. The gate driving circuit 104 sequentially outputs gate pulses having a pulse width of approximately one horizontal period.

The POL / SOE logic circuit 102 may be embedded in the timing controller 101.

The liquid crystal display according to the first embodiment of the present invention further includes a system 105 for supplying digital video data RGB and timing signals Vsync, Hsync, DE, and CLK to the timing controller 101.

The system 105 extracts video data from a broadcast signal or an image source input from an external device, including a broadcast signal, an external device interface circuit, a graphic processing circuit, a line memory 106, and converts the video data into digital. Supply to timing controller 101. The interlace broadcast signal received by the system 106 is stored in line memory and then output. The video data of the interlace broadcast signal exists only in the odd line in the odd frame period and only in the even line in the even frame period. Accordingly, when the system 105 receives the interlace broadcast signal, the system 105 generates even line data of the odd frame period and odd line line data of the even frame as an average value or black data value of valid data stored in the line memory 106. This system 105 supplies timing signals 101 with timing signals Vsync, Hsync, DE, CLK together with the digital video data. Also, the system 105 includes a timing controller 101, a POL / SOE logic circuit 102, a data driving circuit 103, a gate driving circuit 104, and a DC-DC converter for generating driving voltages of the liquid crystal display panel. It supplies power to circuits such as a DC-DC convertor) and an inverter for lighting the light source of the backlight unit.

12 and 13 are circuit diagrams showing the data driving circuit 103 in detail.

12 and 13, the data driving circuit 103 includes a plurality of source integrated circuits (ICs) driving k (k is an integer smaller than m) data lines D1 to Dk, respectively. Include. Each of the source integrated circuits includes a shift register 111, a data register 112, a first latch 113, a second latch 114, a digital-to-analog converter (hereinafter referred to as a “DAC”) 115, and a charge share. A circuit (Charge Share Circuit) 116 and an output circuit 117.

The shift register 111 shifts the source start pulse SSP from the timing controller 101 according to the source sampling clock SSC to generate a sampling signal. In addition, the shift register 111 shifts the source start pulse SSP to transfer the carry signal CAR to the shift register 111 of the next integrated circuit. The data register 112 temporarily stores digital video data RGBodd of odd pixels and digital video data RGBeven of even pixels separated by the timing controller 101 and first stores the stored data RGBodd and RGBeven. Supply to 113. The first latch 113 samples the digital video data RGBeven and RGBodd from the data register 112 in response to a sampling signal sequentially input from the shift register 111 and the data RGBeven and RGBodd. Latches and outputs the data simultaneously. The second latch 114 simultaneously latches data input from the first latch 113 and then simultaneously with the second latch 114 of other integrated circuits during the low logic period of the source output enable signals SOE and FGDSOE. Output digital video data. The DAC 115 includes a P-decoder (PDEC) 121 supplied with a positive gamma reference voltage GH and an N-decoder (NDEC) 122 supplied with a negative gamma reference voltage GL as shown in FIG. 13. And a multiplexer 123 for selecting an output of the P-decoder 121 and an output of the N-decoder 122 in response to the polarity control signals FGDPOL / POL. The P-decoder 121 decodes the digital video data input from the second latch 114 and outputs a positive gamma compensation voltage corresponding to the gray value of the data, and the N-decoder 122 uses the second latch ( 114 decodes the digital video data inputted from the digital video data, and outputs a negative gamma compensation voltage corresponding to the grayscale value of the data. The multiplexer 123 selects a positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal FGDPOL / POL, and outputs the selected positive / negative gamma compensation voltage as an analog data voltage. The charge share circuit 116 shorts the neighboring data output channels during the high logic period of the source output enable signals SOE and FGDSOE, and outputs the average value of the neighboring data voltages as the charge share voltage, or the source output in. The common voltage Vcom is supplied to the data output channels during the high logic period of the enable signals SOE and FGDSOE to reduce the sudden change of the positive data voltage and the negative data voltage. The output circuit 117 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

14 and 15 are circuit diagrams showing the POL / SOE logic circuit 102 in detail.

Referring to FIG. 14, the POL / SOE logic circuit 102 includes a logic unit 131, first and second multiplexers 132 and 133.

The logic unit 131 receives the gate start pulse GSP, the first polarity control signal POL, the first source output enable signal SOE, and the clock signal CLK3 from the timing controller 101, and a multiple of N. The second polarity control signal FGDPOL is generated in the first frame period, and the second source output enable signal FGDSOE is generated in the multipleth N frame period.

The first multiplexer 132 selects one of the first polarity control signal POL and the second polarity control signal FGDPOL according to a logic value of the control signal applied to its control terminal.

The second multiplexer 133 selects one of the first source output enable signal SOE and the second source output enable signal FGDSOE according to a logic value of the control signal applied to the control terminal.

Control terminals of the first and second multiplexers 132 and 133 are connected to option pins. The option pin is connected to the control terminals of the first and second multiplexers 132 and 133 and may be selectively connected to the ground voltage source GND or the power supply voltage Vcc by the manufacturer. For example, when the option pin is connected to the ground voltage source GND, the first multiplexer 132 is supplied with a selection control signal SEL2 of "0" to its control terminal to output the second polarity control signal FGDPOL. The second multiplexer 133 is supplied with a selection control signal SEL2 of "0" to its control terminal to output the second source output enable signal FGDSOE. When the opsen pin is connected to the power supply voltage Vcc, the first multiplexer 132 is supplied with a selection control signal SEL2 of "1" to its control terminal to output the first polarity control signal POL, and the second The multiplexer 133 is supplied with a selection control signal SEL2 of "1" to its control terminal and outputs a first source output enable signal SOE.

15 and 16, the logic unit 131 includes a frame counter 141, a POL inverting unit 142, an exclusive OR gate (hereinafter referred to as “XOR”) 143, and an SOE timing analyzer 144. ), An SOE adjusting unit 145, and a third multiplexer 146.

The frame counter 141 is a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 in response to the gate start pulse GSP, which is generated once during one frame period and coincided with the start of one frame period. Outputs information Fcnt. In addition, the frame counter 141 generates N frame information indicating the Nth multiple frame period.

The POL inverting unit 142 receives the frame count information Fcnt from the frame counter 141 and calculates the rest of the frame count information Fcnt with N, and the logic is performed when the rest is '0'. Generates an output signal inverted. This output signal is a POL inversion signal (POLinv), which maintains high logic (or low logic) for N-1 frame periods as shown in FIG. 16, and low logic (or high logic) at the beginning of the Nth multiple-frame period. Is reversed. Therefore, the POL inversion signal POLinv output from the POL inversion unit 142 indicates its start time every N multiple times the frame period.

The XOR 143 performs an exclusive OR operation on the first polarity control signal POL and the POL inverted signal POLinv to have the same polarity pattern in multiples of N-1 and N frame periods as shown in FIG. A second polarity control signal FGDPOL is generated in which the polarity pattern is inverted in the frame period in the frame period.

The SOE timing analyzer 144 analyzes the first source output enable signal SOE in the unit of the clock signal CLK3 to measure the rising edge, pulse width, and polling of the first source output enable signal SOE. Detecting a falling edge.

The SOE adjustment unit 145 generates the second source output enable signal FGDSOE with the second pulse width W2 in the Nth th frame period using the SOE information Check_SOE from the SOE timing analyzer 144. do.

The third multiplexer 146 selects the output of the SOE adjustment unit 145 in the N th frame period according to the N frame information from the frame counter 141, and selects an output of the first multiplexer in a frame period other than the N th frame period. The source output enable signal SOE is selected to generate a second source output enable signal FGESOE.

17 is a flowchart illustrating a driving method of a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 17, in the driving method of the liquid crystal display according to the second exemplary embodiment of the present invention, the input data is analyzed to determine whether the input data is data in which a DC residual image may appear, such as interlace data or scroll data. (S1, S2)

In step S2, if it is determined that the current input data is data that can cause a DC residual image, the second embodiment of the present invention determines whether the current frame is a multiple of N frame period, and if the multiple times of N frame period, The polarity of the data voltage to be displayed on the liquid crystal display panel is controlled by using the polarity control signal FGDPOL and the second source output enable signal FGDSOE (S3 and S4).

In operation S2, if the current input data is not data capable of displaying a DC residual image, the data voltage to be displayed on the liquid crystal display panel using the first polarity control signal POL and the first source output enable signal SOE. Control the polarity (S5)

18 shows a liquid crystal display according to a second embodiment of the present invention.

Referring to FIG. 18, the liquid crystal display according to the second exemplary embodiment of the present invention may include a system 105, a liquid crystal display panel 100, an image analysis circuit 161, a timing controller 101, and a POL / SOE logic circuit. 162, a data driver circuit 103, and a gate driver circuit 104. In this embodiment, the system 105, the liquid crystal display panel 100, the timing controller 101, the data driving circuit 103 and the gate driving circuit 104 are substantially the same as those of the first embodiment described above, and therefore the same reference numerals. And the detailed description thereof will be omitted.

The image analysis circuit 161 determines whether DC residual image may occur with respect to the digital video data of the currently input image. The image analysis circuit 161 compares data between neighboring lines in one frame image, and determines the currently input data as interlace data when the data between the lines is larger than a predetermined threshold. In addition, the image analysis circuit 161 compares the data of each pixel on a frame-by-frame basis to detect a moving image in the display image and a moving speed of the image, and if the moving image moves at a preset speed, the moving image is included. The frame data is determined to be scroll data. As a result of the image analysis, the image analysis circuit 161 generates the selection signal SEL3 indicating the interlace data and the scroll data, and controls the POL / SOE logic circuit 162 using the selection signal SEL3. .

The POL / SOE logic circuit 162 performs a second operation in a multiple frame period of N when data for which a direct current residual image may appear in response to the first logic value of the selection signal SEL3 from the image analysis circuit 161 is input. The polarity control signal FGDPOL and the second source output enable signal FGESOE are generated. The POL / SOE logic circuit 162 generates a first polarity control signal when the data for which the DC residual image may appear may not be input in response to the second logic value of the selection signal SEL3 from the image analysis circuit 161. POL) and a first source output enable signal SOE.

The timing controller 101, the image analysis circuit 161, and the POL / SOE logic circuit 162 may be integrated in one chip.

As described above, the liquid crystal display device and the driving method thereof according to the embodiment of the present invention can prevent the DC afterimage by controlling the polarity of the data voltage in the same polar pattern as the previous frame period in the multipleth frame period of N. For example, the pulse width of the source output enable signal is widened during the multiple times of N to decrease the amount of charge of the liquid crystal cells, thereby reducing the flicker in the multiple times of N.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (39)

A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with gate pulses and having a plurality of liquid crystal cells; A data driving circuit inverting the polarity of the data voltage in response to a polarity control signal and outputting the data voltage to the data lines in response to a source output enable signal; A gate driving circuit supplying the gate pulses to the gate lines; And The polarity control signal is inverted in units of one frame period for a frame period other than a multiple of N (N is an integer greater than or equal to 8), and the phase of the polarity control signal for a multiple of N and the previous frame period of N. And a POL / SOE logic circuit controlling the same, and controlling the pulse width of the source output enable signal to be longer than other frame periods during the multiple times of the N frame periods. The method of claim 1, And the gate pulses of the source output enable and the gate pulses overlap each other during the multiple times N frame periods. The method of claim 1, The liquid crystal cell, Charging the data voltage for a frame period other than the multiple times frame period of N; Charging the data voltage after charging any one of a common voltage and a charge share voltage during the multiple times frame period of N; The common voltage is substantially equal to the voltage supplied to the common electrode of the liquid crystal cell, and the charge share voltage is an average voltage between the positive data voltage and the negative data voltage supplied to neighboring data lines. Liquid crystal display device. The method of claim 1, When the pulse width of the source output enable signal generated during another frame period other than the multiple of N frame period is '1', the pulse of the source output enable signal generated during the multiple of N frame period is '1'. The liquid crystal display device, characterized in that the width is 1.36 ~ 1.71. The method of claim 1, A reference polarity control signal inverted every one frame period for every frame period, a reference source output enable signal having a constant pulse width for all the frame periods, and a gate start pulse indicating the start of the gate pulse at the beginning of the frame period; And a timing controller which occurs once. The method of claim 5, wherein The POL / SOE logic circuit is By using the gate start pulse, the reference polarity control signal, the reference source output enable signal, and a clock signal, the polarity control signal and the N of A logic unit generating the source output enable signal having a wider pulse width during a multipleth frame period; A first multiplexer for selecting any one of the reference polarity control signal and the polarity control signal; And And a second multiplexer for selecting any one of the reference source output enable signal and the source output enable signal. The method of claim 6, The logic unit, A frame counter counting the gate start pulses to generate frame count information; A polarity inversion unit for generating a polarity inversion signal inverted at the beginning of the multiple times frame period of N using the output of the counter; An XOR gate generating an exclusive logic sum operation of the reference polarity control signal and the polarity inversion signal to generate the polarity control signal; A timing analyzer configured to detect a rising edge, a pulse width, and a falling edge of the reference source output enable signal using the clock signal to generate a timing analysis signal; A pulse width adjusting unit configured to generate a source output enable signal having a pulse width wider than that of the reference source output enable signal using the timing analysis signal; And In response to the output of the frame counter, the output of the pulse width adjusting unit is selected during the multiple times frame of N and the reference source output enable signal is selected for a frame period other than the multiple times frame of N. And a third multiplexer for outputting an output enable signal. A liquid crystal display panel having a plurality of data lines supplied with data voltages and a plurality of gate lines supplied with gate pulses and having a plurality of liquid crystal cells; An image analysis circuit for detecting any one of interlace data and scroll data in the input image; A data driving circuit inverting the polarity of the data voltage in response to a polarity control signal and outputting the data voltage to the data lines in response to a source output enable signal; A gate driving circuit supplying the gate pulses to the gate lines; And When one of the interlace data and the scroll data detected by the image analysis circuit is input, the polarity control signal is transmitted in units of one frame period for another frame period other than N (N is an integer of 8 or more). The polarity control signal phase is controlled in the same manner during the multiple times of N and the previous frame period, and the pulse width of the source output enable signal is changed to another frame during the multiple times of N. And a POL / SOE logic circuit for controlling longer than the period. The method of claim 8, And the gate pulses of the source output enable and the gate pulses overlap each other during the multiple times N frame periods. A driving method of a liquid crystal display apparatus having a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a gate pulse and having a plurality of liquid crystal cells, Inverts the polarity control signal in units of one frame period for a frame period other than the multipleth frame period of N (N is an integer greater than or equal to 8) and phases the polarity control signal during the multipleth frame period of N and the previous frame period. Equally controlling; Controlling a pulse width of a source output enable signal to be longer than another frame period during the multiple times frame period of N; Inverting the polarity of the data voltage in response to the polarity control signal and outputting the data voltage to the data lines in response to the source output enable signal; And And supplying the gate pulses to the gate lines. The method of claim 10, And superimposing the pulses of the source output enable and the gate pulses during the multiple times N frame periods. The method of claim 10, The liquid crystal cell, Charging the data voltage for a frame period other than the multiple times frame period of N; Charging the data voltage after charging any one of a common voltage and a charge share voltage during the multiple times frame period of N; The common voltage is substantially equal to the voltage supplied to the common electrode of the liquid crystal cell, and the charge share voltage is an average voltage between the positive data voltage and the negative data voltage supplied to neighboring data lines. A method of driving a liquid crystal display device. The method of claim 10, When the pulse width of the source output enable signal generated during another frame period other than the multiple of N frame period is '1', the pulse of the source output enable signal generated during the multiple of N frame period is '1'. A driving method for a liquid crystal display device, characterized in that the width is from 1.36 to 1.71. A driving method of a liquid crystal display apparatus having a liquid crystal display panel having a plurality of data lines supplied with a data voltage and a plurality of gate lines supplied with a gate pulse and having a plurality of liquid crystal cells, Detecting any one of interlace data and scroll data in the input image; When any one of the interlace data and the scroll data is input, the polarity control signal is inverted in units of one frame period for another frame period other than N (N is an integer of 8 or more). Controlling the phase of the polarity control signal equally during the period and the previous frame period; Controlling a pulse width of a source output enable signal to be longer than another frame period during the multiple times frame period of N; Inverting the polarity of the data voltage in response to the polarity control signal and outputting the data voltage to the data lines in response to the source output enable signal; And And supplying the gate pulses to the gate lines. The method of claim 14, And the gate pulses of the source output enable and the gate pulses overlap each other during the multiple times N frame periods. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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