KR100876893B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device according to the present invention includes a trench type isolation film formed to define an active region of a semiconductor substrate; A buried insulating layer formed to contact the device isolation layer in both side edge portions of the active region in a length direction; A recess gate formed on the semiconductor substrate including the device isolation layer, the recess gate including an operation gate disposed in the active region and a passing gate disposed on the device isolation layer; And a junction region formed in surfaces of active regions on both sides of the operation gate, and formed in an active region portion adjacent to the passing gate so as to extend below the buried insulation layer at least deeper than a bottom surface of the main gate.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art.

2 is a cross-sectional view of a semiconductor device for explaining the semiconductor device according to the embodiment of the present invention.

3A through 3F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100, 300: semiconductor substrate T: trench

H: groove 102, 302: device isolation film

104, 304 buried insulating film 106, 306 gate insulating film

108, 308: gate conductive films 110, 310: hard mask films

PG: Passing Gate G: Operation Gate

112, 312a, 312b: junction area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of improving operating characteristics of a DRAM cell transistor and a method for manufacturing the same.

As the integration of semiconductor devices increases, channel lengths of transistors decrease, and ion implantation concentrations in junction regions such as source and drain regions are increasing.

As a result, interference between the source region and the drain region is increased, a control ability of the gate is decreased, and a so-called short channel effect is generated in which a threshold voltage (Vt) is drastically lowered. In addition, a problem arises in that the refresh characteristic is deteriorated due to an increase in the junction leakage current due to an increase in the electric field of the junction region. Therefore, the structure of a transistor having a conventional planar channel structure has reached its limit in overcoming the problems associated with the high integration.

As a result, researches on ideas and actual process development researches on how to implement a MOSFET device having various types of recess channels capable of securing an effective channel length have been actively conducted. In addition, a method of forming a transistor having a channel having a three-dimensional structure capable of expanding a channel width has been proposed.

One such effort has recently been proposed in the field of logic devices (Fin Gate) having a channel having a three-dimensional structure. The protruding gate has a structure in which a gate line is formed to protrude a portion of the active region and surround the protruding active region. In this case, an effective channel width is increased to improve current drive characteristics through the channel. Threshold voltage margin is improved.

However, in the above-described prior art, a passing gate formed on the device isolation layer affects an operation gate formed in an active region, causing variation in the threshold voltage of the cell transistor, and leakage current (Leakage Current: LC) is increased, whereby the refresh characteristics are lowered and the operating characteristics of the cell transistors are deteriorated.

1 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art.

As illustrated, a junction region 112, such as a source region and a drain region, is formed in the semiconductor substrate 100 on which the device isolation layer 102, the pass gate PG, and the operation gate G are formed. The junction region 112 is formed to have a depth smaller than that of the operation gate G. For this reason, the influence of the passing gate PG on the operation gate G cannot be blocked.

In other words, when the passing gate PG is turned on, the generated electric field affects an adjacent operation gate G so that the operation gate G is turned on. As a result, the leakage current of the operation gate G increases, the threshold voltage fluctuates, and the refresh characteristic is deteriorated, thereby deteriorating the operating characteristics of the cell transistor.

Here, reference numeral 106 of FIG. 1 denotes a gate insulating film, 108 denotes a gate conductive film, and 110 denotes a hard mask film.

The present invention relates to a semiconductor device capable of reducing the effect of passing gates on adjacent operation gates and a method of manufacturing the same.

In addition, the present invention relates to a semiconductor device capable of improving refresh characteristics and a method of manufacturing the same.

In addition, the present invention relates to a method for manufacturing a semiconductor device capable of improving operating characteristics of a DRAM cell transistor.

In an embodiment, a semiconductor device may include a trench type isolation layer formed to define an active region of a semiconductor substrate; A buried insulating layer formed to contact the device isolation layer in both side edge portions of the active region in a length direction; A recess gate formed on the semiconductor substrate including the device isolation layer, the recess gate including an operation gate disposed in the active region and a passing gate disposed on the device isolation layer; And a junction region formed in surfaces of active regions on both sides of the operation gate, and formed in an active region portion adjacent to the passing gate so as to extend below the buried insulation layer at least deeper than a bottom surface of the main gate.

Here, the buried insulating film is formed to have a width of 300 ~ 1000Å.

The buried insulating film is formed to a depth similar to that of the operation gate.

The buried insulating film is formed to have a depth of 500 to 1500 Å.

The operation gate is formed in a fin pattern in which the active region at the bottom thereof protrudes.

In addition, a method of manufacturing a semiconductor device according to an embodiment of the present invention, forming a trench in the device isolation region of the semiconductor substrate having an active region and the device isolation region; Forming grooves on both side edge portions of the active region in contact with the trench; Depositing an insulating film to fill the trench and the trench to form a trench type device isolation layer defining the active region, and to form a buried insulation film in a groove in contact with the device isolation film; Forming a recess gate on the semiconductor substrate including the device isolation layer, the recess gate including an operation gate disposed in the active region and a passing gate disposed on the device isolation layer; And forming a junction region in an active region portion adjacent to the passing gate in an active region surface on both sides of the operation gate to extend below the buried insulating layer at a depth deeper than at least a bottom surface of the main gate. do.

The buried insulating film is formed to have a width of 300 to 1000 GPa.

The buried insulating film is formed to a depth similar to that of the operation gate.

The buried insulating film is formed to have a depth of 500 to 1500 Å.

The operation gate is formed in a fin pattern in which the active region at the bottom thereof protrudes.

The junction region is formed through an ion implantation process.

The ion implantation process is carried out with an energy of 50 ~ 100keV.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a trench is formed by first etching an isolation region of a semiconductor substrate, and second grooves are formed on both sides of the trench to form grooves having a depth smaller than that of the trench. Then, an insulating film is deposited in the trench and the grooves on both sides of the trench to form an isolation layer and a buried insulation layer, and a recess gate including a passing gate disposed on the isolation layer and an operation gate disposed in the active region. do.

Then, a junction region is formed in the substrates on both sides of the operation gate through an ion implantation process. In this case, the junction region is formed to extend from a portion adjacent to the passing gate to a lower portion of the buried insulating layer to have a depth deeper than or similar to a bottom surface of the operation gate.

In this case, the junction region formed in the portion adjacent to the passing gate and the operation gate may serve to block the influence of the passing gate on the operation gate, and thus an electric field generated when the passing gate is turned on. Can be prevented from affecting adjacent operation gates.

As a result, a phenomenon in which the leakage current of the operation gate increases and a variation in the threshold voltage can be suppressed. Through this, the refresh characteristic can be improved and the operating characteristic of the cell transistor can be improved.

2 is a cross-sectional view of a semiconductor device for describing a semiconductor device according to an embodiment of the present invention.

As shown, a trench (T) type isolation layer 302 defining the active region is formed in the semiconductor substrate 300 having an active region and an isolation region, and passing through the isolation layer 302. A recess gate is formed including a gate PG and an operation gate G disposed on the active region.

Here, the grooves H contacting the device isolation layer 302 are formed in both edge portions of the active region in the longitudinal direction, and the buried insulating layer 304 is formed in the grooves. In this case, the buried insulating film 304 is formed to have a width similar to that of the operation gate G, for example, about 300 to 1000 mW, and to a depth similar to the operation gate G, for example, about 500 to 1500 mW. It is formed to have a depth of. The operation gate G is formed in a fin pattern in which the active region at the bottom thereof protrudes.

Subsequently, junction regions 312a and 312b are formed in the active region of the semiconductor substrate 300 on both sides of the operation gate G through an ion implantation process. In this case, since the junction region 312a formed between the operation gate G and the passing gate PG extends to the lower portion of the buried insulating film 304, the junction region 312a may have a depth similar to that of the bottom surface of the operation gate G. Or is formed to have a deeper depth.

Therefore, in the present invention, the junction region 312a formed between the operation gate G and the passing gate PG serves to block the influence of the passing gate PG on the operation gate G, It is possible to prevent the threshold voltage of the cell transistor from fluctuating and increasing the leakage current, thereby improving the refresh characteristics and the operating characteristics of the cell transistor.

3A to 3F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, a first mask pattern (not shown) is formed on the semiconductor substrate 300 having an active region and an isolation region to expose the isolation region. Thereafter, the device isolation region of the semiconductor substrate 300 exposed by the first mask pattern is first etched to form a trench T, and then the first mask pattern is removed.

Referring to FIG. 3B, a second mask pattern (not shown) is formed on the semiconductor substrate 300 from which the first mask pattern is removed to expose a portion of the active region around the trench T including the trench T. Referring to FIG. do. Then, the upper portion of the trench T exposed by the second mask pattern is secondly etched by a predetermined depth to form grooves H having a depth smaller than the trenches T on both sides of the trench T. After that, the second mask pattern is removed.

In this case, the groove H is formed to contact the trench T in both side edge portions of the active region in the longitudinal direction. The groove H is formed to have a width similar to that of the operation gate disposed in the active region, for example, to have a width of about 300 to 1000 mW, and to have a depth similar to that of the operation gate, for example, to about 500 to 1500 mW. Form to have.

Referring to FIG. 3C, the trench T and the groove H provided on both sides of the trench T are filled with an insulating layer. Subsequently, the insulating film CMP is formed until the surface of the semiconductor substrate 300 is exposed to form a trench type isolation layer 302 defining the active region of the semiconductor substrate 300 in the trench T. A buried insulating film 304 having a depth smaller than that of the device isolation film 302 is formed in the groove H.

Referring to FIG. 3D, after a recess mask (not shown) is formed on the semiconductor substrate 300 on which the device isolation layer 302 and the buried insulating layer 304 are formed, the channel length is increased. The gate area exposed by the recess mask is recessed. Next, the recess mask is removed, and then a fin pattern (not shown) is formed in which a portion of the active region protrudes to increase the channel width.

Subsequently, the gate insulating film 306, the gate conductive film 308, and the hard mask film 310 are sequentially deposited on the surface of the semiconductor substrate 300 on which the fin pattern is formed.

Referring to FIG. 3E, the hard mask layer 310, the gate conductive layer 308, and the gate insulating layer 306 are sequentially etched to pass through the pass gate PG and the active region on the device isolation layer 302. A recess gate including an operation gate G disposed in the gate is formed. In this case, the operation gate G is formed in a fin pattern in which the active region at the bottom thereof protrudes.

Referring to FIG. 3F, an ion implantation process is performed on the semiconductor substrate 300 on which the passing gate PG and the operation gate G are formed to form a junction region in the semiconductor substrate 300 between the operation gate G. 312a, 312b). The ion implantation process is performed with an energy of about 50 to 100 keV.

In this case, the junction region 312a formed in a portion of the active region adjacent to the passing gate PG extends below the buried insulating layer 304 so that an influence of the passing gate PG on the operation gate G is blocked. To have a depth similar to that of the bottom of the operation gate G, or to have a deeper depth.

Thereafter, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device according to the embodiment of the present invention.

According to the present invention, the junction region formed in the portion adjacent to the passing gate may be formed to have a depth similar to that of the bottom of the operation gate, thereby preventing the passing gate from affecting the operation gate.

As a result, the present invention can suppress a phenomenon in which an electric field generated when the passing gate is turned on affects an adjacent operation gate and thus appears as if the operation gate is turned on. In addition, the leakage current of the operation gate may be reduced and the variation of the threshold voltage may be prevented.

Therefore, the present invention can not only improve the refresh characteristics, but also improve the operating characteristics of the DRAM cell transistor.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms a junction region between the passing gate and the operation gate to have a depth similar to that of the bottom of the operation gate, thereby preventing the passing gate from affecting the adjacent operation gate.

Therefore, the present invention can improve the refresh characteristics and can improve the operating characteristics of the DRAM cell transistor.

Claims (12)

A trench type isolation layer formed to define an active region of the semiconductor substrate; A buried insulating layer formed to contact the device isolation layer in both side edge portions of the active region in a length direction; A recess gate formed on the semiconductor substrate including the device isolation layer, the recess gate including an operation gate disposed in the active region and a passing gate disposed on the device isolation layer; And A junction region formed in surfaces of active regions on both sides of the operation gate, the junction region being formed to extend below the buried insulation layer at least deeper than a bottom surface of the main gate in an active region portion adjacent to the passing gate; A semiconductor device comprising a. The method of claim 1, The buried insulating film is a semiconductor device, characterized in that formed to have a width of 300 ~ 1000Å. The method of claim 1, And the buried insulation film is formed to a depth similar to that of the operation gate. The method of claim 3, wherein The buried insulating film is a semiconductor device, characterized in that formed to have a depth of 500 ~ 1500Å. The method of claim 1, And the operation gate is formed in a fin pattern in which the active region at the bottom thereof protrudes. Forming a trench in the isolation region of the semiconductor substrate having an active region and an isolation region; Forming grooves on both side edge portions of the active region in contact with the trench; Depositing an insulating film to fill the trench and the trench to form a trench type device isolation layer defining the active region, and to form a buried insulation film in a groove in contact with the device isolation film; Forming a recess gate on the semiconductor substrate including the device isolation layer, the recess gate including an operation gate disposed in the active region and a passing gate disposed on the device isolation layer; And Forming a junction region in an active region portion adjacent to the passing gate in an active region surface on both sides of the operation gate such that a junction region extends below the buried insulating layer at least deeper than a bottom surface of the main gate; Method of manufacturing a semiconductor device comprising a. The method of claim 6, And the buried insulating film is formed to have a width of 300 to 1000 GPa. The method of claim 6, And the buried insulation film is formed to a depth similar to that of the operation gate. The method of claim 8, And the buried insulating film is formed to have a depth of 500 to 1500 Å. The method of claim 6, And the operation gate is formed in a fin pattern with the active region protruding from the bottom thereof. The method of claim 6, The junction region is formed by an ion implantation process. The method of claim 11, The ion implantation process is a method of manufacturing a semiconductor device, characterized in that performed with energy of 50 ~ 100keV.

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