KR100855624B1 - Semiconductor package and manufacturing method - Google Patents

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. Bonding a first semiconductor chip having a first connection terminal on one surface to one surface of a heat sink having a through electrode, electrically connecting one side of the through electrode and the first connection terminal, and coating an insulating material on one surface of the heat sink 1 encapsulating a semiconductor chip, bonding the other surface of the second semiconductor chip having a second connection terminal to one surface thereof to the other surface of the heat sink, and coating the second semiconductor chip by coating an insulating material on the other surface of the heat sink. A method of manufacturing a semiconductor package comprising encapsulating and insulating the insulating material to form a first via electrically connected to the other side of the through electrode and the second connection terminal, wherein the semiconductor chip is directly bonded to a heat sink to form a thermal path. By shortening the heat dissipation efficiency of the semiconductor package can be enhanced, a plurality of semiconductor chips can be stacked vertically to reduce the package size. In addition, build-up technology can be applied to improve the reliability of the connection.

Description

Semiconductor package and method for manufacturing the same

1 is a cross-sectional view showing a first semiconductor package according to the prior art.

2 is a cross-sectional view showing a second semiconductor package according to the prior art.

3 is a flow chart of a method of manufacturing a semiconductor package according to the first embodiment of the present invention.

4 is a flowchart of a method of manufacturing a semiconductor package according to the first embodiment of the present invention.

5 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

6 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

7 is a sectional view of a semiconductor package according to a fourth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

12 through electrode 13 flip chip bonding

14 wire 20 heat sink

21: Floor 23: First mounting space

24: adhesive 25: second mounting space

26, 28: semiconductor chip 27, 29: connection terminal

30: insulating material 34: via hole

36: First Via 37: Third Via

38: Buildup Layer 40: Second Via

41: bump pad 42: bump

The present invention relates to a semiconductor package and a method of manufacturing the same.

The semiconductor package is a technology for efficiently packaging devices used in electronic products, and includes chip packaging technology for bonding and electrically connecting the cut semiconductor chips to a substrate and modularizing them. In package technology, through small size and excellent surface mount package technology, recently high density package technology and peripheral package technology are applied to surface mount type such as ball grid array (BGA) and chip scale package (CSP). It is rapidly developing into a smile and light weight trend.

Current chip scale package (CSP) is a flip chip (Flip chip) method is applied, the bump ball (Bump Ball) technology is essentially used for the electrical connection between the chip or the chip and the substrate. Such bump ball technology has a problem of reliability due to solder fatigue failure due to thermal stress at the connection with the chip pad, and the I of the package due to the limitation of the miniaturization of the bump ball. The problem is that the number of / O is limited.

The flip chip method to which the bump ball technology is applied generates an additional problem that the overall process is complicated and the cost increases because an under fill process must be added to supplement the reliability problem described above.

To solve this problem, as shown in FIGS. 1 and 2, the build-up layer 110 is built up from the electrical contact pattern 104 on the semiconductor chip 102. So-called 'build up technology' was developed. However, even in the case of the build-up technology, there is a problem that the overall size of the package becomes large in the process of forming a package structure such as SIP (System In Package). That is, as shown in FIG. 2, in the case of a package using a plurality of semiconductor chips 102, each semiconductor chip must be mounted in a horizontal array method so that the entire set may be installed. It is difficult to minimize the pattern size.

In addition, heat generated by the driving of the device is discharged through the heat sink 108 covering the outer portion of the encapsulant through the encapsulant 106 surrounding the outer portion of the semiconductor chip 102 on the surface of the semiconductor chip 102. There is a problem in that the path of heat is long so that heat cannot be effectively released.

SUMMARY OF THE INVENTION The present invention provides a semiconductor package and a method of manufacturing the same, by applying a build-up technique to improve the reliability of the connection and stacking a plurality of semiconductor chips vertically to reduce the package size.

In addition, the present invention is to provide a semiconductor package and a method of manufacturing the semiconductor chip that can be directly bonded to the heat sink to shorten the thermal path to enhance the heat dissipation efficiency of the semiconductor package.

According to an aspect of the invention, the step of bonding the first semiconductor chip having the first connection terminal on one surface to one surface of the heat sink having a through electrode, electrically connecting one side of the through electrode and the first connection terminal, the heat sink Encapsulating the first semiconductor chip by coating an insulating material on one surface thereof, bonding the other surface of the second semiconductor chip having a second connection terminal to one surface thereof to the other surface of the heat sink, and coating an insulating material on the other surface of the heat sink. 2. A method of manufacturing a semiconductor package is provided, the method comprising encapsulating a semiconductor chip, and forming a first via electrically connected to another side of the through electrode and a second connection terminal by drilling an insulating material.

After the step of forming the first via, the build-up step of stacking the build-up layer on the other surface of the heat sink coated with the insulating material, and further comprises a build-up step of forming a second via electrically connected to the first via by drilling the build-up layer Can be.

Buildup layers may be stacked in plurality, and second vias may be formed in the plurality of buildup layers, respectively.

After the buildup step, the method may further include forming a conductive bump electrically connected to the second via on the surface of the buildup layer.

Bonding to one surface of the heat sink or bonding to the other surface of the heat sink includes bonding the first semiconductor chip or the second semiconductor chip to the heat sink through an adhesive between the heat sink and the first semiconductor chip or the second semiconductor chip. It may include a step.

The step of electrically connecting may be performed by wire bonding one side of the through electrode and the first connection terminal.

The through electrode is formed to correspond to the first connection terminal, and the step of electrically connecting may be performed by flip chip bonding so that one side of the through electrode and the first connection terminal face each other.

Bonding to one surface of the heat sink includes bonding the other surface of the first semiconductor chip to one surface of the heat sink, and electrically connecting is electrically connected to one side of the through electrode and the first connection terminal by drilling an insulating material. Forming a third via.

Encapsulating the first semiconductor chip or encapsulating the second semiconductor chip may include applying and firing a liquid resin on the heat sink to cover the first semiconductor chip or the second semiconductor chip. have.

The forming of the first via may include drilling a via hole by drilling an insulating material to expose the other side of the through electrode, drilling a via hole by exposing the insulating material to expose a second connection terminal, and plating an inner surface of the via hole. It may include.

The first mounting space recessed in one surface of the heat sink is formed, the step of bonding to one surface of the heat sink may include the step of bonding the first semiconductor chip to the bottom surface of the first mounting space.

Encapsulating the first semiconductor chip may include applying an insulating material to fill the first mounting space.

A second mounting space recessed on the other surface of the heat sink is formed, and the step of bonding to the other surface of the heat sink may include bonding the other surface of the second semiconductor chip to the bottom surface of the second mounting space.

Encapsulating the second semiconductor chip may include applying an insulating material to fill the second mounting space.

In addition, according to another aspect of the present invention, a heat dissipation plate having a first semiconductor chip having a first connection terminal formed on one surface thereof, a through electrode electrically connected to the first connection terminal formed on one side thereof, and having a first surface bonded to the first semiconductor chip And a second semiconductor chip having a second connection terminal formed on one surface and the other surface bonded to the other surface of the heat sink, and a through electrode penetrating through the insulating material and the insulating material stacked on the heat sink and encapsulating the first semiconductor chip and the second semiconductor chip. A semiconductor package including a first via electrically connected to another side of the second terminal and a second connection terminal is provided.

On the other hand, it may further include a build-up layer and a second via electrically connected to the first via through the build-up layer stacked on the other surface of the heat sink coated with the insulating material.

The buildup layer may be stacked in plural, and the second via may be formed in plural so as to be processed in the plurality of buildup layers and electrically connected to each other.

The semiconductor device may further include a conductive bump formed on a surface of the buildup layer and electrically connected to the second via.

One side of the through electrode and the first connection terminal may be electrically connected by wire bonding.

The through electrode may be formed to correspond to the first connection terminal, and may be electrically connected by flip chip bonding so that one side of the through electrode and the first connection terminal face each other.

The other surface of the first semiconductor chip may further include a third via bonded to one surface of the heat sink and electrically connected to one side of the through electrode and the first connection terminal through the insulating material.

The first mounting space recessed in one surface of the heat sink is formed, the first semiconductor chip can be bonded to the bottom surface of the first mounting space.

The insulating material may encapsulate the first semiconductor chip by filling the first mounting space.

A second mounting space recessed in the other surface of the heat sink is formed, the other surface of the second semiconductor chip may be bonded to the bottom surface of the second mounting space.

The insulating material may encapsulate the second semiconductor chip by filling the second mounting space.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

Hereinafter, an embodiment of a semiconductor package and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, and in the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numbers. Duplicate explanations will be omitted.

3 is a flowchart of a semiconductor package manufacturing method according to a first embodiment of the present invention, and FIG. 4 is a flowchart of a semiconductor package manufacturing method according to a first embodiment of the present invention. Referring to FIG. 4, the through electrode 12, the wire 14, the heat sink 20, the bottom surface 21, the first mounting space 23, the second mounting space 25, the adhesive 24, and the first electrode 12 are formed. 1 semiconductor chip 26, first connection terminal 27, second semiconductor chip 28, second connection terminal 29, insulating material 30, via hole 34, first via 36, build-up Layer 38, solder resist 39, second via 40, bump land 41, and bump 42 are shown.

In the present exemplary embodiment, the first semiconductor chip 26 having the first connection terminal 27 formed on one surface thereof is bonded to one surface of the heat sink 20 having the through electrode 12 formed thereon. 1, electrically connecting the connection terminal 27, encapsulating the first semiconductor chip 26 by coating the insulating material 30 on one surface of the heat sink 20, and second connecting terminal 29 on one surface of the heat sink 20. Bonding the other surface of the second semiconductor chip 28 having the substrate to the other surface of the heat sink 20, and encapsulating the second semiconductor chip 28 by coating the insulating material 30 on the other surface of the heat sink 20. And forming a first via 36 electrically connected to the other side of the through electrode 12 and the second connection terminal 29 by puncturing the insulating material 30 to directly heat-dissipate the semiconductor chip 20. ) To shorten the thermal path to enhance the heat dissipation efficiency of the semiconductor package, and to stack a plurality of semiconductor chips vertically It can reduce the paper size. In addition, build-up technology can be applied to improve the reliability of the connection.

Referring to the method of manufacturing a semiconductor package according to the present embodiment, first, as shown in FIGS. 4A and 4B, a first semiconductor chip having a first connection terminal 27 formed on one surface thereof is illustrated. (26) is bonded to one surface of the heat sink 20 in which the through electrode 12 is formed (S100).

The heat sink 20 is for dissipating heat generated during the operation of the device to the outside, and the heat sink 20 may be made of a copper sheet, a metal sheet, a silicon sheet, a metal foil, a copper foil, or a silicon sheet deposited on the surface of the metal layer. Can be.

The through electrode 12 is formed through the heat sink 20 for electrical connection between one surface and the other surface of the heat sink 20. The through electrode 12 is for electrical conduction between the semiconductor chip or the buildup layer 38 formed on one surface and the other surface of the heat sink 20 and may be made of a conductive material. In general, since the heat sink 20 is often made of a metallic material such as copper, an insulating material is interposed on the outer circumferential surface of the through electrode 12 to prevent short circuit between the through electrode 12 and the heat sink 20. The short circuit between the heat sink 20 and the through electrode 12 is prevented. Of course, when the heat sink 20 is made of an insulating material, the through electrode 12 may be formed to penetrate the heat sink 20.

In the present embodiment, the other surface of the first semiconductor chip 26 having the first connection terminal 27 formed on one surface is bonded to one surface of the heat sink 20. That is, as shown in FIG. 4B, the first semiconductor chip is disposed such that the other surface of the first semiconductor chip 26 on which the first connection terminal 27 is not formed and one surface of the heat sink 20 face each other. The other surface of 26 is bonded to one surface of the heat sink 20. This is for bonding the first connection terminal 27 and one side of the through electrode 12 in the subsequent process by bonding the wire 14.

Meanwhile, one surface of the first semiconductor chip 26 may be joined to one surface of the heat sink 20 (see FIG. 6). That is, the first semiconductor chip 26 having the through electrode 12 formed at a position corresponding to the first connection terminal 27 of the first semiconductor chip 26 and having the first connection terminal 27 formed on one surface thereof. One surface of is bonded to one surface of the heat sink 20 in which the through electrode 12 corresponding to the first connection terminal 27 is formed.

The fact that the through electrode 12 is formed at a position corresponding to the first connection terminal 27 of the first semiconductor chip 26 means that the first semiconductor chip 26 has the first connection terminal 27 formed on one surface thereof. When one surface is bonded to one surface of the heat sink 20, the through electrode 12 is connected such that the first connection terminal 27 for electrical connection with the outside of the first semiconductor chip 26 is communicated through the through electrode 12. It means that the heat sink 20 is formed. As such, the first connection terminal 27 of the first semiconductor chip 26 may implement electrical connection through the through electrode 12.

In the present exemplary embodiment, the first mounting space 23 is recessed in one surface of the heat sink 20 so that the thickness of the semiconductor package can be reduced, and thus the first mounting space 23 is formed on the bottom surface 21 of the first mounting space 23. The semiconductor chip 26 is bonded (S101).

In order to bond the first semiconductor chip 26 and the heat sink 20, the first semiconductor chip 26 is attached to the heat sink 20 through the adhesive 24 between the first semiconductor chip 26 and the heat sink 20. Can be bonded. As a result, the first semiconductor chip 26 can be bonded to the heat sink 20 inexpensively and quickly.

Next, as shown in FIG. 4B, one side of the through electrode 12 and the first connection terminal 27 are electrically connected (S200). As described above, the other surface of the first semiconductor chip 26 on which the first connection terminal 27 is not formed and the other surface of the first semiconductor chip 26 face each other so that the other surface of the first semiconductor chip 26 is not disposed. When bonded to one surface of the first connection terminal 27 and one side of the through electrode 12 can be electrically connected by bonding the wire 14 (S201).

On the other hand, when the first connecting terminal 27 is formed on one surface of the first semiconductor chip 26 and one surface of the first semiconductor chip 26 is joined to one surface of the heat sink 20, the through electrode 12 One side and the first connection terminal 27 may be electrically connected by flip chip bonding. In the flip chip bonding process, a bump is attached to a first connection terminal 27 formed on one surface of the first semiconductor chip 26, a reflow flux is applied, and the bump is passed through a through electrode ( After mounting on one side of 12), the bumps are melted by reflow heating to electrically connect the first connection terminal 27 of the first semiconductor chip 26 and one side of the through electrode 12 to each other.

Next, as shown in FIG. 4C, the first semiconductor chip 26 is encapsulated by coating the insulating material 30 on one surface of the heat sink 20 (S300). The encapsulation process is formed by applying a liquid PI (polyimide) resin (resin) on the heat sink 20 so as to cover the first semiconductor chip 26 bonded to one surface of the heat sink 20 and firing it.

In the present exemplary embodiment, the first semiconductor chip bonded to the bottom surface 21 of the first mounting space 23 is coated with an insulating material 30 so that the first mounting space 23 formed on one surface of the heat sink 20 is embedded. 26) is encapsulated (S301).

Meanwhile, vias and circuit patterns may be formed using the insulating material 30 encapsulating the first semiconductor chip 26 as one substrate (see FIG. 7). That is, the other surface of the first semiconductor chip 26 is disposed on one surface of the heat sink 20 so that the other surface of the first semiconductor chip 26 on which the first connection terminal 27 is not formed and one surface of the heat sink 20 face each other. After encapsulating the first semiconductor chip 26 by bonding the insulating material 30 to one surface of the heat sink 20, and encapsulating the insulating material 30, one side and the first connection terminal of the through electrode 12 are drilled. A via may be formed to be electrically connected with the reference numeral 27.

Next, as shown in FIG. 4D, the other surface of the second semiconductor chip 28 having the second connection terminal 29 formed on one surface thereof is bonded to the other surface of the heat sink 20 (S400). That is, as shown in (d) of FIG. 4, the second semiconductor chip (ie, the second surface of the second semiconductor chip 28 on which the second connection terminal 29 is not formed and the other surface of the heat sink 20 are opposed to each other). The other surface of 28 is bonded to the other surface of the heat sink 20. Therefore, even if a plurality of semiconductor chips are stacked, all of the semiconductor chips 26 and 28 are directly bonded to the heat sink 20, thereby improving heat dissipation efficiency. In order to bond the second semiconductor chip 28 and the heat sink 20, the second semiconductor chip 28 is attached to the heat sink 20 through the adhesive 24 between the second semiconductor chip 28 and the heat sink 20. Can be bonded. As a result, the second semiconductor chip 28 can be bonded to the heat sink 20 inexpensively and quickly.

In the present embodiment, as described above, the second mounting space 25 is recessed in the other surface of the heat sink 20 so as to reduce the thickness of the semiconductor package, thereby forming the second surface of the second semiconductor chip 28 as the second surface. It is bonded to the bottom surface 21 of the mounting space 25 (S401).

Next, as shown in FIG. 4E, the second semiconductor chip 28 is encapsulated by coating the insulating material 30 on the other surface of the heat sink 20 (S500). The encapsulation process applies a liquid PI (polyimide) resin on the heat sink 20 to cover the second semiconductor chip 28 bonded to the other surface of the heat sink 20 and calcinates it as described above. .

In the present exemplary embodiment, the second semiconductor chip bonded to the bottom surface 21 of the second mounting space 25 by applying an insulating material 30 so that the second mounting space 25 formed on the other surface of the heat sink 20 is embedded. 28) encapsulated (S501). The insulating material 30 encapsulating the second semiconductor chip 28 may serve as one substrate in a subsequent process so that vias or circuit patterns may be formed on the insulating material 30.

Next, as illustrated in FIGS. 4F and 4G, the insulating material 30 is punctured to electrically connect with the other side of the through electrode 12 and the second connection terminal 29. 1 via 36 is formed (S600). In forming the first via 36, a process of forming the via hole 34 is required. As shown in FIG. 4F, the first via 36 is electrically connected to the first connection terminal 27 of the first semiconductor chip 26. Drilling the insulating material 30 to expose the other side of the through-electrode 12 connected to the via hole 34 to drill the via hole 34, the insulating material 30 so that the second connection terminal 29 of the second semiconductor chip 28 is exposed. Drilling holes to drill the via hole (34). When the via hole 34 is drilled, plating is performed on the inner surface of the via hole 34. The plating may be performed by applying a process such as Cu sputtering or conductive paste filling to form a plating layer. The first via 36 allows the first connection terminal 27 of the first semiconductor chip 26 to be electrically connected to the outside through the penetrating electrode 12 and is bonded to the other surface of the heat sink 20. The second connection terminal 29 of the second semiconductor chip 28 may be electrically connected to the outside.

Of course, the drilling process used for drilling the via hole 34 and the plating process for electrically conducting the via hole 34 are not limited to the above-described embodiment.

In the present embodiment, the insulating material 30 for embedding the second mounting space 25 formed on the other surface of the heat sink 20 is drilled to be electrically connected to the other side of the through electrode 12 and the second connection terminal 29. One via 36 is formed. That is, the insulating material 30 filling the second mounting space 25 may form a single layer substrate, and the first via 36 and the circuit pattern may be formed on the substrate.

Next, as shown in (h) of FIG. 4, the buildup layer 38 is laminated on the other surface of the heat sink 20 to which the insulating material 30 is applied, and the buildup layer 38 is perforated to form a first layer. A second via 40 electrically connected to the via 36 is formed (S700).

The number of stacks of the buildup layer 38 and the processing of the via holes 34 may vary depending on the design of the semiconductor package. 4 illustrates an example in which two buildup layers 38 are stacked and conductive bumps 42 are combined.

The buildup layer 38 may be formed by applying a liquid insulating material or by bonding an insulating material in the form of a film. For example, the liquid PI, which is the same material as the insulating material 30 of the encapsulating process, may be applied and cured, or the PI film may be laminated.

When the build-up layer 38 is made of the same material as the insulating material 30, the encapsulating process of the semiconductor chip and the lamination process of the build-up layer 38 can be performed in the same process. Since the shrinkage and expansion of the semiconductor package due to heat generated in the semiconductor chip are not different in the insulating material 30 and the buildup layer 38, an error due to thermal stress can be prevented.

When the buildup layer 38 is stacked, the via holes are processed to form second vias 40 electrically connected to the first vias 36. The process of forming the second via 40 may be the same as the process of forming the first via 36 described above. That is, to form the via hole by drilling the build-up layer 38 to expose the land portion of the first via 36 and plating the inner surface of the via hole to electrically connect the first via 36 and the second via 40 to each other. do.

4 repeats the above-described buildup process when stacking a plurality of buildup layers 38 as an example of a buildup process of stacking two buildup layers 38. As described above, the buildup process is performed a plurality of times as necessary according to the design of the semiconductor package. Accordingly, a plurality of buildup layers 38 are stacked, and the second via 40 is formed in each buildup layer 38. Is processed to implement the electrical connection passage. In the present embodiment, the bump lands 41 for forming the solder resist 39 in the outermost buildup layer 38 and for joining the conductive bumps 42 such as solder balls. ) And a contact point for electrical connection between the semiconductor package and the external device (see (i) of FIG. 4). The bump lands 41 are electrically connected to the second vias 40.

Next, as illustrated in FIG. 4J, a conductive bump 42 electrically connected to the second via 40 is formed on the surface of the build-up layer 38 (S800). The conductive bumps 42 are for electrical connection between the semiconductor package and the external device, and may be formed by bonding the conductive bumps 42 such as solder balls to the bump lands 41 formed in the previous process.

5 is a cross-sectional view of a semiconductor package according to a second exemplary embodiment of the present invention. Referring to FIG. 5, the through electrode 12, the wire 14, the heat sink 20, the first mounting space 23, the adhesive agent 24, the second mounting space 25, and the first semiconductor chip 26 are described. , The first connection terminal 27, the second semiconductor chip 28, the second connection terminal 29, the insulating material 30, the buildup layer 38, the first via 36, the solder resist 39, Second via 40, bump land 41, and bump 42 are shown.

In the semiconductor package according to the present exemplary embodiment, a first semiconductor chip 26 having a first connection terminal 27 formed on one surface thereof and a through electrode 12 having one side electrically connected to the first connection terminal 27 formed thereon A heat sink 20 having one surface bonded to the first semiconductor chip 26, a second connection terminal 29 formed at one surface thereof, and a second semiconductor chip 28 formed at the other surface bonded to the other surface of the heat sink 20, The other side and the second connection of the through electrode 12 through the insulating material 30 and the insulating material 30 which are stacked on the heat sink 20 and encapsulate the first semiconductor chip 26 and the second semiconductor chip 28. Using the first via 36 electrically connected to the terminal 29 as a component, the semiconductor chip can be directly bonded to the heat sink 20 to shorten the thermal path, thereby enhancing heat dissipation efficiency of the semiconductor package. The package size can be reduced by stacking the semiconductor chips vertically. In addition, build-up technology can be applied to improve the reliability of the connection.

Since the electrical path from the semiconductor chip is implemented through the build-up process from the connection terminal of the semiconductor chip, a finer pitch can be realized. For example, when a pitch of about 100 micrometers is implemented by applying a conventional bump ball technology, a pitch of about 30 micrometers may be implemented by applying a build-up technique according to the present embodiment, thereby realizing fine pitch and This can contribute to the miniaturization of the package.

The heat sink 20 is for dissipating heat generated during the operation of the device to the outside, and the heat sink 20 may be made of a copper sheet, a metal sheet, a silicon sheet, a metal foil, a copper foil, or a silicon sheet deposited on the surface of the metal layer. Can be.

The through electrode 12 is formed through the heat sink 20 for electrical connection between one surface and the other surface of the heat sink 20. The through electrode 12 may be formed of a conductive material for electrical conduction between the semiconductor chips 26 and 28 or the buildup layer 38 formed on one surface and the other surface of the heat sink 20. In general, since the heat sink 20 is often made of a metallic material such as copper, an insulating material is interposed on the outer circumferential surface of the through electrode 12 to prevent short circuit between the through electrode 12 and the heat sink 20. Short circuit between the heat sink 20 and the through electrode 12 can be prevented. Of course, when the heat sink 20 is made of an insulating material, the through electrode 12 may be formed to penetrate the heat sink 20.

According to the present exemplary embodiment, when the other surface of the first semiconductor chip 26 having the first connection terminal 27 formed on one surface is bonded to one surface of the heat sink 20, one side of the through electrode 12 and the first connection terminal 27 are formed. ) To bond the wires 14 for electrical connection. That is, as shown in FIG. 5, the other surface of the first semiconductor chip 26 on which the first connection terminal 27 is not formed and the other surface of the heat dissipation plate 20 face each other. Is bonded to one surface of the heat sink 20, and one side of the through electrode 12 and the first connection terminal 27 are electrically connected by bonding the wires 14. In addition, in the present exemplary embodiment, the first mounting space 23 is recessed in one surface of the heat sink 20 so as to reduce the thickness of the semiconductor package, thereby providing the bottom surface 21 of the first mounting space 23. The other surface of the first semiconductor chip 26 is bonded.

The wire 14 is for electrical connection between one side of the through electrode 12 and the first connection terminal 27, and one side of the through electrode 12 and the first connection terminal 27 are bonded by wire 14. Electrically connected. As such, one side of the through electrode 12 and the first connection terminal 27 are electrically connected to each other, such that the first semiconductor chip 26 may be electrically connected to the buildup layer 38 through the through electrode 12. have.

On the other hand, the other surface of the second semiconductor chip 28 having the second connection terminal 29 formed on one surface is joined to the other surface of the heat sink 20. That is, as shown in FIG. 5, the other surface of the second semiconductor chip 28 so that the other surface of the second semiconductor chip 28 on which the second connection terminal 29 is not formed and the other surface of the heat sink 20 face each other. Is bonded to the other surface of the heat sink (20). Therefore, even when a plurality of semiconductor chips are stacked, all of the semiconductor chips are directly bonded to the heat sink 20, thereby improving heat dissipation efficiency. In addition, in the present embodiment, as described above, the second mounting space 25 is recessed in the other surface of the heat sink 20 so as to reduce the thickness of the semiconductor package, thereby forming the other surface of the second semiconductor chip 28. The bottom surface 21 of the second mounting space 25 is bonded.

The insulating material 30 is stacked on the heat sink 20 to encapsulate the first semiconductor chip 26 and the second semiconductor chip 28. The insulating material 30 covers the semiconductor chip to protect the semiconductor chip from an impact from the outside, and improves the bonding reliability of the semiconductor chip and the heat sink 20. The insulating material 30 is formed by applying a liquid PI (polyimide) resin (resin) and firing it.

In the present embodiment, the first mounting space 23 is coated by the insulating material 30 so that the first mounting space 23 formed on one surface of the heat sink 20 and the second mounting space 25 formed on the other surface of the heat sink 20 are embedded. The first semiconductor chip 26 bonded to the bottom surface 21 of the 23 and the second semiconductor chip 28 bonded to the bottom surface 21 of the second mounting space 25 are encapsulated. The insulating material 30 encapsulating the second semiconductor chip 28 may serve as one substrate in a subsequent process so that vias and circuit patterns may be formed on the insulating material 30.

The first via 36 penetrates the insulating material 30 and is electrically connected to the other side of the through electrode 12 and the second connection terminal 29 of the second semiconductor chip 28. ) And the second semiconductor chip 28. In forming the first via 36, first, a via hole is required. As illustrated in FIG. 5, the through electrode 12 electrically connected to the first connection terminal 27 of the first semiconductor chip 26 is formed. The through hole is drilled by drilling the insulating material 30 so as to expose the other side thereof, and the via hole is drilled by drilling the insulating material 30 to expose the second connection terminal 29 of the second semiconductor chip 28. When the via hole is drilled, plating is performed on the inner surface of the via hole. The plating may be performed by applying a process such as Cu sputtering or conductive paste filling to form a plating layer. The first via 36 allows the first connection terminal 27 of the first semiconductor chip 26 to be electrically connected to the outside through the penetrating electrode 12 and is bonded to the other surface of the heat sink 20. The second connection terminal 29 of the two semiconductor chips 28 may be electrically connected to the outside.

The buildup layer 38 is laminated on the other surface of the heat sink 20 to which the insulating material 30 is applied to form a multi-layered substrate. The buildup layer 38 may be formed to provide electrical connection between the first via 36 and the buildup layer 38. Two vias 40 are formed. The number of stacks of the buildup layer 38 and the processing of the via holes may vary depending on the design of the semiconductor package. FIG. 5 illustrates an example in which two buildup layers 38 are stacked and conductive bumps 42 are combined.

The buildup layer 38 may be made of an insulating material, and may be formed by applying a liquid PI, which is the same material as the insulating material 30, to be cured, or by stacking a PI film.

When the build-up layer 38 is made of the same material as the insulating material 30, the encapsulation process of the semiconductor chip and the lamination process of the build-up layer 38 can be performed in the same process. Since the shrinkage and expansion of the semiconductor package due to heat generated in the semiconductor chip are not different in the insulating material 30 and the buildup layer 38, an error due to thermal stress can be prevented. When the buildup layer 38 is stacked, the via holes are processed to form second vias 40 electrically connected to the first vias 36. The process of forming the second via 40 may be the same as the process of forming the first via 36 described above. That is, to form the via hole by drilling the build-up layer 38 to expose the land portion of the first via 36 and plating the inner surface of the via hole to electrically connect the first via 36 and the second via 40 to each other. do.

5 repeats the above buildup process when stacking a plurality of buildup layers 38 as an example of a buildup process of stacking two buildup layers 38. As described above, the buildup process is performed a plurality of times as necessary according to the design of the semiconductor package. Accordingly, a plurality of buildup layers 38 are stacked, and the second via 40 is formed in each buildup layer 38. Is processed to implement the electrical connection passage. In the present embodiment, the bump lands 41 for forming the solder resist 39 in the outermost buildup layer 38 and for joining the conductive bumps 42 such as solder balls. ) And a contact point for electrical connection between the semiconductor package and the external device. The bump lands 41 are electrically connected to the second vias 40.

The conductive bumps 42 are for electrical connection between the semiconductor package and the external device and are electrically connected to the second vias 40 on the surface of the buildup layer 38. The conductive bumps 42 may be formed by adhering conductive bumps 42 such as solder balls to the bump lands 41.

6 is a cross-sectional view of a semiconductor package according to a third exemplary embodiment of the present invention. Referring to FIG. 6, a through electrode 12, a flip chip bonding 13, a heat sink 20, a bottom surface 21, and a first surface of the semiconductor package may be described. The mounting space 23, the second mounting space 25, the first semiconductor chip 26, the first connection terminal 27, the second semiconductor chip 28, the second connection terminal 29, and the insulating material 30. A build up layer 38, a first via 36, a second via 40, a solder resist 39, a bump land 41, and a bump 42 are shown.

According to the present exemplary embodiment, one surface of the first semiconductor chip 26 having the first connection terminal 27 formed on one surface is bonded to one surface of the heat sink 20, and one side of the through electrode 12 and the first connection terminal ( The flip chip bonding 13 is performed to make an electrical connection with the 27. That is, the first semiconductor chip 26 having the through electrode 12 formed at a position corresponding to the first connection terminal 27 of the first semiconductor chip 26 and having the first connection terminal 27 formed on one surface thereof. One surface of is bonded to one surface of the heat sink 20 having the through electrode 12 corresponding to the first connection terminal 27, and one side of the through electrode 12 and the first connection terminal 27 are flip chip bonded ( 13) to be electrically connected.

The fact that the through electrode 12 is formed at a position corresponding to the first connection terminal 27 of the first semiconductor chip 26 means that the first semiconductor chip 26 has the first connection terminal 27 formed on one surface thereof. When one surface is bonded to one surface of the heat sink 20, the through electrode 12 is connected such that the first connection terminal 27 for electrical connection with the outside of the first semiconductor chip 26 is communicated through the through electrode 12. It means that the heat sink 20 is formed. As such, the first connection terminal 27 of the first semiconductor chip 26 may implement electrical connection through the through electrode 12.

The first connection terminal 27 is formed on one surface of the first semiconductor chip 26, and the through electrode 12 is formed at a position corresponding to the first connection terminal 27 on the heat sink 20 so that the first connection terminal 27 is formed. When one surface of the semiconductor chip 26 and one surface of the heat sink 20 are bonded to each other, the first connection terminal 27 and one side of the through electrode 12 may be electrically connected by flip chip bonding 13. Can be connected. In the flip chip bonding 13 process, the bumps are attached to the first connection terminals 27 formed on one surface of the first semiconductor chip 26, the bumps are applied after the reflow flux is applied. After mounting on one side of the penetrating electrode 12, the bump is melted by reflow heating to electrically connect the first connection terminal 27 of the first semiconductor chip to one side of the penetrating electrode 12.

Since other components are the same as in the above-described second embodiment, description thereof will be omitted.

7 is a cross-sectional view of a semiconductor package in accordance with a fourth embodiment of the present invention. Referring to FIG. 7, the through electrode 12, the heat sink 20, the first mounting space 23, the second mounting space 25, the first semiconductor chip 26, the first connection terminal 27, and the first 2 semiconductor chip 28, second connection terminal 29, insulating material 30, build-up layer 38, first via 36, third via 37, second via 40, solder resist 39, bump land 41, and bump 42 are shown.

In this embodiment, the via and the circuit pattern are formed by using the insulating material 30 encapsulating the first semiconductor chip 26 as one substrate. That is, the other surface of the first semiconductor chip 26 is disposed on one surface of the heat sink 20 so that the other surface of the first semiconductor chip 26 on which the first connection terminal 27 is not formed and one surface of the heat sink 20 face each other. Bonding, coating the insulating material 30 on one surface of the heat sink 20 to encapsulate the first semiconductor chip 26, and then drilling the insulating material 30 encapsulating the first semiconductor chip 26. A third via 37 electrically connected to one side of the through electrode 12 and the first connection terminal 27 is formed.

The process of forming the third via 37 drills the via hole by drilling the insulating material 30 so that one side of the through electrode 12 is exposed, and exposes the first connection terminal 27 of the first semiconductor chip 26. Drill the via hole by drilling the insulating material 30 as much as possible. When the via hole is drilled, plating is performed on the inner surface of the via hole. The plating may be performed by applying a process such as Cu sputtering or conductive paste filling to form a plating layer. The third via 37 allows the first connection terminal 27 of the first semiconductor chip 26 to be electrically connected to the outside through the through electrode 12.

Other components are the same as the above-described second embodiment or the third embodiment, and a description thereof will be omitted.

Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

As described above, according to an exemplary embodiment of the present invention, the semiconductor chip may be directly bonded to a heat sink to shorten a thermal path, thereby enhancing heat dissipation efficiency of the semiconductor package, and stacking a plurality of semiconductor chips vertically to improve package size. Can be shrunk.

In addition, build-up technology can be applied to improve the reliability of the connection.

Claims (25)

Bonding a first semiconductor chip having a first connection terminal on one surface to one surface of a heat sink on which a through electrode is formed; Electrically connecting one side of the through electrode and the first connection terminal; Encapsulating the first semiconductor chip by coating an insulating material on one surface of the heat sink; Bonding the other surface of the second semiconductor chip having the second connection terminal to one surface to the other surface of the heat sink; Encapsulating the second semiconductor chip by coating an insulating material on the other surface of the heat sink; Coated on the other side of the heat sink Perforating the insulating material to form a first via electrically connected to the other side of the through electrode and the second connection terminal. The method of claim 1, After forming the first via, And a build-up step of stacking a build-up layer on the other surface of the heat sink coated with the insulating material, and forming a second via electrically connected to the first via by drilling the build-up layer. The method of claim 2, The build-up layer is stacked in plurality, the second via is a semiconductor package manufacturing method, characterized in that formed in the plurality of the build-up layer, respectively. The method of claim 2, After the buildup phase above, And forming a conductive bump electrically connected to the second via on the surface of the build-up layer. The method of claim 1, Bonding to one surface of the heat sink or bonding to the other surface of the heat sink is performed by interposing an adhesive between the heat sink and the first semiconductor chip or the second semiconductor chip, respectively, the first semiconductor chip or the second semiconductor. And attaching a chip to the heat sink. The method of claim 1, The electrically connecting step, The method of manufacturing a semiconductor package, characterized in that performed by wire bonding (bonding) one side of the through electrode and the first connection terminal. The method of claim 1, The through electrode is formed to correspond to the first connection terminal, The electrically connecting step, The semiconductor package manufacturing method of claim 1, wherein one side of the through electrode and the first connection terminal are performed by flip chip bonding. The method of claim 1, Bonding to one surface of the heat sink, Bonding the other surface of the first semiconductor chip to one surface of the heat sink; The electrically connecting step, Perforating the insulating material to form a third via electrically connected to one side of the through electrode and the first connection terminal. The method of claim 1, The encapsulating the first semiconductor chip or the encapsulating the second semiconductor chip may be performed by applying a liquid resin to the heat sink to cover the first semiconductor chip or the second semiconductor chip and firing them. A semiconductor package manufacturing method comprising the step. The method of claim 1, Forming the first via, Drilling a via hole by drilling the insulating material to expose the other side of the through electrode; Drilling a via hole by drilling the insulating material to expose the second connection terminal; And And plating an inner surface of the via hole. The method of claim 1, A concave recessed first mounting space is formed on one surface of the heat sink, and the through electrode is formed on a bottom surface of the first mounting space. Bonding to one surface of the heat sink, And bonding the first semiconductor chip to a bottom surface of the first mounting space. The method of claim 11, Encapsulating the first semiconductor chip, And applying the insulating material to fill the first mounting space. The method of claim 1, A second mounting space recessed in the other surface of the heat sink is formed, the through electrode is formed on the bottom surface of the second mounting space, Bonding to the other surface of the heat sink, And bonding the other surface of the second semiconductor chip to the bottom surface of the second mounting space. The method of claim 13, Encapsulating the second semiconductor chip may include: And applying the insulating material to fill the second mounting space. A first semiconductor chip having a first connection terminal formed on one surface thereof; A heat dissipation plate having one side electrically connected to the first connection terminal, and one surface thereof bonded to the first semiconductor chip; A second semiconductor chip formed on one surface thereof and having the other surface bonded to the other surface of the heat sink; An insulating material stacked on the heat sink and encapsulating the first semiconductor chip and the second semiconductor chip; And Formed on the other surface of the heat sink And a first via penetrating the insulating material and electrically connected to the other side of the through electrode and the second connection terminal. The method of claim 15, A build-up layer laminated on the other surface of the heat sink to which the insulating material is applied; And And a second via penetrating the build-up layer and electrically connected to the first via. The method of claim 16, The build-up layer is stacked in plurality, and the second via is a plurality of semiconductor packages, characterized in that formed in plurality to be processed in each of the build-up layer and electrically connected to each other. The method of claim 16, And a conductive bump formed on a surface of the buildup layer and electrically connected to the second via. The method of claim 15, One side of the through electrode and the first connection terminal is a semiconductor package, characterized in that electrically connected by wire bonding. The method of claim 15, The through electrode is formed to correspond to the first connection terminal, And one side of the through electrode and the first connection terminal are electrically connected by flip chip bonding so as to face each other. The method of claim 15, The other surface of the first semiconductor chip is bonded to one surface of the heat sink, The semiconductor package further comprises a third via penetrating the insulating material formed on one surface of the heat sink and electrically connected to one side of the through electrode and the first connection terminal. The method of claim 15, One surface of the heat sink is recessedly formed with a first mounting space, the through electrode is formed on the bottom surface of the first mounting space And the first semiconductor chip is bonded to a bottom surface of the first mounting space. The method of claim 22, The insulating material is a semiconductor package, characterized in that for encapsulating the first semiconductor chip by filling the first mounting space. The method of claim 15, A second mounting space recessed in the other surface of the heat sink is formed, the through electrode is formed on the bottom surface of the second mounting space The other surface of the second semiconductor chip is bonded to the bottom surface of the second mounting space, the semiconductor package. The method of claim 24, The insulating material is a semiconductor package, characterized in that for encapsulating the second semiconductor chip by filling the second mounting space.

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