KR100843883B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device, the method comprising: forming a lower separator pattern exposing a bit line contact region on an active region on an upper portion of a semiconductor substrate to reduce leakage current between a source / drain junction region; Forming a conductive layer over the surface, forming a trench by etching the conductive layer, the lower separator pattern, and the semiconductor substrate on the device isolation region using a device isolation mask, and filling the trench to form a device isolation layer; Forming a recess by etching the gate predetermined region in the region, and forming a gate on the recess, thereby preventing leakage current between the source / drain junction region and reducing the depth of the source / drain junction region. Even if it is deep enough, it is not affected by the adjacent gate and thus the threshold voltage change can be prevented.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a layout showing a semiconductor device according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

3A to 3J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

5 is a view for explaining the effect of the method of manufacturing a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a short channel effect and an adjacent gate are formed even when a source / drain junction region is deeply formed by fabricating a silicon-on-insulator (SOI) substrate to form a depletion channel region The present invention relates to a method for manufacturing a semiconductor device capable of minimizing the influence.

In general, as the channel length of the cell transistor decreases, the ion concentration of the cell channel is increased to meet the threshold voltage of the cell transistor, and as a result, the electric field of the source / drain region is increased, thereby increasing the leakage current. Falls out. Therefore, the following semiconductor device structure has been proposed in order to increase the channel length of the cell transistor.

FIG. 1 is a layout diagram illustrating a semiconductor device according to the related art, and shows an active region 14 and a recess 16 defined by an isolation layer 12.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and FIG. 2A is a cross sectional view taken along line AA ′ of FIG. 1, and FIGS. 2B and 2C are cross sectional views taken along line BB ′ of FIG. 1. It is shown.

Referring to FIG. 2A, a pad isolation layer and a pad nitride layer are formed on the semiconductor substrate 10, and the pad oxide layer, the pad nitride layer, and the semiconductor substrate 10 having a predetermined depth are etched using an element isolation mask to form a trench for device isolation. To form.

Next, an insulating film filling the device isolation trench is formed, and a planarization process is performed until the pad nitride film is exposed.

Next, the pad nitride layer and the pad oxide layer are removed to form an isolation layer 12 to define an active region 14.

Referring to FIG. 2B, a recess 16 is formed by etching the semiconductor substrate 10 in the gate predetermined region using a recess mask.

2C, a source / drain junction region 18 is formed by performing a source / drain ion implantation process on the semiconductor substrate 10.

However, when the junction depth is deepened when the source / drain junction region 18 is formed, the leakage current between the source / drain junction region 18 is rapidly increased in the channel region formed under the recess 16, and the junction depth is increased. If it is made shallower, there is a problem in that the threshold voltage Vt changes due to an increase in the junction leakage current or a large influence of the voltage applied to the adjacent gate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing leakage current between source / drain junction regions and preventing a change in threshold voltage due to adjacent gate influence.

Method for manufacturing a semiconductor device according to the invention,
Forming a lower separator pattern on the semiconductor substrate to expose a predetermined region of the bit line contact on the active region;
Forming a conductive layer over the entire surface,
Etching the conductive layer, the lower separator pattern, and the semiconductor substrate on the device isolation region using a device isolation mask to form a trench, and filling the trench to form a device isolation layer;
Etching a gate predetermined region in the active region to form a recess;

Forming a gate on the recess

delete

delete

delete

delete

Characterized in that it comprises a.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A to 3J are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 3A, a lower separator 102 is formed on the semiconductor substrate 100.

In this case, the lower separator 102 preferably forms a silicon oxide (SiO 2) film at a thickness of 1 to 100 nm, and the lower separator 102 may be formed at 02, H 20, H 2, 03 and at a temperature of 200 to 1000 ° C. It is preferable to carry out in an atmosphere containing a gas selected from a combination of these.

Referring to FIG. 3B, the lower separator 102 of the bit line contact region is etched to form a lower separator pattern 102a.

In this case, the etching process of the lower separator 102 is preferably performed by a plasma etching method using a gas selected from CxFyHz, O2, HCl, Ar, He, and a combination thereof. Where x, y, and z are integers

Here, the lower isolation layer pattern 102a exposes a bit line contact predetermined region, which grows the conductive layer 104 to be formed in a subsequent process, and forms a bit line contact plug and a body of the semiconductor substrate 100. Body).

Referring to FIG. 3C, the conductive layer 104 is formed on the lower separator pattern 102a by using the semiconductor substrate 100 exposed by the lower separator pattern 102a as a seed layer.

In this case, the conductive layer 104 preferably forms an epitaxial silicon layer with a thickness of 10 to 500 nm, and the epitaxial silicon layer forming process is performed at a temperature range of 500 to 1000 ° C., such as HCl, SiH 4, SiH 2, Cl 2, It is preferable to perform the selective epitaxial growth (SEG) method using the selected gas among H 2 and a combination thereof.

Referring to FIG. 3D, a pad nitride film 106 is formed on the conductive layer 104.

In this case, a pad oxide layer may be formed before the pad nitride layer 106 is formed to suppress stress between the semiconductor substrate 100 and the pad nitride layer 106.

Referring to FIG. 3E, the pad nitride layer 106, the conductive layer 104, and the semiconductor substrate 100 having a predetermined depth are etched by a photolithography process using a device isolation mask to form a device isolation trench 108. do.

Next, a sidewall oxide film is formed on the sidewalls and bottom of the device isolation trench 108.

Referring to FIG. 3F, a device isolation insulating layer 110 is formed on the pad nitride layer 106 including the device isolation trench 108.

In this case, the isolation layer 110 is preferably formed of a silicon oxide (SiO 2) film.

Next, the device isolation insulating film 110 is planarized until the pad nitride film 106 is exposed.

Referring to FIG. 3G, the pad nitride layer 106 is removed to form an isolation layer 112 that defines an active region.

In this case, the pad nitride layer 106 may be removed by a wet etching method using heated phosphoric acid (H 3 PO 4).

Referring to FIG. 3H, the recess 114 is formed by etching the conductive layer 104 a predetermined depth by a photolithography process using a recess mask.

In this case, the depth of the recess 114 may be formed such that the vertical distance d1 between the bottom of the recess 114 and the lower separator pattern 102a is spaced apart by 10 to 100 nm.

Referring to FIG. 3I, a gate oxide layer 116 is formed over the entire surface including the recess 114.

In this case, the gate oxide film 116 preferably has a thickness of 1 to 20 nm in any one or two or more layers selected from a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a silicon nitride film, and a combination thereof.

As shown in FIG. 3J, the gate oxide layer 116 is formed on the sidewall of the recess 114 because the silicon (Si) crystal lattice plane of the sidewall of the recess 114 and the bottom surface thereof are different from each other. The gate oxide film 116 has a thickness of 0.5 to 2 times that of the gate oxide film 116 formed on the bottom surface.

delete

delete

delete

delete

Next, a gate polysilicon layer 122, a gate metal layer 124, and a gate hard mask layer 126 are formed on the gate oxide layer 116.

In this case, the gate polysilicon layer 122 is preferably formed by chemical vapor deposition using polysilicon doped using any one selected from phosphorus (Ph) and boron (B), the gate metal layer 124 is It is preferable to form using any one selected from Ti, TiN, W, Al, Cu, WSix and combinations thereof.

Next, the gate hard mask layer 126, the gate metal layer 124, and the gate polysilicon layer 122 are etched by a photolithography process using a gate mask (not shown) to complete the gate 128.

Next, the gate spacer 130 is formed on the sidewall of the gate 128. Next, a source / drain ion implantation process using the gate 128 and the gate spacer 130 as a mask is performed to form a source / drain junction region 118 in the semiconductor substrate 100.
In this case, a lower portion of the source / drain junction region 118 formed under the storage electrode contact predetermined region is separated by the lower separator pattern 102a, and only an upper portion thereof is used. In this state, when the back bias voltage Vbb is applied to the semiconductor substrate 100 under the bit line contact region, the channel region 120 under the recess (114 in FIG. 3H) is depleted. Thus, leakage current between the source / drain junction regions 118 is prevented.
In particular, if the vertical distance (d1 of 3h) between the recess 114 and the lower separator pattern 102a is adjusted, the channel region 120 may become a complete depletion region.
As a result, the depth of the source / drain junction region 118 can be formed deep, thereby reducing the change in the threshold voltage Vt due to the voltage applied to the adjacent gate. In addition, even if the voltage applied to the source / drain junction region 118 increases, the current value is not largely changed, thereby improving read / write operation characteristics of the device.

Next, an interlayer insulating film is formed over the entire surface, and the interlayer insulating film is planarized until the gate hard mask layer 126 is exposed.

Next, the interlayer insulating layer is etched by a photolithography process using a landing plug contact mask to form a landing plug contact hole.

Next, the landing plug 132 is formed by filling a conductive film in the landing plug contact hole.

Meanwhile, when it is necessary to reduce the line width CD of the semiconductor substrate 100 exposed when the lower separator pattern 102a is formed, the following process may be performed.

4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Referring to FIG. 4A, a lower separator is formed on the semiconductor substrate 200, and the lower separator of the bit line contact region is removed to form a lower separator pattern 202.

Referring to FIG. 4B, an insulating film 204 is formed on the semiconductor substrate 200 including the lower separator pattern 202.

Referring to FIG. 4C, an insulating layer pattern 204a is formed on sidewalls of the lower separator pattern 202 by performing an entire surface etching process on the insulating layer 204.

In this case, it can be seen that the line width CD to which the semiconductor substrate 200 is exposed by the insulating layer pattern 204a is reduced compared to FIG. 3B.

Referring to FIG. 4D, the conductive layer 206 is formed on the lower separator pattern 202 by using the exposed semiconductor substrate 200 as a seed layer.

5 is a view for explaining the effect of the method of manufacturing a semiconductor device according to the present invention, (i) is a plan view, (ii) is a cross-sectional view taken along the cutting line D-D '.

Referring to FIG. 5, when the device isolation trench is formed in the cell region C, the first and second device isolation trenches 108a and 108b having different depths may be formed.

Here, the first device isolation trench 108a is formed to the same depth as the prior art, and the second device isolation trench 108b is formed by the lower isolation pattern 102a to form the first device isolation trench 108a. Formed at a shallower depth.

That is, since the channel region between the source / drain junction region is depleted by the lower separator pattern 102a, the device isolation characteristic is improved even when the second device isolation trench 108b is formed to a shallow depth. do. In addition, the parasitic capacitance can be reduced as it acts as a silicon-on-insulator (SOI) channel region.

According to the present invention, a silicon-on-insulator (SOI) -type substrate is formed to form a depletion channel region to prevent leakage current between the source / drain junction regions, and even if the depth of the source / drain junction region is sufficiently deep, Since it is not affected by the gate, it provides an effect to prevent the threshold voltage change.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (15)

Forming a lower separator pattern on the semiconductor substrate to expose a bit line contact region on the active region; Forming a conductive layer over the entire surface; Etching the conductive layer, the lower separator pattern, and the semiconductor substrate on the device isolation region using a device isolation mask to form a trench, and filling the trench to form a device isolation layer; Etching a gate predetermined region in the active region to form a recess; And Forming a gate on the recess Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the forming of the lower separator pattern is Forming a lower separator with a silicon oxide (SiO 2) film having a thickness of 1 to 100 nm on the semiconductor substrate; And Etching the lower separator of the bit line contact region; Method of manufacturing a semiconductor device comprising a. The method of claim 2, wherein the forming of the lower separator is performed in an atmosphere containing a gas selected from 02, H20, H2, 03, and a combination thereof at a temperature of 200 ° C. to 1000 ° C. 4. The method of claim 2, wherein the lower separator etching process is performed by a plasma etching method using a gas selected from among CxFyHz, O 2, HCl, Ar, He, and a combination thereof. , y, z are integers) The method of claim 1, wherein the conductive layer forms an epitaxial silicon layer having a thickness of about 10 nm to about 500 nm. The method of claim 5, wherein the epitaxial silicon layer forming process is a selective epitaxial growth method using a gas selected from HCl, SiH4, SiH2, Cl2, H2, and combinations thereof in a temperature range of 500 ~ 1000 ℃ Method of manufacturing a semiconductor device, characterized in that carried out as. The method of claim 1, further comprising forming a pad nitride film on the conductive layer after the conductive layer forming step. 8. The method of claim 7, wherein the pad nitride film is removed after the device isolation film is formed. The method of claim 8, wherein the pad nitride film removing process is performed by a wet etching method using heated phosphoric acid (H 3 PO 4). The method of claim 1, wherein the recess is formed to have a depth at which a vertical distance between the bottom of the recess and the lower separator pattern is 10 to 100 nm apart. The method of claim 1, further comprising forming a gate oxide film after the recess forming step. 12. The gate oxide film of claim 11, wherein the gate oxide film is formed of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a silicon nitride film, or a combination of two or more thereof, having a thickness of 1 to 20 nm. Method of manufacturing a semiconductor device. The method of claim 1, wherein the gate is a stacked structure of a gate polysilicon layer, a gate metal layer, and a gate hard mask layer. The method of claim 13, wherein the gate polysilicon layer is formed by chemical vapor deposition using polysilicon doped using any one selected from phosphorus (Ph) and boron (B). . The method of claim 13, wherein the gate metal layer is formed using any one selected from Ti, TiN, W, Al, Cu, WSix, and a combination thereof.

Images