KR100825068B1 - RAM testing and troubleshooting system - Google Patents

Abstract

According to the present invention, a RAM is tested with a test pattern automatically generated by adding a BIST (Built In Self Test) and BISR (Built In Self Repair) circuit in a device having a RAM, and a test result is that a bit The present invention relates to a RAM test and troubleshooting system that repairs a normal bit if present. In the RAM test and troubleshooting system, a RAM comprising a main ram and a redundancy cell, and a fault address ( an internal register for storing a fail address and a good redundancy address, and a system clock and a test pattern generated when the device is powered on, and writing the test pattern to RAM using the system clock. Reads back through the internal comparator and compares it to the test pattern, which compares the fail address and normal redundant address. It is (good redundancy address) first operating unit including a processor for failure to be stored in the internal register; And a RAM address counter for generating an address for accessing a ram cell when a signal related to a RAM access is input to the device input, and comparing the RAM address counter with a failure address to compare with a failure address. It characterized by consisting of a second operating unit composed of a comparator.

RAM, automatic test, automatic troubleshooting, BIST, BISR, program

Description

RAM testing and troubleshooting system {BUILT IN SELF TEST AND BUILT IN SELF REPAIR SYSTEM}

1 is a view for explaining a conventional RAM test and troubleshooting system,

2 is a view for explaining the concept of the present invention,

3 is a view for explaining the data flow in the RAM test and troubleshooting system according to the present invention,

4 is a view for explaining the configuration of the RAM test and troubleshooting system according to the present invention.

*** Explanation of symbols on main parts of drawing ***

100: first operating unit

110: ram

120: internal register

130: fault handling unit

131: internal comparator

200: second operating unit

210: address counter

220: comparator

The present invention relates to a ram test and troubleshooting system.

In particular, the RAM is tested with a test pattern automatically generated by adding a BIST (Built In Self Test) and BISR (Built In Self Repair) circuit in a device equipped with RAM, and a test bit has a failure bit. RAM test and troubleshooting system that repairs normal bits.

FIG. 1 is a diagram illustrating a conventional ram test and a repair method. The accompanying drawings include a test pattern output apparatus 10 for outputting a test pattern, and a test pattern output apparatus ( 10) compares the display driver IC 20 having the RAM 21 inputted and recorded with the display driver IC 20 with data read from the RAM 21 and whether they match the write pattern, and if the result of the comparison matches, If it is determined that the bit does not match and the fault bit is determined to be a fault bit and outputs the result, the fault bit is scanned from the fault bit detection device 30 by a laser beam to physically detect the fault bit. It consists of a fault handling device 40 that melts and connects a spare cell to the fault bit.

Referring to the operation of the RAM failure test and processing system configured as described above are as follows.

First, the test pattern output device 10 is connected to the input terminal of the display drive IC 20 having the RAM 21, the fault bit detection device 30 is connected to the output terminal, and the fault bit detection device 30 is connected. The fault handler 40 is connected.

After all the devices are connected as described above, the test pattern stored in advance in the test pattern output device 10 is recorded in the display drive IC 20.

Then, the data recorded in the RAM 21 is read through the failure bit detection device 30 connected to the output terminal of the display drive chassis 20.

The failure bit detection device 30 compares the read data with the previously stored write pattern data to determine whether they match, and if there is a mismatch, determines the bits of the non-matching part as the failure bits to the failure processing device 40. Output

Then, the failure processing apparatus 40 scans the laser beam to the corresponding bit of the RAM 21 to melt the corresponding bit, and connects an extra cell to the fault bit so that the RAM operates normally.

In the conventional RAM test and troubleshooting system as described above, a test pattern must be externally input, and a process of comparing an output and an expected pattern with a comparison circuit is necessary, so additional devices are required as well as RAM test time. There is a problem that it takes a lot.

In addition, the existing RAM test and troubleshooting system needs to connect spare cells that can be operated normally after fusing physically using expensive laser equipment. There is a problem that takes a lot of equipment costs.

The present invention has been made to solve the problems of the existing technology as described above, the object of the present invention is to automatically add a built-in self test (BIST) and Built In Self Repair (BISR) circuit in a device equipped with RAM The present invention provides a RAM test and fault handling system that tests a RAM with a test pattern generated by using a circuit and repairs a normal bit if a failure bit exists.

An embodiment of the present invention proposed to solve the above technical problem, in the RAM test and fault handling system, a RAM consisting of a main ram (Redundancy cell) and a failure address (fail) an internal register that stores an address and a good redundancy address, and a system clock and a test pattern generated when the device is powered on, and writes the test pattern to RAM using the system clock, and then writes the recorded test pattern. A first operating unit including a fault handling unit which reads back through an internal comparator and compares it with a test pattern and stores a failure address and a good redundancy address in the internal register as a result of the comparison; And a RAM address counter for generating an address for accessing a ram cell when a signal related to a RAM access is input to the device input, and comparing the RAM address counter with a failure address to compare with a failure address. It characterized by consisting of a second operating unit composed of a comparator.

According to another embodiment of the present invention, in the RAM test and the fault handling method, (1) the fault handling unit is set to a high state with an automatic test on signal (BIST On) while the reset is released when the device power is applied. Generating a signal of a level and internally generating a system clock; (2) The fault processor, when the system clock and the automatic test on signal (BIST On), the write signal and RAM address (bist_addr) and RAM write generated by the system clock (System clock) Outputting data to RAM; (3) a fault processing unit, outputting a read signal generated by the system clock to the RAM; (4) a fault processing unit receiving data read_out_data read back from the RAM as an input; (5) the failure processing unit comparing write data with read data read_out_data through a comparator in a circuit; (6) the fault processor passes the write data and the read data if the read data is the same, and if the write error is different, outputs the fault address of the read RAM to an internal register, and stores the internal register according to the system clock; (7) When all the main RAM cells and whether or not the completion of the failure test for the main ram cell and the completion of the check of the main ram cell and redundancy circuit, the automatic test on signal (BIST On) generates a low level signal and outputs process; (8) an address counter comparing the fail address received from the internal register while increasing or decreasing a ram access address when a write signal and data are input to the device input; And (9) an address counter, if the comparison value is different, a process of outputting a real ram address of which the value is continuously increased or decreased to a ram to read / write to the ram address; Characterized in that consisting of.

Hereinafter, a RAM test and a failure handling system will be described in detail with reference to the accompanying drawings.

RAM test and troubleshooting system is applied to the present invention is a ram test and troubleshooting system 400 is provided in the display driver Ishi 300 as shown in Figure 2, the display driver isi 300 When power is supplied to the RAM 110, the RAM 110 provided in the display driver Icy 300 diagnoses whether there is a fault bit, and if a fault bit is found, replaces the spare cell so that the RAM 110 performs normal operation.

The RAM test and troubleshooting system 400 operating as described above is composed of a first operating unit 100 and a second operating unit 200 as shown in FIG. 4.

The first operating unit 100 includes a RAM 110 including a main ram and a redundancy cell, an internal register storing a failure address and a good redundancy address. When the device is powered on, the system clock and the test pattern are generated, the test pattern is recorded in the RAM 110 using the system clock, and the read test pattern is read back through the internal comparator 131. Comparing with the test pattern, and the failure result (fail address) and the good redundancy address (good redundancy address) is composed of a failure processing unit 130 to be stored in the internal register (120).

The test pattern generated by the failure processor 130 is data to be written / read in the RAM 110, and is composed of a data combination of 1s and 0s that can alternately write 1s and 0s to a RAM bit cell. The test pattern generates pattern data according to the circuit configuration of the failure processing unit 130 after power is applied to the device.

The second operating unit 200 generates a RAM address counter 210 that generates an address for accessing a RAM cell when a signal related to a RAM access is input to the device input, and an address generated by the RAM address counter fails. The comparator 220 compares and replaces an address with a fail address.

The RAM address counter 210 is replaced with an address of a redundant cell that can replace the faulty cell address when a faulty cell and a faulty address are generated.

Referring to the operation of the RAM test and troubleshooting system configured as described above are as follows.

First, as shown in FIG. 3 and FIG. 4, the failure processing unit 130 is reset when the power is applied to the device, and the reset is released to a high state with the automatic test on signal BIST On. While generating a signal of the level (T1 interval in Figure 3) while generating a system clock (System clock) internally.

When the system clock and the automatic test on signal BIST are on, the fault processor 130 writes a RAM signal, a RAM address (bist_addr), and a RAM write generated by the system clock. The data is output to the RAM 110. In this case, the RAM write data is a high level value which is a test pattern automatically generated after power is applied to the device.

After the RAM write data is output to the RAM 110 as described above, the failure processor 130 outputs the read signal generated by the system clock to the RAM 110.

The failure processor 130 receives the data read_out_data read from the RAM as an input again, and writes data and read data re-entered through a comparator 131 provided in the circuit. Compare (read_out_data).

As a result of the comparison, if the write data and the read data are the same, the fault processor 130 passes, and if different, the fault address of the read RAM 110 is output to the internal register 120, and the internal register 120 is a system clock. Save the fault address accordingly.

The failure processing unit 130 checks the main ram cell and the redundancy cell when the failure test is completed for all the main ram cells and whether or not the cells. The signal BIST On generates and outputs a low level signal (T2 section in FIG. 3).

Meanwhile, the address counter 210 generates an address that can access a ram cell when a write signal and data are input to a device input, and increases or decreases the ram access address through a comparator 220. At the same time, it compares with a failure address received from the internal register 120.

If the comparison result is different, the comparator 220 allows the address counter 210 to output a real ram address, which has been continuously increased or decreased, to RAM. Read / write is done.

As a result of the comparison, if the comparison value is the same, the comparator 220 causes the address counter 210 to replace the address counter value with an address of a redundancy cell, thereby replacing the RAM with a real ram address. ram, 110).

The present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art, which are included in the spirit and scope of the present invention included in the appended claims.

The present invention having the configuration and operation and the preferred embodiment as described above has the effect of reducing the total time required for the RAM test by reducing the time loss (loss) required during the RAM test in the RAM test process.

In addition, the present invention allows the RAM cell that has failed as much as an additional redundant cell to be processed through a programmed circuit, rather than through hardware equipment such as a laser, to further process the faulty cell. It has the effect of reducing the loss of RAM bit defects in the overall yield of the device without cost.

Claims (7)

RAM testing and troubleshooting system, RAM consisting of main ram and redundancy cell, internal registers that store fault address and good redundancy address, system clock and test pattern when the device is powered on The test pattern is written to the RAM using a system clock, and then the read test pattern is read back through an internal comparator and compared with the test pattern. The result of the comparison is a failure address and a good redundancy. a first operating unit including a fault handling unit for storing an address) in the internal register; And When a signal related to a RAM access is input to the device input, a RAM address counter for generating an address for accessing a RAM cell and a comparison of the address generated in the RAM address counter with a fail address are replaced. A second operating unit composed of a comparator; RAM test and troubleshooting system, characterized in that consisting of. The test pattern generated by the fault processor, A RAM test and troubleshooting system comprising data combinations of 1s and 0s that can write 1s and 0s alternately to a RAM bit cell as data to be written to / read from RAM. The method of claim 2, wherein the test pattern, And a pattern data is generated according to the circuit configuration of the fault handling unit after power is applied to the device. The method of claim 1, wherein the RAM address counter, And a fault cell and a fault address are generated, the fault cell address is replaced with an address of a redundant cell that can be replaced. delete delete delete

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