KR100816563B1 - Manufacturing Method of Thin Film Transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor which can simplify the process of a normal stacked thin film transistor and improve its characteristics. In the thin film transistor having a normal stacked structure, a pixel electrode is formed by using a first mask on a glass substrate. Forming a source / drain electrode and an amorphous silicon layer using a second mask to selectively overlap with the pixel electrode, depositing a resin on the amorphous silicon layer, and then using a third mask Defining an active layer, and forming a gate electrode on the resin using a fourth mask.

Description

Manufacturing method of thin film transistor {A METHOD FOR MANUFACTURING THIN FILM TRANSISTOR}

1A to 1C are cross-sectional views illustrating a method of manufacturing a thin film transistor having a normal stacked structure, according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101: glass substrate 102a: pixel electrode

103a: source / drain electrode 104: n ⁺ amorphous silicon

105: amorphous silicon layer 106: resin

107a: gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor capable of simplifying a process and improving characteristics of a normal stacked thin film transistor.

Recently, with the development of new high-tech video devices such as high definition TVs (HDTVs), there is a demand for flat panel displays.                         

LCD is a representative technology of flat panel display and does not have problems such as low power and high speed which ELD (Electro Luminescence Display), VFD (Vacuum Fluorescence Display) and PDP (Plasma Display Panel) cannot solve.

These LCDs are divided into two types, passive and active. Active LCDs are controlled by active elements such as thin film transistors so that each pixel is controlled in terms of speed, viewing angle, and contrast. It is used as the best indicator for HDTV that requires excellent resolution of 1 million pixels or more. Accordingly, as the importance of TFTs is highlighted, R & D on them is intensifying.

Currently, research and development on TFTs, which are used as electrical switching elements for selective driving of pixel electrodes in LCDs, focus on improving the yield and productivity, and thus improving the structure of TFTs and improving the characteristics of amorphous or polycrystalline silicon. It is focused on ohmic contact resistance of electrodes and prevention of disconnection / short circuit. Of these, more research is being conducted on the technology of amorphous silicon TFT because of its large area, low cost, and mass productivity.

In general, there are two types of TFT structures: a coplanar type in which a source and a gate are in one plane, and a staggered type in a different plane. TFTs are mostly stacked.

Here, the stacked TFT has a bottom gate type called an invertede staggered under the source and drain and a top called normal staggered with the gate above the source and drain. It can be distinguished into a top gate type.

Among these, the bottom gate type cannot use a single layer of aluminum due to the problem of Hilllock, but the top gate type can use a single layer of aluminum, which has the advantage of wider metal selection. In the case of the bottom gate type, the thickness cannot be increased because of the problem due to the step difference, but the top gate type can increase the thickness because there is no step problem. Therefore, the line width can be reduced and high definition is possible, and it is easy to apply to a big screen.

In addition, since the top gate type can reduce the number of masks compared to the bottom gate type, the manufacturing cost can be reduced, and the damage of the amorphous silicon is reduced because the thickness of the amorphous silicon is not necessary because channel damage is not required. (leakage current) can be reduced.

However, the top gate type, called a normal stack type, deposits amorphous silicon and then deposits a silicon nitride film (SiN _X ) used as an insulating film. At this time, the deposition conditions of the silicon nitride film cause defects in the amorphous silicon film below.

That is, the TFT characteristics are deteriorated because the silicon is damaged after deposition of the gate insulating film by the CVD equipment in the process after the amorphous silicon.

Accordingly, the present invention has been made to solve the above problems of the prior art, using a resin as a gate insulating film (regin) to simplify the process of the top gate type called the normal stack type, and to improve the characteristics of a thin film transistor The purpose is to provide a method of manufacturing.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a pixel electrode on a glass substrate using a first mask in a thin film transistor having a normal stacked structure, and selectively overlapping the pixel electrode. Forming a source / drain electrode and an amorphous silicon layer using a second mask, depositing a resin on the amorphous silicon layer, and then defining an active layer using a third mask; And forming a gate electrode using the fourth mask.

In addition, the gate electrode formed on the resin is preferably characterized in that the deposition at a low temperature.

The gate electrode may be selected from any one of Al, AlNd, Mo, and Cr, and may be used by laminating Mo above and below.

Hereinafter, a method of manufacturing a thin film transistor of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a thin film transistor having a normal stacked structure according to an embodiment of the present invention.

In the method of manufacturing a thin film transistor having a normal stacked structure according to an embodiment of the present invention, as illustrated in FIG. 1A, a transparent electrode layer 102 is deposited on a glass substrate 101, and an etching process using a first mask is performed. Through the pixel electrode 102a is formed. In this case, the transparent electrode layer 102 uses ITO or IZO.

Then, a source / drain electrode metal film 103 is deposited on the entire surface of the substrate 101 including the pixel electrode 102a, and the n ⁺ amorphous silicon layer 104 is disposed on the source / drain electrode metal film 103. ), And then the source / drain electrode 103a is formed by patterning the source / drain electrode metal film 103 and the n ⁺ amorphous silicon layer 104 through an etching process using a second mask. In this case, any one of the source / drain electrodes 103a is connected to overlap the pixel electrode 102a.

Subsequently, as shown in FIG. 1B, an amorphous silicon layer 105 is deposited on the n ⁺ amorphous silicon layer 104, and a resin 106 is deposited on the amorphous silicon layer 105. The active layer is defined by patterning the amorphous silicon layer 105 and the resin 106 through an etching process using a third mask.

Next, as shown in FIG. 1C, the gate electrode metal film 107 is deposited at a low temperature on the resin 106 where the active layer is defined, and selectively patterned through an etching process using a fourth mask to form the gate electrode. To form. At this time, the gate electrode metal film 107 is selected from any one of Al, AlNd, Mo, Cr, and is used by laminating Mo on the upper and lower portions.

Here, when the hard bake temperature is 130 ° C. or more during the development of the resin 106, the resin properties change, and thus, it is difficult to use the insulating film while having a good dielectric constant. However, the normal stack type is effective because the process temperature is low later on.

As described above, according to the method of manufacturing the thin film transistor of the present invention, since the resin having good dielectric properties is used in the normal stack type, the damage to amorphous silicon when the gate insulating film is deposited by CVD can be eliminated, thereby improving the characteristics. have.

In addition, the number of mask processes can be reduced compared to the inverse stack type, and manufacturing cost can be reduced, and the use of resin can simplify the process because an insulating film deposition process and an etching process are unnecessary.

Claims (3)

Forming a pixel electrode on the glass substrate using a first mask; Forming a source / drain electrode and an n ⁺ amorphous silicon layer using a second mask to selectively overlap with the pixel electrode; After depositing an amorphous silicon layer and a resin on the n ⁺ amorphous silicon layer, defining an active layer using a third mask; And And forming a gate electrode on the resin by using a fourth mask. The method of claim 1, The gate electrode formed on the resin is a thin film transistor manufacturing method characterized in that the low temperature deposition at a low temperature of 130 ℃ or less. The method of claim 1, The gate electrode may be any one selected from Al, AlNd, Mo, and Cr, and Mo may be stacked on top of each other to use the thin film transistor.

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