KR100808592B1 - Delay lock loop circuit - Google Patents

Abstract

The present invention relates to a delay locked loop circuit, wherein a second delay part for additionally delaying the first and second clock signals output from the first delay part corresponding to a test mode signal is placed in front of the duty error adjuster, thereby providing an additional delay. This has the effect of providing a delayed loop circuit that can be tested for low frequencies by increasing the clock period without circuitry and control circuitry.

Description

A circuit for delay locked loop

1 is a block diagram of a delay locked loop circuit according to an embodiment of the prior art.

FIG. 2 is a block diagram illustrating a configuration and an operation of a first delay line of FIG. 1. FIG.

3 is a block diagram of a delay locked loop circuit according to an embodiment of the present invention.

4 is a block diagram illustrating a configuration and an operation of a second delay unit of FIG. 3.

FIELD OF THE INVENTION The present invention relates to delay locked loop circuits and, more particularly, to delay locked loop circuits that support low frequency testing.

In general, a delay locked loop (DLL) circuit is a circuit for delaying an internal clock of a synchronous memory using a clock in a semiconductor memory device to match an external clock without an error. That is, when an external clock is used internally, skew occurs between an external clock and an internal clock or an external clock and data, and a DLL circuit is used to reduce such skew.

As shown in FIG. 1, the conventional DLL circuit includes a buffer 110, a first delay unit 120, a duty error adjuster 130, a first comparison signal generator 140, and a second comparison signal generator. And 150.

Here, the first delay unit 120 includes the first and second delay lines 122 and 124 and delays the clock input signal RCLK input from the buffer 110.

In addition, the first comparison signal generator 140 includes a first delay model unit 142 and a first phase detector 144, and a delay amount of the clock input signal RCLK to be delayed in the first delay unit 120. In order to control the first comparison signal CON1 is output.

In addition, the second comparison signal generator 150 includes a second delay model unit 152 and a second phase detector 154 and a delay amount of the clock input signal RCLK to be delayed in the first delay unit 120. The second comparison signal CON2 is output to control the control.

The DLL circuit of FIG. 1 operates as follows.

Initial operation, the first loop, the first delay model by the external clock signal CLK is activated at the edge of the clock through the buffer 110 to bypass the first delay line 122 and the duty error adjuster 130 The first compensation clock signal ICLK1 is generated by compensating the time difference between the internal clocks through the unit 142, and the first phase detector 144 generates the first compensation clock signal ICLK1 and the external clock signal CLK. The phases are compared to generate a first comparison signal CON1 for a delay amount to be delayed in the first delay line 122.

Next, in the second loop, independent of the first loop, an external clock signal CLK is activated at the edge of the clock through the buffer 110 to bypass the second delay line 124 and the duty error adjuster 130. By compensating for the time difference between the internal clock via the second delay model unit 152 to generate a second compensation clock signal (ICLK2), the second phase detector 154 and the second compensation clock signal (ICKL2) and the external The phase of the clock signal CLK is compared to generate a second comparison signal CON2 for a delay amount to be delayed in the second delay line 124.

As such, when the locking process of all the clocks of the first delay unit 120 is completed in the second loop, the first clock signal CLK1 and the first clock signal output from the first delay line 122 and the second delay line 124 are completed. The two clock signals CLK2 coincide with rising edges, while their duty ratios are opposite to each other.

Afterwards, the duty error adjuster 130 performs a phase mixing operation on the up edge and the down edge of the first clock signal CLK1 and the second clock signal CLK2, so that the first mixed clock has a duty ratio of exactly 50%. The signal CLK_OUT, that is, the internal clock is obtained.

As described above, in the conventional DLL circuit, after each delay line independently locks, the rising edges of the first clock signal CLK1 and the second clock signal CLK2 coincide with each other when the duty error correction starts. It is in a state. Therefore, the second delay model unit 152 and the second phase detector 154 present in the second feedback loop are both turned off, and instead, the first comparison signal CON1 output from the first phase detector 144 is used. ) To control the first and second delay lines 122 and 124.

FIG. 2 is a block diagram illustrating a configuration and operation of the first delay line 122 of FIG. 1.

Referring to FIG. 2, the first delay line 122 includes an upper coarse delay line (UCDL) and a lower coarse delay line formed of a plurality of unit delay cells (UDCs). line: LCDL) consists of a dual course delay line connected to a fine delay unit (FDU).

Looking at the operation of the first delay line 122, the clock input signal (RCLK) input from the buffer 120 is fast locking through the coarse delay lines (UCDL, DCDL), the reference clock to some extent After the feedback clock is approaching, fine tuning of the fine delay unit (FDU) is used to reduce the underlying jitter.

That is, the upper coarse delay line UCDL and the lower coarse delay line LCDL receive the clock input signal RCLK output from the buffer 210 and respectively delay the first and second intermediate clock signals IN1. , IN2) to the fine delay unit (FDU). Thereafter, the fine delay unit FDU mixes the first and second intermediate clock signals IN1 and IN2 output from the respective coarse delay lines UCDL and LCDL according to the weight K, and thereby the first clock signal CLK1. )

As described above, in the conventional DLL circuit, a delayable maximum delay time and a minimum delay time, that is, a range of the highest frequency and the lowest frequency at which the DLL circuit can normally operate synchronously may be set in each of the delay lines 122, It is determined by the minimum delay time and the maximum delay time that can be delayed in 124).

For example, assuming that the error for the fine delay unit (FDU) can be compensated, the total delay amount is equal to the delay amount due to each coarse delay line, which is equal to the clock period tCK of low frequency operation.

However, since the semiconductor memory device operates from a low frequency to a high frequency in nature, it should be able to cope with a situation in which the clock period tCK needs to be varied. This requires additional control circuitry to add unit delay cells (UDCs) to the first and second delay lines 122 and 124 and to control normal operation for each clock period tCK under various circumstances. There is a problem that the complexity and area are increased, resulting in additional effort, time, and cost.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of driving a normal DLL circuit in response to a variable external clock. More specifically, it provides a delay locked loop circuit capable of low frequency testing by increasing the clock period corresponding to the test mode.

In order to achieve the above object, a delay locked loop circuit for delaying an internal clock signal to coincide with an external clock signal of the present invention receives a clock signal activated at an edge of the external clock signal and is determined by a first comparison signal. A first delay line delaying time and outputting a first clock signal; A first additional delay unit configured to further delay the first clock signal corresponding to a test mode signal to output a second clock signal; And a first comparison signal generator configured to compensate for a time difference between the second clock signal and the internal clock and to generate the first comparison signal for adjusting the delay time of the first delay line by comparing with the external clock signal. A first loop means comprising;

A second delay line receiving the clock signal and outputting a third clock signal by delaying and inverting a predetermined time by a second comparison signal; A second additional delay unit configured to further delay the third clock signal corresponding to a test mode signal to output a fourth clock signal; And generating a second comparison signal for delaying a fourth clock signal to have the same delay as a pass through which the second clock signal passes, and adjusting the delay time of the second delay line in comparison with the external clock signal. A second loop means comprising a comparison signal generator; And a duty error adjuster configured to adjust an duty of the second clock signal output from the first loop means and the fourth clock signal output from the second loop means to output an internal clock that matches the external clock signal. Characterized in that it comprises a.

The first and second additional delay units may be located at the front end of the duty error adjuster.

When the test mode signal is disabled, the first additional delay unit bypasses the first clock signal input from the first delay line to the duty error adjusting unit, and the test mode signal is enabled. In this case, the first clock signal input from the first delay line is additionally delayed and transferred to the duty error controller.

Similarly, when the test mode signal is disabled, the second additional delay unit bypasses the third clock signal input from the second delay line to the duty error adjusting unit, and the test mode signal is enabled. In this case, the third clock signal input from the second delay line is additionally delayed and transferred to the duty error controller.

Preferably, the first additional delay unit comprises: a first inverter for inverting the test mode signal; A first NAND gate configured to NAND-couple the test mode signal inverted by the first inverter and the first clock signal input from the first delay line; A first additional delay line for further delaying the first clock signal input from the first delay line corresponding to the test mode signal; A second NAND gate NAND combining the first clock signal delayed in the first additional delay line and the test mode signal; And a third NAND gate outputting the second clock signal by NAND combining the output signal of the first NAND gate and the output signal of the second NAND gate again.

Here, the first additional delay line is configured by connecting a unit delay cell consisting of two NAND gates in a predetermined number in series.

Preferably, the second additional delay unit comprises: a second inverter for inverting the test mode signal; A fourth NAND gate configured to receive and NAND couple the test mode signal inverted by the second inverter and the third clock signal output from the second delay line; A second additional delay line for further delaying the third clock signal input from the second delay line corresponding to the test mode signal; A fifth NAND gate NAND combining the third clock signal and the test mode signal delayed in the second additional delay line; And a sixth NAND gate outputting the fourth clock signal by NAND combining the output signal of the fourth NAND gate and the output signal of the fifth NAND gate again.

The second additional delay line may be configured by connecting a predetermined number of unit delay cells consisting of two NAND gates in series.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a delay locked loop circuit according to an embodiment of the present invention.

As shown in FIG. 3, a DLL circuit according to an embodiment of the present invention may include a buffer 210, a first delay unit 220, a duty error adjuster 230, a first comparison signal generator 240, The second comparison signal generator 250 and the second delay unit 260 are included.

The buffer 210 receives the external clock signal CLK and generates a clock input signal RCLK that is activated at the edge of the clock.

The first delay unit 220 uses the first comparison signal CON1 output from the first comparison signal generator 240 and the second comparison signal CON2 output from the second comparison signal generator 250. As a result, the clock input signals RCLK input from the buffer 210 are delayed for each predetermined time. To this end, the first delay line 222 and the second delay line 224 are included.

The first delay line 222 delays the clock input signal RCLK by a predetermined time by using the first comparison signal CON1 output from the first comparison signal generator 240 to receive the first clock signal CLK1. Create

The second delay line 224 delays and inverts the clock input signal RCLK by a predetermined time using the second comparison signal CON2 output from the second comparison signal generator 250 to invert the second clock signal CLK2. )

The second delay unit 260 further delays the first and second clock signals CLK1 and CLK2 output from the first delay unit 220 in correspondence with the test mode signal TM, so that the duty error adjuster 230 By increasing the delay time, the clock cycle (tCK) that the DLL circuit can handle can be increased to prepare for a low frequency test environment.

The duty error adjuster 230 receives the first additional delayed clock signal CLKD1 and the second additional delayed clock signal CLKD2 output from the second delay unit 260, and receives the first mixed clock signal CLK_OUT1 and The second mixed clock signal CLK2 'is generated, and the first mixed clock signal CLK_OUT1 and the second mixed clock signal CLK2' have their edges at the falling edge and the second clock signal CLK1, respectively. The signal is moved between the falling edges of the clock signal CLK2.

The first comparison signal generator 240 generates the first comparison signal CON1 by comparing the external clock signal CLK with the first compensation clock signal ICLK1. To this end, the first delay model unit 242 and the first phase detector 244 is included.

The first delay model unit 242 receives the first mixed clock signal CLK_OUT from the duty error adjuster 230 and compensates for a time difference between an externally applied clock and an actual internal clock. ICLK1).

The first phase detector 244 receives the external clock signal CLK and generates a first comparison signal CON1 by comparing it with the first compensation clock signal ICLK1 output from the first delay model unit 242. .

The second comparison signal generator 250 generates the second comparison signal CON2 by comparing the external clock signal CLK with the second compensation clock signal ICLK2. To this end, the second delay model unit 252 and the second phase detector 254 is included.

The second delay model unit 252 receives the second mixed clock signal CLK2 'from the duty error adjuster 230 to compensate for a time difference between an externally applied clock and an actual internal clock, and a second compensated clock signal. Create (ICLK2).

The second phase detector 254 receives the external clock signal CLK and generates a second comparison signal CON2 by comparing it with the second compensation clock signal ICLK2 output from the second delay model unit 152. .

4 is a block for explaining the configuration and operation of the second delay unit 260 of FIG. 3.

Referring to FIG. 4, the second delay unit 260 is added between the first delay unit 220 and the duty error adjusting unit 230, and corresponding to the test mode signal TM, the first delay unit 220. The first and second additional delayed clock signals CLKD1 and CLKD2 which have bypassed or additionally delayed the first and second clock signals CLK1 and CLK2 inputted from the output signal are output to the duty error adjuster 230. To this end, it includes a first additional delay unit 262 and a second additional delay unit 264.

 In detail, when the test mode signal TM is in a disabled state, the first additional delay unit 262 may perform a duty error on the first clock signal CLK1 input from the first delay unit 220. When bypassing to the adjuster 230 and the test mode signal TM is in an enable state, the first clock signal CLK1 input from the first delay unit 220 is further delayed to allow the first clock signal CLK1 to be delayed. The additional delay clock signal CLKD1 is generated and transferred to the duty error adjuster 230.

To this end, the first additional delay unit 262 may convert the test mode signal TM and the first clock signal CLK1 inverted by the inverter IN1 and the inverter IN1 to invert the test mode signal TM. A first additional delay line 265 for additionally delaying the first NAND gate NAND1 to receive the NAND input, a first clock signal CLK1 input from the first delay unit 220, and a first additional delay The second NAND gate NAND2 which NAND couples the delayed first clock signal CLK1 and the test mode signal TM on the line 265, and the output signal of the first NAND gate NAND1 and the second NAND gate NAND1. And a third NAND gate NAND3 for outputting the first additional delayed clock signal CLKD1 by NAND-combining the output signal again.

Similarly, when the test mode signal TM is in the disabled state, the second additional delay unit 264 transfers the second clock signal CLK2 input from the first delay unit 220 to the duty error adjuster 230. When bypassing and the test mode signal TM is enabled, the second additional delay clock signal CLKD2 is further delayed by additionally delaying the second clock signal CLK2 input from the first delay unit 220. It generates and transfers to the duty error adjustment unit 230.

To this end, the second additional delay unit 264 may convert the test mode signal TM and the second clock signal CLK2 inverted by the inverter IN2 and the inverter IN2 to invert the test mode signal TM. A fourth NAND gate NAND4 that receives NAND coupling, a second additional delay line 267 that further delays the second clock signal CLK2 input from the first delay unit 220, and a second additional delay. An output signal of the fifth NAND gate NAND5 and the fourth NAND gate NAND4 and the fifth NAND gate NAND5 that NAND couple the second clock signal CLK2 and the test mode signal TM delayed at the line 267. And a sixth NAND gate NAND6 outputting the second additional delayed clock signal CLKD2 by NAND combining the output signal of the NAND again.

Here, the first and second additional delay lines 265 and 267 may include a unit delay cell (UDC) including two NAND gates used in each coarse delay line UCDL and LCDL of the first delay unit 220. It is configured by connecting a predetermined number in series.

As such, by configuring the second delay unit 260 in which the operation is controlled by the test mode signal TM between the first delay unit 220 and the duty error adjuster 230, the clock is free of additional delay and control circuits. It is possible to increase the period tCK.

Therefore, according to the present invention, an additional delay circuit and a control circuit are provided by placing a second delay section in front of the duty error adjustment section that further delays the first and second clock signals output from the first delay section corresponding to the test mode signal. This has the effect of providing a delayed loop circuit that can be tested for low frequencies by increasing the clock period without an increase.

Claims (9)

A delay locked loop circuit for delaying an internal clock signal to match an external clock signal, A first delay line receiving a clock signal activated at an edge of the external clock signal and outputting a first clock signal by delaying a predetermined time by a first comparison signal; A first additional delay unit configured to further delay the first clock signal corresponding to a test mode signal to output a second clock signal; And A first comparison signal generator configured to compensate for a time difference between the second clock signal and the internal clock and generate the first comparison signal for adjusting a delay time of the first delay line by comparing with the external clock signal; First loop means comprising a; A second delay line receiving the clock signal and outputting a third clock signal by delaying and inverting a predetermined time by a second comparison signal; A second additional delay unit configured to further delay the third clock signal corresponding to a test mode signal to output a fourth clock signal; And A second comparison signal that delays the fourth clock signal to have the same delay as the pass through which the second clock signal passes and generates the second comparison signal for adjusting the delay time of the second delay line in comparison with the external clock signal; Generation unit; A second loop means comprising a; And A duty error adjuster configured to adjust an duty of the second clock signal output from the first loop means and the fourth clock signal output from the second loop means to output an internal clock that matches the external clock signal; Delay fixed loop circuit comprising a. The method of claim 1, The first additional delay unit, And a delay locked loop circuit located in front of the duty error adjuster. The method of claim 1, The second additional delay unit, And a delay locked loop circuit located in front of the duty error adjuster. The method of claim 1, The first additional delay unit, When the test mode signal is disabled, the first clock signal is bypassed and output as the second clock signal. When the test mode signal is enabled, the first clock signal is delayed to delay the second clock signal. A delay locked loop circuit that outputs a clock signal. The method of claim 1, The second additional delay unit, When the test mode signal is disabled, the third clock signal is bypassed and output as the fourth clock signal. When the test mode signal is enabled, the third clock signal is delayed to delay the fourth clock signal. A delay locked loop circuit that outputs a clock signal. The method of claim 1, The first additional delay unit A first inverter for inverting the test mode signal; A first NAND gate configured to NAND-couple the test mode signal inverted by the first inverter and the first clock signal input from the first delay line; A first additional delay line for further delaying the first clock signal input from the first delay line corresponding to the test mode signal; A second NAND gate NAND combining the first clock signal delayed in the first additional delay line and the test mode signal; And, A third NAND gate outputting the second clock signal by NAND combining the output signal of the first NAND gate and the output signal of the second NAND gate again; Delay fixed loop circuit comprising a. The method of claim 6, And the first additional delay line is formed by connecting a predetermined number of unit delay cells consisting of two NAND gates in series. The method of claim 1, The second additional delay unit A second inverter for inverting the test mode signal; A fourth NAND gate configured to receive and NAND couple the test mode signal inverted by the second inverter and the third clock signal output from the second delay line; A second additional delay line for further delaying the third clock signal input from the second delay line corresponding to the test mode signal; A fifth NAND gate NAND combining the third clock signal and the test mode signal delayed in the second additional delay line; And And a sixth NAND gate outputting the fourth clock signal by NAND combining the output signal of the fourth NAND gate and the output signal of the fifth NAND gate again. The method of claim 8, And the second additional delay line is formed by connecting a predetermined number of unit delay cells consisting of two NAND gates in series.

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