KR100781041B1 - Flash memory device and its erasing control method - Google Patents

Abstract

The present invention relates to a flash memory device and a method of controlling an erase operation thereof, wherein an erase protection voltage applied to local word lines of an unselected block is lowered by a leakage current in an erase operation performed in a block unit to prevent an erase operation from proceeding. In order to prevent the erase of unselected blocks by applying a predetermined positive voltage to the global word line, a fast program or a slow erase phenomenon can be prevented from occurring in an increase in the number of erase operations, and the erase operation of the erase target block is performed. If this is not done normally, the erase operation is performed again by adjusting the positive voltage applied to the global word line or the voltage applied to the bulk of the block to be erased so that the voltage difference between the local word line and the bulk is increased, thereby ensuring reliability of the erase operation. Improves unusable by bad erase The occurrence of blocks can be minimized.

Description

Flash memory device and method for controlling erase operation of the same}

1 is a circuit diagram of memory cells and pass gates for explaining an erase operation of a conventional flash memory device.

2 is a characteristic graph illustrating a slow erasure characteristic and a fast program characteristic according to the number of erase operations in the prior art.

3 is a characteristic graph showing slow erasure characteristics and fast program characteristics at the level of the erase voltage in the prior art.

4 is a block diagram of a flash memory device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating in detail a memory cell array, a block selector, a second bias voltage generator, a bulk voltage generator, and an X-decoder shown in FIG. 4.

FIG. 6 is a diagram illustrating in detail the memory cells, the switching elements, the bulk voltage baler, and the bias voltage selector illustrated in FIG. 5.

7 is a flowchart illustrating a method of controlling an erase operation of a flash memory device according to an embodiment of the present invention.

8A is a cross-sectional view illustrating an example of the switching element illustrated in FIG. 6.

FIG. 8B is a diagram illustrating a change in energy potential according to a bias voltage change of a word line in the switching device illustrated in FIG. 6.

9A to 9C are waveform diagrams for describing a first exemplary embodiment in which a voltage is applied to a global word line and a P well during an erase operation in FIG. 5.

10A to 10C are waveform diagrams for describing a second exemplary embodiment in which a voltage is applied to a global word line and a P well during an erase operation in FIG. 5.

11 is a characteristic graph for comparing changes in threshold voltages of unselected blocks during an erase operation.

12 is a characteristic graph illustrating a slow erasure characteristic and a fast program characteristic according to the number of erase operations in the present invention.

Explanation of symbols for main parts of drawings>

100: flash memory device 110: memory cell array

120: input buffer 130: control logic circuit

140: high voltage generator 150: X-decoder

160: block selection unit 170: page buffer

180: Y-decoder 190: data input / output buffer

40: bulk voltage generator 50: first bias voltage generator

60: second bias voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method of controlling the erase operation thereof, and more particularly to a flash memory device and a method of controlling the erase operation of the flash memory device for preventing the reliability of the erase operation from being degraded due to leakage current in the block-based erase operation. .

In general, flash memory devices are classified into a NOR type, which is mainly used to store a small amount of information at high speed, and a NAND type, which is mainly used to store a large amount of information. The flash memory device performs a read operation, a program operation, and an erase operation. Program and erase operations involve storing data in one or more cells by injecting electrons into or floating from the floating gate. For example, in a program operation, only selected cells of a plurality of memory cells included in a memory cell block are programmed. The erase operation of the flash memory device is performed by the electrons present in the floating gate of the memory cell being discharged to the P-well by the FN tunneling. In the erase operation, data stored in all memory cells included in the memory cell block are simultaneously erased. That is, the erase operation is performed in units of memory cell blocks.

1 is a circuit diagram of memory cells and pass gates for explaining an erase operation of a conventional flash memory device. In the erase operation, a bias voltage Vb of 0 V is applied to the global word line GWL, and a bulk voltage VBK1 of 20 V is applied to the P-well of the memory cells CA1-CAn and CB1-CBn (n is an integer). ) Is applied. Sources and drains of the memory cells CA1 to CAn and CB1 to CBn are in a floating state. In addition, the gate of the NMOS transistor NM1 connected between the local word line WL1 and the global word line GWL of the selected (ie, to be erased) memory cell block A has a voltage Vcc level. The block select signal BKSEL1 is input. In addition, a bulk voltage VBK2 of 0 V is applied to a substrate (not shown) of the NMOS transistor NM1. The NMOS transistor NM1 is turned on in response to the block select signal BKSEL1 and connects the local word line WL1 to the global word line GWL. As a result, the voltage of the local word line WL1 becomes 0V, and the control gates (not shown) and the memory cells CA1-CAn of the memory cells CA1-CAn connected to the local word line WL1. A voltage difference of 20V is generated between the P-wells. Therefore, electrons of the floating gates of the memory cells CA1 to CAn are emitted to the P-wells, thereby performing an erase operation of the memory cell block A. FIG.

On the other hand, a gate selection signal of 0V is applied to the gate of the NMOS transistor NM2 connected between the local word line WL2 and the global word line GWL of the memory cell block B that is not selected (that is, not erased). BKSEL2) is input. In addition, a bulk voltage VBK2 of 0V is applied to the substrate of the NMOS transistor NM2. The NMOS transistor NM2 is turned off in response to the block select signal BKSEL2 and separates the local word line WL2 from the global word line GWL. As a result, the local word line WL2 is in a floating state. Thereafter, the bulk voltage VBK1 of 20 V applied to the P-wells of the memory cells CB1-CBn is induced in the local word line WL2 by a capacitive coupling phenomenon. The voltage level of the local word line WL2 is boosted to about 19V. Accordingly, a minute voltage difference of about 1 V is generated between the local word line WL2 and the P-wells of the memory cells CB1-CBn, so that electrons are not emitted from the floating gates of the memory cells CB1-CBn. . As a result, while the erase operation of the memory cell block A is performed, the erase operation of the memory cell block B is not performed. However, even when the NMOS transistor NM2 is turned off, a leakage current may be generated in the NMOS transistor NM2. Therefore, the voltage level of the local word line WL2 boosted to a voltage level close to the bulk voltage VBK1 may be gradually decreased. As a result, the voltage difference between the control gates of the memory cells CB1-CBn and the P-wells is increased, so that a small amount of electrons are emitted from the floating gates of the memory cells CB1-CBn which should not be erased. (I.e. shallow erase). Erase disturbances, such as shallow erase, become more severe when the number of memory cell blocks included in a flash memory device increases. For example, the shallow erase phenomenon may occur repeatedly in memory cells of a memory cell block that should not be erased each time the memory cell blocks perform an erase operation one by one. As a result, threshold voltages of the corresponding memory cells are gradually reduced, causing a failure during read operation.

In addition, as the number of erase operations increases, a past program phenomenon in which a threshold voltage becomes higher than a target voltage in a program operation, or a slow erase phenomenon in which the threshold voltage does not sufficiently decrease to a target voltage in an erase operation. Is generated. Referring to Figure 2 in more detail as follows.

2 is a characteristic graph illustrating a slow erasure characteristic and a fast program characteristic according to the number of erase operations in the prior art.

Referring to FIG. 2, even when the program or erase operation is performed under the same condition, as the accumulated erase count increases, the threshold voltage after the program operation or the erase operation is higher than the target voltage. This means that the program operation proceeds quickly or the erase operation proceeds slowly. This phenomenon is caused by the high voltage difference between the word line and the bulk during the erase operation. In other words, the larger the voltage difference between the word line and the bulk during the erase operation, the more severe the fast program and slow erase phenomenon.

 3 is a characteristic graph showing slow erasure characteristics and fast program characteristics at the level of the erase voltage in the prior art.

Referring to FIG. 3, when the erase operation is performed while the voltage difference between the word line and the bulk is high (high potential erase), a fast program phenomenon and a slow erase phenomenon may occur. However, when the erase operation is performed in a state where the voltage difference between the word line and the bulk is relatively low (low potential erase), the fast program phenomenon and the slow erasure phenomenon are relatively less likely to occur.

As described above, in order to suppress the occurrence of the fast program phenomenon and the slow erasure phenomenon, the erase operation should be performed with the voltage difference between the word line and the bulk lowered. However, in this case, the erase operation time is long, and the erase operation may not be normally performed. After the erase operation is performed, erase verification is performed. If the erase operation is not performed normally, the corresponding block is not treated as an invalid block. This results in a reduction in the number of available blocks, resulting in a reduction in data storage capacity.

In contrast, in the flash memory device and the erase operation control method of the present invention, the erase operation is performed because the erase protection voltage applied to the local word lines of the unselected block is lowered by the leakage current in the erase operation in the block unit. In order to prevent the block from being erased by applying a predetermined positive voltage to the global word line, it is possible to prevent the occurrence of a fast program or a slow erase phenomenon due to an increase in the number of erase operations, and If the erase operation is not performed normally, the erase operation is performed again by adjusting the positive voltage applied to the global word line or the voltage applied to the bulk of the block to be erased so as to increase the voltage difference between the local word line and the bulk. Improved reliability for use by erase failure It is possible to minimize the occurrence of impossible blocks.

A flash memory device according to a first embodiment of the present invention includes first and second memory cell blocks each including a local drain select line, a local source select line, and local word lines to which a plurality of memory cells are connected, and block selection. A block selector for connecting the local word lines to the global word lines in accordance with the signal, applying a first erase voltage to the global word lines during the first erase operation during the erase operation, and the first erase operation is abnormally completed. A first bias voltage generator for applying a second erase voltage at a level different from the first erase voltage to the global word lines during the new second erase operation, and a bulk for applying the bulk voltage to the bulk of the memory cells during the erase operation. And a voltage generator.

In the above, the erase voltage applied to the global word lines is lowered for each new erase operation, and the erase operation is terminated after a predetermined number of times. The first bias voltage generator generates an erase voltage such that the voltage difference between the local word line and the bulk becomes 15V during the first erase operation. The erase voltage applied to the global word lines is reduced linearly, quadratic, or exponentially within a range of 0.1V to 0.5V each time a new erase operation is performed.

The apparatus further includes a page buffer for reading data stored in the memory cells, and a Y-decoder for outputting data stored in the page buffer to the data input / output buffer and the first bias voltage generator. The first bias voltage generator changes the first erase voltage to the second erase voltage according to the data output from the Y-decoder.

A flash memory device according to a second embodiment of the present invention includes memory cell blocks each including a local drain select line, a local source select line, and local word lines to which a plurality of memory cells are connected, and a local word according to a block selection signal. A block selector for connecting the lines with the global word lines, a first bias voltage generator for applying a positive voltage to the global word lines during the erase operation, and a first during the first erase operation during the erase operation. A bulk voltage generator for applying a bulk voltage to the bulk of the memory cells and for applying a second erase voltage of a level different from the first erase voltage to the bulk during a new second erase operation when the first erase operation is abnormally completed. .

In the above, the first erase operation is determined to be abnormally completed unless all of the memory cells selected for the erase operation are erased by the first erase operation. The bulk voltage generator generates a first bulk voltage such that the voltage difference between the local wordline and the bulk is 15V during the initial erase operation, and the first bulk voltage within a range of 0.5V to 1V for each new erase operation is performed. , To increase quadratic or exponentially.

The apparatus further includes a page buffer for reading data stored in the memory cells, and a Y-decoder for outputting data stored in the page buffer to the data input / output buffer and the bulk voltage generator. The bulk voltage generator generates a second bulk voltage to perform a second erase operation in accordance with the data output from the Y-decoder.

A flash memory device according to a third embodiment of the present invention includes memory cell blocks each including a local drain select line, a local source select line, and a local word line to which a plurality of memory cells are connected, and a local according to a block selection signal. A block selector for connecting the word lines to the global word lines, and an erase voltage having a positive potential applied to the global word lines during an erase operation, and erased for re-execution of the erase operation if an unerased memory cell exists. A first bias voltage generator for lowering the level of the voltage and applying it to the global word line, and applying the bulk voltage to the bulk of the memory cells during the erase operation, and if the non-erased memory cell exists, the bulk voltage to re-execute the erase operation It includes a bulk voltage generator for applying the bulk at a higher level.

In the above description, the first bias voltage generator and the bulk voltage generator generate the erase voltage and the bulk voltage so that the voltage difference between the local word line and the bulk becomes 15 V during the initial erase operation, and the local word line and the bulk voltage generator when the erase operation is performed again. The bulk voltage is increased while reducing the level of the erase voltage so that the voltage difference between the bulk is higher than 15V. The first bias voltage generator first decreases the erase voltage by 0.1V to 0.5V, or the second decreases or exponentially, and the bulk voltage generator reduces the bulk voltage by 0.5V to 1V. Increase primarily or quadraticly or exponentially.

The apparatus further includes a page buffer for reading data stored in the memory cells, and a Y-decoder for outputting data stored in the page buffer to the data input / output buffer, the bulk voltage generator, and the first bias voltage generator. When the first bias voltage generator and the bulk voltage generator detect data indicating an unerased state among data output from the Y-decoder, the first bias voltage generator and the bulk voltage generator lower the level of the erase voltage and increase the level of the bulk voltage, respectively, in order to perform the erase operation.

The method may further include an X-decoder for decoding the row address signal and outputting the block selection signal to the high voltage generator. The apparatus may further include a second bias voltage generator for applying a predetermined operating voltage to the local drain select line and the local source select line according to any one of a program, a read, and an erase operation.

The first bias voltage generator includes: a first pump circuit for generating read voltages for a read operation in response to a read command; a second pump circuit for generating program voltages for a program operation in response to a program command; and an erase command. A third pump circuit which generates an erase voltage in response and decreases the level of the erase voltage when data indicating an unerased state is detected among data output from the Y-decoder, and read voltages in response to an operation command signal or And a bias voltage selector for selecting program voltages or erase voltages and outputting the selected voltages to global word lines, respectively. The bias voltage selector is connected to a select signal generator that generates select signals based on an operation command signal, and global word lines, respectively, and selects one of read voltages, program voltages, and erase voltages in response to the select signals. Select circuits respectively output to corresponding global word lines.

According to an embodiment of the present disclosure, a method of controlling an erase operation of a flash memory device may include electrically connecting local word lines and global word lines of a selected block according to a block selection signal, and between the positive potentials according to an erase command. Performing an erase operation by applying an erase voltage to the global word line and applying a bulk voltage higher than the erase voltage to the bulk of the memory cell, a verification step of determining whether the erase operation is normally performed, and an erase operation is not normally performed. Otherwise, the erase operation is performed by lowering the level of the erase voltage such that the voltage difference between the local word line and the bulk becomes larger.

In the above, the verifying and erasing operations may be repeated by a predetermined number of times while lowering the erase voltage by a predetermined level. If the erase operation is not performed by the predetermined number of times, the corresponding block may be treated as an invalid block. have.

According to another aspect of the present invention, a method of controlling an erase operation of a flash memory device may include electrically connecting local word lines and global word lines of a selected block according to a block selection signal, Performing an erase operation by applying an erase voltage to the global word line and applying a bulk voltage higher than the erase voltage to the bulk of the memory cell, a verification step of determining whether the erase operation is normally performed, and an erase operation is not normally performed. If not, increasing the level of the bulk voltage so that the voltage difference between the local word line and the bulk becomes larger.

In the above description, the verifying and erasing operations may be repeated a predetermined number of times while increasing the bulk voltage by a predetermined level. If the erase operation is not performed until the predetermined number of times, the corresponding block may be treated as an invalid block. have.

According to a third embodiment of the present invention, a method of controlling an erase operation of a flash memory device may include electrically connecting local word lines and global word lines of a selected block according to a block selection signal, and between positive potentials according to an erase command. Performing an erase operation by applying an erase voltage to the global word line and applying a bulk voltage higher than the erase voltage to the bulk of the memory cell, a verification step of determining whether the erase operation is normally performed, and an erase operation is not normally performed. If not, the step of performing the erase operation by simultaneously adjusting the levels of the erase voltage and the bulk voltage so that the voltage difference between the local word line and the bulk becomes larger.

In the above, the verifying and erasing operation may be repeated by a predetermined number of times by lowering the level of the erase voltage by a predetermined level and by increasing the bulk voltage by a predetermined level. You can treat the block as an invalidated block.

It is also desirable to set the levels of the erase voltage and bulk voltage such that the voltage difference between the local word line and the bulk is at least 15V.

The erase voltage may be lowered in 0.1V to 0.5V units and may be exponentially lowered so that the voltage difference increases in a range where the voltage difference between the local word line and the bulk becomes at least 15V or more.

The bulk voltage may be increased in units of 0.5V to 1V, and may be exponentially increased so that the voltage difference increases in a range where the voltage difference between the local word line and the bulk becomes at least 15V or more.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

4 is a block diagram of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 4, the flash memory device 100 may include a memory cell array 110, an input buffer 120, a control logic circuit 130, a high voltage generator 140, an X-decoder 150, and a block selector ( 160, a page buffer 170, a Y-decoder 180, and a data input / output buffer 190. The memory cell array 110 includes memory cell blocks MB1-MBK (K is an integer) each of which includes a plurality of memory cells (not shown). The input buffer 120 receives a command signal CMD or an address signal ADD and outputs the same to the control logic circuit 130. The control logic circuit 130 receives the command signal CMD or the address signal ADD in response to external control signals / WE, / RE, ALE, and CLE. The control logic circuit 130 generates one of a read command READ, a program command PGM, and an erase command ERS in response to the command signal CMD. The control logic circuit 130 generates a row address signal RADD and a column address signal CADD based on the address signal ADD.

The high voltage generator 140 includes a bulk voltage generator 40, a first bias voltage generator 50, and a second bias voltage generator 60. The bulk voltage generator 40 generates a bulk voltage VCC in response to one of the read command READ, the program command PGM, and the erase command ERS, and generates the bulk voltage VCC. Supply to the P-well of the memory cells. More specifically, in response to the read command READ or the program command PGM, the bulk voltage generator 40 generates the bulk voltage VCB to a low voltage (eg, 0V) level. . In addition, the bulk voltage generator 40 generates the bulk voltage VCB at a high voltage (eg, 16V to 20V) level in response to the erase command ERS. On the other hand, after the erase operation, if there is a cell in which the erase operation is not normally performed according to the data output from the Y-decoder 180, the level of the bulk voltage VCB is adjusted. For example, when the erase operation is not normally performed, the level of the bulk voltage VCB is increased in units of 0.5V or 1V, and the rising width may be changed according to design.

The first bias voltage generator 50 may apply a drain bias voltage VGD and a source bias voltage VGS in response to one of the read command READ, the program command PGM, and the erase command ERS. Is generated, the drain bias voltage VGD is supplied to the global drain select line GDSL, and the source bias voltage VGS is supplied to the global source select line GSSL. More specifically, in response to the read command READ, the first bias voltage generator 50 sets the drain bias voltage VGD and the source bias voltage VGS to a high voltage (eg, 4.5V). ) Occurs at the level. In addition, in response to the program command PGM, the first bias voltage generator 50 generates the drain bias voltage VGD to an internal voltage VCC, not shown, and the source bias voltage VGS. Occurs at the low voltage level. In response to the erase command ERS, the first bias voltage generator 50 generates the drain bias voltage VGD and the source bias voltage VGS at the low voltage level.

The second bias voltage generator 60 may perform word line bias voltages VWF1-1 in response to one of the read command READ, the program command PGM, and the erase command ERS and the decoding signal DEC. VWFJ (J is an integer) or word line bias voltages VWS1-VWSJ (J is an integer) or word line bias voltages VWT1-VWTJ (J is an integer) to generate global word lines GWL1-. GWLJ) (J is an integer). More specifically, in response to the read command READ, the second bias voltage generator 60 generates word line bias voltages VWF1-VWFJ. In addition, the second bias voltage generator 60 generates the word line bias voltages VWS1-VWSJ in response to the program command PGM. In addition, the second bias voltage generator 60 generates the word line bias voltages VWT1 -VWTJ in response to the erase command ERS. Here, the second bias voltage generator 60 generates a positive voltage higher than 0 V when the erase command ERS is input, and after the erase operation, the erase operation is not normally performed according to the data output from the Y-decoder 180. If the cell is present, the level of the word line bias voltages VWT1-VWTJ is adjusted. For example, when the erase operation is not performed normally, the levels of the word line bias voltages VWT1 -VWTJ are lowered by 0.1V to 0.5V, and the falling width may be changed according to design.

In the above, when the erase operation is not normally performed, the bulk voltage generator 40 and the second word line voltage generator 60 adjust the level of the output voltage, which increases the voltage difference between the word line and the bulk to perform the erase operation. It is to carry out again. Here, only one of the bulk voltage generator 40 and the second word line voltage generator 60 may adjust the level of the output voltage so that the voltage difference between the word line and the bulk is increased, and the two simultaneously adjust the level of the output voltage. It may be. More details will be described later.

The X-decoder 150 decodes the row address signal RADD and outputs the decoded signal DEC. The block selector 160 selects one or a portion of the memory cell blocks MB1-MBK in response to the decoding signal DEC, and localizes the selected memory cell block (or memory cell blocks). Word lines WL11-WL1J (see FIG. 5) are respectively connected to the global word lines GWL1-GWLJ. In addition, the block selector 160 connects the drain select line (one of DSL1-DSLK, see FIG. 5) of the selected memory cell block to the global drain select line GDSL, and the source of the selected memory cell block. A select line (one of SSL1-SSLK, see FIG. 5) is connected to the global source select line GSSL. Since the structure and detailed operations of the page buffer 170, the Y-decoder 180, and the data input / output buffer 190 may be understood by those skilled in the art, a detailed description thereof will be provided. Will be omitted.

FIG. 5 is a diagram illustrating in detail a memory cell array, a block selector, a second bias voltage generator, a bulk voltage generator, and an X-decoder shown in FIG. 4.

Referring to FIG. 5, the memory cell block MB1 of the memory cell array 110 includes the memory cells M111 -M1JT (J and T are integers), the drain select transistor DST1, and the source select transistor SST1. Include. The memory cells M111-M1JT share bit lines BL1-BLT (T is an integer), local word lines WL11-WL1J (J is an integer), and a common source line CSL1. That is, the memory cells M111-M11T are connected to the bit lines BL1-BLT through the drain select transistor (s) DST1, respectively, and the memory cells M1J1-M1JT are connected to the source select transistor. It is connected to the common source line CSL1 through (s) SST1. In addition, gates of the memory cells M111-M1JT are connected to the local word lines WL11-WL1J. Meanwhile, gates of the drain select transistor (s) DST1 are connected to a local drain select line DSL1, and gates of the source select transistor (s) SST1 are connected to a local source select line SSL1.

Since the configuration of the memory cell blocks MB2-MBK of the memory cell array 110 is similar to that of the memory cell block MB1, detailed description thereof will be omitted. The block selector 160 includes a block switch 161 and a plurality of switching units PG1 -PGK (K is an integer). The block switch unit 161 outputs block selection signals BSEL1 to BSELK (K is an integer) in response to the decoding signal DEC received from the X-decoder 150. The plurality of switching units PG1-PGK are disposed corresponding to the memory cell blocks MB1-MBK one by one, and are enabled or disabled in response to the block selection signals BSEL1-BSELK, respectively. .

Each of the plurality of switching units PG1-PGK includes a plurality of switching elements. For example, the switching unit PG1 includes switching elements GD1, G11-G1J, and GS1. Since the configuration and specific operations of the switching units PG2-PGK are similar to those of the switching unit PG1, the operation of the switching unit PG1 will be described. Preferably, the switching elements GD1, G11-G1J, GS1 may be implemented with NMOS transistors. Hereinafter, the switching elements GD1, G11-G1J and GS1 are referred to as NMOS transistors. The block select signal BSEL1 is input to gates of the NMOS transistors GD1, G11-G1J, and GS1. The source of the NMOS transistor GD1 is connected to a global drain select line GDSL, and the drain thereof is connected to the local drain select line DSL1. Sources of the NMOS transistors G11-G1J are respectively connected to global word lines GWL1-GWLJ, and drains thereof are respectively connected to the local word lines WL11-WL1J. A source of the NMOS transistor GS1 is connected to a global source select line GSSL, and a drain thereof is connected to the local source select line SSL1. The NMOS transistors GD1, G11-G1J, and GS1 are simultaneously turned on or off in response to the block select signal BSEL1. More specifically, the NMOS transistors GD1, G11-G1J and GS1 are turned on when the block select signal BSEL1 is enabled, and the NMOS when the block select signal BSEL1 is disabled. Transistors GD1, G11-G1J and GS1 are turned off. When the NMOS transistors GD1, G11-G1J, and GS1 are turned on, the global drain select line GDSL is in the local drain select line DSL1, and the global source select line GSSL is selected in the local source. The line SSL1 and the global word lines GWL1 to GWLJ are connected to the local word lines WL11 to WL1J, respectively.

The second bias voltage generator 60 includes first to third pump circuits 61, 62, and 63 and a bias voltage selector 64. The first pump circuit 61 generates the read voltages VRD1 and VRD2 in response to the read command READ. Preferably, the read voltage VRD1 has a high voltage (eg, 4.5V) level, and the read voltage VRD2 has a low voltage (eg, 0V) level. In a read operation of the memory cell array 110, the read voltage VRD1 is supplied to a local word line to which gates of unselected memory cells (ie, memory cells that are not to be read) are connected, and the read voltage VRD2. Is supplied to the local word line to which the gates of the selected memory cells (ie, memory cells to be read) are connected.

The second pump circuit 62 generates the program voltages VPG and VPS in response to the program command PGM. Preferably, the program voltages VPG and VPS each have a high voltage level (eg, VPG = 18V, VPS = 10V). In the program operation of the memory cell array 110, the program voltage VPG is supplied to a local word line to which gates of memory cells to be programmed are connected, and the program (or pass) voltage VPs is programmed. Gates of memory cells that will not be supplied are supplied to the local word line to which they are connected.

In addition, the third pump circuit 63 generates the erase voltage VERS having a positive level higher than 0V in response to the erase command ERS. That is, during the erase operation, the erase voltage Vers is generated to apply a voltage higher than OV to word lines of the selected block. At this time, the voltage difference between the word line and the bulk is reduced in the block in which the erase operation is performed by the positive potential erase voltage VERS, and the erase voltage VERS has a voltage difference of 15 V between the word line and the bulk in the block in which the erase operation is performed. It is desirable to be generated at a level that can be from to 20V. On the other hand, if the non-erased data (for example, 0) is detected among the data output from the Y-decoder (180 of FIG. 4) in the operation of determining whether the erase operation is normally performed, the third operation is performed. The pump circuit 63 lowers the level of the erase voltage Vers in units of 0.1V to 0.5V and outputs it. At this time, the falling width may be changed according to the design. In this case, the erase voltage Vers may be lowered linearly or linearly, or may be exponentially lowered. Then, the voltage difference between the word line and the bulk is increased, and the erase operation is re-executed according to the increased voltage difference.

The bias voltage selector 64 selects the read voltages VRD1 and VRD2 in response to the decoding signal DEC received from the X-decoder 150 as word line bias voltages VWF1-VWFJ. The global word lines GWL1 may be output to the global word lines GWL1-GWLJ, or the program voltages VPG and VPS may be selected as word line bias voltages VWS1-VWSJ (J is an integer). Output to the global word lines GWL1-GWLJ respectively as word line bias voltages VWT1 -VWTJ. Detailed configurations and operation descriptions of the first to third pump circuits 61, 62, and 63 may be omitted by those skilled in the art.

The bulk voltage generator 40 applies a bulk voltage of a high voltage to be applied to a bulk (eg, P well) in which the memory cells M111-M1JT (J and T are integers) are formed in an erase operation in response to the erase command ERS. Create (VCB). In this case, the bulk voltage VCC is generated at a level such that the voltage difference between the word line and the bulk may be 15V to 20V in the block in which the erase operation is performed. On the other hand, in the operation of determining whether the erase operation is normally performed, if the non-erased data (for example, 0) is detected among the data output from the Y-decoder (180 in FIG. 4) (the erase operation fails), the bulk voltage The generator 40 increases the level of the bulk voltage VCB in units of 0.5V to 1V and outputs the same. In this case, the rising width may be changed according to the design. For example, the bulk voltage VCB can be increased primary or secondary functionally, or can be increased exponentially. Then, the voltage difference between the word line and the bulk is increased, and the erase operation is re-executed according to the increased voltage difference. Then, the voltage difference between the word line and the bulk is increased, and the erase operation is re-executed according to the increased voltage difference.

As described above, when the erase operation is performed while the positive voltage is applied to the global word line, and the erase operation is not normally performed, the third pump circuit 63 and the bulk voltage generator 40 to increase the voltage difference between the word line and the bulk. ) Or the output voltage of these modes is adjusted to perform the erase operation again. At this time, the output voltage of the third pump circuit 63 or the bulk voltage generator 40 is adjusted so that the voltage difference between the word line and the bulk is at least 15V or more.

FIG. 6 is a diagram illustrating in detail the memory cells, pass gates, a bulk voltage generator, and a bias voltage selector illustrated in FIG. 5.

Referring to FIG. 6, the bias voltage selector 64 includes a select signal generator 65 and select circuits S1 -SJ (J is an integer). The selection signal generator 65 generates the selection signals SL1 -SLJ based on the decoding signal DEC. The selection circuits S1 -SJ include switches SW11-SW15,..., SWJ1-SWJ5 respectively connected to the global word lines GWL1-GWLJ. The selection circuits S1-SJ receive read voltages VRD1 and VRD2, program voltages VPG and VPS, and an erase voltage VERS, respectively, and respond to the selection signals SL1-SLJ. The word line bias voltages VWF1 -VWFJ or VWS1 -VWSJ or VWT1 -VWTJ are respectively output to the global word lines GWL1-GWLJ. In more detail, for example, the switches SW11-SW15 of the selection circuit S1 may include the read voltages VRD1 and VRD2, the program voltages VPG and VPS, and erase. The voltage VERS is connected between the global word line GWL1, respectively. The switches SW11 to SW15 are turned on or off according to logic values of bits B1-B5 of the selection signal SL1, respectively. Here, when the switches SW11 to SW15 are implemented as NMOS transistors, the switches SW11 to SW15 are turned on when the logic values of the bits B1 to B5 are 1. In addition, the switches SW11 to SW15 are turned off when the logic values of the bits B1 to B5 are zero.

For example, when one of the switches SW11 and SW12 is turned on, one of the read voltages VRD1 and VRD2 is input to the global word line GWL1 as the word line bias voltage VWF1. In addition, when one of the switches SW13 and SW14 is turned on, one of the program voltages VPG and VPS is input to the global word line GWL1 as the word line bias voltage VWS1. In addition, when the switch SW15 is turned on, the erase voltage VERS is input to the global word line GWL1 as the word line bias voltage VWT1. At this time, since the selection signal generator 65 generates a logic value of one of the bits B1-B5 as 1 and a logic value of the remaining bits as 0, one of the switches SW11-SW15 is turned on. And the rest are off. As a result, one of the read voltages VRD1 and VRD2, the program voltages VPG and VPS and the erase voltage VERS is applied to the global word line GWL1. The configuration and specific operation of the selection circuits S2-SJ are similar to those of the selection circuit S1 described above.

In FIG. 6, the selection circuits S1-SJ include five switches, respectively, but the selection circuits S1-SJ are word line bias voltages VWF1-VWFJ or VWS1-VWSJ or VWT1. As long as -VWTJ are respectively output, the configuration of the selection circuits S1 -SJ may be variously changed.

In FIG. 6, for the sake of simplicity, the NMOS transistors G11, GK1, G1J and GKJ connected to the global word lines GWL1 and GWLJ, the local word lines WL11, WL1J, WLK1, and WLKJ are stored. Only cells M111, M11T, M1J1, M1JT, MK11, MK1T, MKJ1, MKJT are shown. Gates of the memory cells M111-M11T are connected to the local word line WL11, and gates of the memory cells M1J1-M1JT are connected to the local word line WL1J. The gates of the memory cells MK11-MK1T are connected to the local word line WLK1, and the gates of the memory cells MKJ1-MKJT are connected to the local word line WLKJ. The source and the drain of the NMOS transistor G11 are connected to the global word line GWL1 and the local word line WL11, respectively, and the source and the drain of the NMOS transistor GK1 are the global word line GWL1. And the local word line WLK1, respectively. In addition, the source and the drain of the NMOS transistor G1J are connected to the global word line GWLJ and the local word line WL1J, respectively, and the source and the drain of the NMOS transistor GKJ are the global word line GWLJ. ) And the local word line WLKJ, respectively.

7 is a flowchart illustrating a method of controlling an erase operation of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 7, the levels of the erase voltage VWTJ and the bulk voltage VCC are set such that the erase voltage VWTJ has a positive potential and a difference from the bulk voltage VCC is 15V (S701). When the erase voltage VWTJ and the bulk voltage VCC are set, an erase operation is performed by using the erase voltage VWTJ and the bulk voltage VVC for all the flash memory cells of the block selected by the block select signal BLKWL. (S702). When the erase operation is completed, it is verified whether the erase operation is normally performed (S703). According to the erase verification result, when all the flash memory cells are erased and the erase operation is normally performed, the erase operation is terminated. However, when the non-erased flash memory cell is present, the erase operation is performed by resetting the erase voltage VWTJ and the bulk voltage VCC. This will be described in more detail as follows.

First, the number of times of the erase operation is increased (S704). Then, it is determined whether the number of times of the erase operation is smaller than the set number of times (S705). If the number of erase operations is smaller than the set number of times, the level of the erase voltage VWTJ or the bulk voltage VCC is changed (S706). At this time, these voltages are changed such that the difference between the erase voltage VWTJ and the bulk voltage VCC becomes larger than 15V. A detailed method of changing the levels of the erase voltage VWTJ and the bulk voltage VCC will be described later. When the change of the erase voltage VWTJ and the bulk voltage VCC is completed, an erase operation is performed using the changed voltages (S702). When the erase operation is completed, the above-described steps S703 to S705 are performed again.

On the other hand, if the erase operation is not normally performed until the number of erase operations reaches the set number of times, the corresponding block is processed as an invalid block (S707).

4 to 6, the erase operation of the flash memory device 100 described with reference to FIG. 7 will be described in more detail. First, the control logic circuit 130 generates the erase command ERS in response to the external control signals / WE, / RE, ALE, and CLE and the command signal CMD, and based on the address signal ADD, Generate the row address signal RADD. In response to the erase command ERS, the bulk voltage generator 40 of the high voltage generator 140 generates the bulk voltage VCB to a high voltage (for example, 17V) level, thereby providing memory cell blocks MB1-MBK. It is supplied to the formed bulk (P well). In addition, the first bias voltage generator 50 of the high voltage generator 140 lowers the drain bias voltage VGD and the source bias voltage VGS in response to the erase command ERS (for example, 0V). Occurs as a level. Therefore, the drain bias voltage VGD is supplied to the global drain select line GDSL, and the source bias voltage VGS is supplied to the global source select line GSSL. The X-decoder 150 decodes the row address signal RADD and outputs a decoded signal DEC. The second bias voltage generator 60 of the high voltage generator 140 generates the word line bias voltages VWT1 -VWTJ in response to the erase command ERS and the decoding signal DEC, thereby generating a global word. Supply to the lines GWL1-GWLJ respectively. More specifically, the third pump circuit 63 of the second bias voltage generator 60 generates an erase voltage VERS having a positive value in response to the erase command ERS. For example, the erase voltage VERS is less than the bulk voltage VBC supplied to the P-well of the memory cell during the erase operation and has a positive value. Preferably, the difference between the bulk voltage VCC supplied to the P-well of the memory cell and the erase voltage VERS may be greater than or equal to 15V during the erase operation. The bias voltage selector 64 of the second bias voltage generator 60 selects the erase voltage Vers in response to the decoding signal DEC, and selects the erase voltage Vers as the word line bias voltages VWT1 -VWTJ. Output More specifically, the selection signal generator 65 of the bias voltage selector 64 responds to the decoding signal DEC, so that the values of the bits B1-B5 of the selection signals SL1-SLJ are selected. Output them as "00001". In response to each of the selection signals SL1 -SLJ, the switches SW15-SWJ5 of the selection circuits S1-SJ of the bias voltage selector 64 are turned on, and the switches SW11-SWJ1 are turned on. , SW12-SWJ1, SW13-SWJ3, SW14-SWJ4) are all turned off. Therefore, the erase voltage VERS is input to the global word lines GWL1-GWLJ as the word line bias voltages VWT1-VWTJ, respectively, through the switches SW15-SWJ5.

In addition, the block selector 160 selects one of the memory cell blocks MB1-MBK in response to the decoding signal DEC, and selects local word lines of the selected memory cell block from the global word lines. GWL1-GWLJ) respectively. For example, when the memory cell block MB1 is selected, the block switch unit 161 of the block selector 160 enables the block select signal BSEL1 in response to the decoding signal DEC. In addition, all of the block selection signals BSEL2-BSELK are disabled. As a result, only the switching unit PG1 of the block selector 160 is enabled, and all other switching units PG2-PGK are disabled. More specifically, the switching elements GD1, G11-G1J, and GS1 of the switching unit PG1 are turned on at the same time, and the switching elements GD2-GDK and G21-of the switching units PG2-PGK are simultaneously turned on. 2J, ... GK1-GKJ, GS2-GSK) are all turned off. Therefore, the drain select line DSL1 of the memory cell block MB1 is connected to the global drain select line GDSL, and the source select line SSL1 is connected to the global source select line GSSL. As a result, a drain bias voltage VGD and a source bias voltage VGS of a low voltage level are input to the drain select line DSL1 and the source select line SSL1, respectively, so that the drain select transistor DST1 and the source select transistor are input. (SST1) is turned off. Therefore, the drains and the sources of the memory cells M111-M1JT of the memory cell block MB1 are in a floating state.

In addition, local word lines WL11 to WL1J of the memory cell block MB1 are connected to the global word lines GWL1 to GWLJ, respectively. As a result, the word line bias voltages VWT1-VWTJ of the global word lines GWL1-GWLJ are transferred to the local word lines WL11-WL1J, respectively. Therefore, a voltage difference (for example, 15 V or more) is generated between the gates and the bulks of the memory cells M111-M1JT of the memory cell block MB1, and the voltage difference causes the memory cells M111-. Electrons are emitted from the floating gates of M1JT to perform an erase operation of the memory cells M111-M1JT.

Meanwhile, drain select lines DSL2-DSLJ of the memory cell blocks MB2-MBK are separated from the global drain select line GDSL, and source select lines SSL2-SSLJ are also the global source select line. (GSSL). The local word lines WL21-WL2J,..., WLK1-WLKJ of the memory cell blocks MB2-MBK are all separated from the global word lines GWL1-GWLJ. Accordingly, the local word lines WL21-WL2J,..., WLK1-WLKJ are bulk voltages of a high voltage (eg, 20V) level applied to memory cells of the memory cell blocks MB2-MBK. Boosted by VCB). As a result, a boosting voltage VBST is generated in the local word lines WL21-WL2J,..., WLK1-WLKJ, which is close to the bulk voltage VCC. Here, the NMOS transistors G21 connected between the local word lines WL21-WL2J,..., WLK1-WLKJ of the memory cell blocks MB2-MBK and the global word lines GWL1-GWLJ. The operation of -G2J, ..., GK1-GKJ) will be described in more detail with reference to FIGS. 5A and 5B. 5A and 5B show a cross-sectional view of the NMOS transistor GK1 and its energy potential. Since the operations of the NMOS transistors G21-G2J,..., GK2-GKJ are similar to those of the NMOS transistor GK1, detailed descriptions of the operations will be omitted.

FIG. 8A is a cross-sectional view of an NMOS transistor GK1, which is a switching element connected to the local word line WLK1 of the memory cell block MBK. The word line bias voltage VWT1 having a positive value is input to the source 72 of the NMOS transistor GK1, and a block selection signal having a low (eg, 0V) level is input to the gate 74. BSELK) is input. The boosting voltage VBST is input to the drain 73 of the NMOS transistor GK1. Since the block select signal BSELK is at a low level, the NMOS transistor GK1 is turned off. In addition, since the word line bias voltage VWT1 has a positive value, as shown in FIG. 8B, the energy potential of the region of the source 72 is reduced as in Ev2. Therefore, the amount of electrons flowing from the source 72 to the substrate 71 is reduced, and the amount of electrons flowing into the local word line WLK1 connected to the drain 73 is reduced. As a result, since the leakage current generated in the NMOS transistor GK is reduced to maintain the local word line WLK1 at the boosting voltage VBST level, data of the memory cells connected to the local word line WLK1 may be reduced. It is not erased.

On the other hand, in contrast to the above, when the word line bias voltage VWT1 of 0 V is input to the source 72, as shown in FIG. 8B, the energy potential of the region of the source 72 increases to Ev1. Done. Therefore, the amount of electrons flowing from the source 72 to the substrate 71 is increased, so that the amount of leakage current of the NMOS transistor GK1 is increased. Therefore, in order to reduce the leakage current of the NMOS transistor GK1, the energy potential of the source 72 region needs to be reduced.

After performing the erase operation under the conditions described above, it is checked whether all memory cells of the block in which the erase operation has been performed are normally erased. This may be confirmed as data output from the page buffer 170 through the Y-decoder 180. For example, after a read operation is performed in units of strings while 0 V is applied to all word lines, when the data output through the Y-decoder 180 is '1', it is determined that the erase operation is normally performed. When the '0' data is output, it may be determined that there is a memory cell in which an erase operation is not normally performed. Conventionally, when a defective cell exists as in the latter case, the corresponding block is not treated as an invalidated block, and thus the data storage capacity is reduced. However, in the present invention, the erase operation is repeated by increasing the voltage difference between the word line and the bulk, thereby minimizing the occurrence of an invalidated block. The process of re-erasing the erase operation by adjusting the voltage difference is described in detail as follows.

9A to 9C are waveform diagrams for describing a first exemplary embodiment in which a voltage is applied to a global word line and a P well during an erase operation in FIG. 5. 10A to 10C are waveform diagrams for describing a second exemplary embodiment in which a voltage is applied to a global word line and a P well during an erase operation in FIG. 5.

Referring to FIG. 9A, a bulk voltage VCB having a predetermined level of an erase voltage VWTJ having a positive value is applied to a global word line GWL and a bulk PWELL that is 15V or more higher than the erase voltage VWTJ. After applying, erase operation is performed. When the erase operation is completed, the erase output operation detects data output through the Y-decoder 180 to determine whether there is a memory cell in which the erase operation is not normally performed. Data output through the Y-decoder 180 is input to the second bias voltage generator 60 and the bulk voltage generator 40, respectively, to generate the erase voltage VWTJ.

When there is a memory cell in which an erase operation is not performed, the second bias voltage generator 60 lowers the level of the erase voltage VWTJ and applies it to the global word line GWL. As a result, the voltage difference between the global word line GWL and the bulk PWELL increases. The erase operation is performed again while the voltage difference is increased. In addition, it is again determined whether there is a memory cell in which the erase operation is not normally performed, and if there is another memory cell in which the erase operation is not performed again, the second bias voltage generator 60 performs the erase voltage VWTJ to further increase the voltage difference. The level of is lowered by 0.1V to 0.5V and applied to the global word line GWL. The erase method is called an incremental stepping pulse erase (ISPE) method, and the erase operation is performed again by increasing the voltage difference using the ISPE method. If all memory cells are normally erased in the process of performing the erase operation again, the erase operation is stopped. However, if a bad memory cell exists even after the erase operation is repeated a predetermined number of times, the block is treated as an invalid block. At this time, the number of times to perform the erase operation can be changed according to the design matter.

In the above, when the erase operation is performed again, the voltage difference between the word line and the bulk is increased by lowering the level of the erase voltage VWTJ applied to the global word line GWL. However, as shown in FIG. 8B, the bulk voltage generator 40 is used. The level of the bulk voltage VCC may be increased by 0.5 V to 1 V to increase the voltage difference between the word line and the bulk. In addition, as shown in FIG. 8C, while the second bias voltage generator 60 lowers the erase voltage VWTJ, the bulk voltage generator 40 simultaneously raises the bulk voltage VCC, thereby causing a voltage difference between the word line and the bulk. You can also increase it.

In the above, the erase voltage VWTJ is first lowered functionally or the bulk voltage VBC is first functionally increased. However, as shown in FIGS. 10A to 10C, the erase voltage VWTJ may be exponentially lowered or the bulk voltage VCC may be exponentially increased. In addition, the erase voltage VWTJ may be lowered quadratically or the bulk voltage VCC may be quadraticly increased.

Through the above method, the present invention minimizes the occurrence of the invalidated block and at the same time reduces the threshold voltage due to the shallow erase phenomenon in the non-selected block in which the erase operation is not performed, or repeatedly performs the erase operation. Therefore, the occurrence of fast program or slow erase can be suppressed.

11 is a characteristic graph for comparing changes in threshold voltages of unselected blocks during an erase operation.

Referring to FIG. 11, since a leakage current occurs in a switching element (G1J in FIG. 5; J is an integer) in the related art, an induced voltage on a word line is gradually lowered to prevent an erase operation in an unselected block, thereby eliminating an erase operation. This shallow erase erasure occurred. As a result, the threshold voltage of the memory cell is lowered in the non-selected block. However, in the present invention, in order to prevent leakage current from occurring in the switching element (G1J in FIG. 5, J is an integer), an erase operation is performed in a state in which an erase voltage of positive potential is applied to a global word line. There is little occurrence of shallow erasure at. As a result, the amount of change in the threshold voltage can be minimized.

12 is a characteristic graph illustrating a slow erasure characteristic and a fast program characteristic according to the number of erase operations in the present invention.

Referring to FIG. 12, in the first erase operation, the voltage difference between the word line and the bulk is maintained to the extent that the erase operation can be normally performed, and if the erase operation is not normally performed, the voltage difference is gradually increased to perform the erase operation. However, even if the erase operation is accumulated hundreds of thousands of times, the fast program and slow erasure occur within approximately 0.5V. Considering the fact that the conventional fast program phenomenon and the slow erasure phenomenon shown in FIG. 2 occur higher than at least 2V, it can be seen that the fast program phenomenon and the slow erasure phenomenon hardly occur in the present invention.

According to the above, the present invention can obtain the following effects.

First, since a voltage higher than 0 V is applied to the global word line during the erase operation, leakage current may be prevented from occurring in the switching device connected between the global word line and the local word line. Therefore, the voltage induced in the word line of the non-selection block in which the erase operation is not performed may be prevented from being lowered, thereby preventing the occurrence of shallow erase in the non-selection block.

Second, in the conventional operation in which an erase operation is performed after the erase operation is performed, if a memory cell in which the erase operation is not normally performed, the corresponding block is not treated as an invalid block. This reduced data storage capacity. However, in the present invention, when there is a memory cell that is not normally performed, the erase operation is performed by increasing the voltage difference between the word line and the bulk, thereby minimizing the occurrence of the invalidated block and minimizing the reduction of the data storage capacity. Can be.

Third, when the erase operation is performed in a state where the voltage difference between the word line and the bulk is high from the beginning, electrons may be trapped or stressed in the tunnel oxide layer, thereby deteriorating electrical characteristics of the memory cell. However, the present invention performs the erase operation with only the minimum voltage difference for the erase operation, and if the erase operation fails, the erase operation is repeated by increasing the voltage difference, so that electrons are trapped or stressed in the tunnel oxide layer. Minimization can increase the lifespan of a memory cell.

Fourth, the present invention performs the erase operation with the minimum voltage difference during the first erase operation, and if the failure occurs, the erase operation is performed by increasing the voltage difference, so that even if the number of read / erase operations accumulates more than hundreds of thousands of times, The occurrence of the erasure phenomenon can be suppressed to the maximum.

Through the above operation, it is possible to improve the reliability of the erase operation, minimize the occurrence of defects, and increase the life of the device.

Claims (32)

First and second memory cell blocks each including a local drain select line, a local source select line, and a local word line to which a plurality of memory cells are connected; A block selector for connecting the local wordlines with global wordlines according to a block select signal; Applying a first erase voltage to the global word lines during a first erase operation during an erase operation, and when the first erase operation is abnormally completed, a second erase at a level different from the first erase voltage during a new second erase operation. A first bias voltage generator for applying a voltage to the global word lines; And And a bulk voltage generator for applying a bulk voltage to the bulk of the memory cells during an erase operation. The method of claim 1, The erase voltage applied to the global word lines is lowered every new erase operation, and the erase operation is terminated after a predetermined number of times. The method of claim 1, And the first bias voltage generator generates the erase voltage such that a voltage difference between the local word line and the bulk becomes 15V during the first erase operation. The method of claim 3, wherein And an erase voltage applied to the global word lines decreases linearly, quadratic, or exponentially within a range of 0.1V to 0.5V each time a new erase operation is performed. The method of claim 1, A page buffer for reading data stored in the memory cells; And And a Y-decoder for outputting data stored in the page buffer to a data input / output buffer and the first bias voltage generator. The method of claim 4, wherein And the first bias voltage generator changes the first erase voltage to the second erase voltage according to data output from the Y-decoder. Memory cell blocks each including a local drain select line, a local source select line, and a local word line to which a plurality of memory cells are connected; A block selector for connecting the local wordlines with global wordlines according to a block select signal; A first bias voltage generator for applying a positive potential erase voltage to the global word lines during an erase operation; And Applying a first bulk voltage to the bulk of the memory cells during a first erase operation during an erase operation, and when the first erase operation is abnormally completed, a second erase at a level different from the first erase voltage during a new second erase operation. And a bulk voltage generator for applying a voltage to said bulk. The method of claim 7, wherein And the first erase operation is determined to be abnormally completed unless all of the memory cells selected for the erase operation are erased by the first erase operation. The method of claim 7, wherein And the bulk voltage generator generates the first bulk voltage such that a voltage difference between the local word line and the bulk becomes 15V during an initial erase operation. The method of claim 9, And the bulk voltage generator increases the first bulk voltage in a primary, quadratic, or exponential function within a range of 0.5V to 1V each time a new erase operation is performed. The method of claim 7, wherein A page buffer for reading data stored in the memory cells; And And a Y-decoder for outputting data stored in the page buffer to a data input / output buffer and the bulk voltage generator. The method of claim 11, And the bulk voltage generator generates the second bulk voltage to perform the second erase operation according to data output from the Y-decoder. Memory cell blocks each including a local drain select line, a local source select line, and a local word line to which a plurality of memory cells are connected; A block selector for connecting the local wordlines with global wordlines according to a block select signal; A first voltage is applied to the global word lines during an erase operation, and when there is an unerased memory cell, the first voltage is applied to the global word line by lowering the level of the erase voltage to re-execute the erase operation. A bias voltage generator; And A flash including a bulk voltage generator for applying a bulk voltage to the bulk of the memory cells during an erase operation, and applying the bulk voltage to the bulk by increasing the level of the bulk voltage to re-execute an erase operation if an unerased memory cell exists. Memory device. The method of claim 13, The first bias voltage generator and the bulk voltage generator generate the erase voltage and the bulk voltage so that a voltage difference between the local word line and the bulk becomes 15V during an initial erase operation, and when the erase operation is performed again. And increasing the bulk voltage while reducing the level of the erase voltage such that the voltage difference between the local word line and the bulk is greater than 15V. The method of claim 13, The first bias voltage generator first decreases the erase voltage in units of 0.1 V to 0.5 V, or decreases the function secondarily or exponentially, and the bulk voltage generator reduces the bulk voltage by 0.5 V. To increase or decrease exponentially in a first function, or in a second function. The method of claim 13, A page buffer for reading data stored in the memory cells; And And a Y-decoder for outputting data stored in the page buffer to a data input / output buffer, the bulk voltage generator, and the first bias voltage generator. The method of claim 16, When the first bias voltage generator and the bulk voltage generator detect data indicating an unerased state among the data output from the Y-decoder, the first bias voltage generator and the bulk voltage generator lower the level of the erase voltage and re-enable the bulk voltage, respectively, in order to perform the erase operation. Increase the level of flash memory device. The method according to any one of claims 1, 7, and 13, And an X-decoder for decoding a row address signal and outputting the block selection signal to the high voltage generator. The method according to any one of claims 1, 7, and 13, And a second bias voltage generator configured to apply a predetermined operating voltage to the local drain select line and the local source select line according to one of a program, a read, and an erase operation. 18. The method of claim 6 or 17, wherein the first bias voltage generation, A first pump circuit for generating read voltages required for read operation in response to a read command; A second pump circuit for generating program voltages required for a program operation in response to the program command; A third pump circuit configured to generate the erase voltage in response to the erase command, and to lower the level of the erase voltage when the data indicating the unerased state is detected among the data output from the Y-decoder; And And a bias voltage selector configured to select the read voltages, the program voltages, or the erase voltage in response to an operation command signal, and output the selected voltages to the global word lines, respectively. The method of claim 20, wherein the bias voltage selector, A selection signal generator for generating selection signals based on the operation command signal; And A flash memory connected to the global word lines, the selection circuits respectively outputting one of the read voltages, the program voltages, and the erase voltage to a corresponding global word line in response to the selection signals; Device. Electrically connecting local word lines and global word lines of the selected block according to the block selection signal; Applying an erase voltage of a positive potential to the global word line according to an erase command and applying a bulk voltage higher than the erase voltage to a bulk of a memory cell to perform an erase operation; A verification step of determining whether the erase operation is normally performed; And And resetting the erase operation by lowering the level of the erase voltage such that the voltage difference between the local word line and the bulk becomes larger when the erase operation is not normally performed. The method of claim 22, The verifying step and the re-implementing of the erase operation may be repeated by a predetermined number of times while lowering the erase voltage by a predetermined level, and if the erase operation is not performed normally until a predetermined number of times, the flash may be processed as an invalid block. A method of controlling an erase operation of a memory device. Electrically connecting local word lines and global word lines of the selected block according to the block selection signal; Applying an erase voltage of a positive potential to the global word line according to an erase command and applying a bulk voltage higher than the erase voltage to a bulk of a memory cell to perform an erase operation; A verification step of determining whether the erase operation is normally performed; And And performing an erase operation by raising the level of the bulk voltage so that the voltage difference between the local word line and the bulk becomes larger when the erase operation is not normally performed. The method of claim 24, The verifying step and the re-implementing of the erase operation may be repeated by a predetermined number of times while increasing the bulk voltage by a predetermined level. If the erase operation is not performed by a predetermined number of times, the flash is processed as an invalid block. A method of controlling an erase operation of a memory device. Electrically connecting local word lines and global word lines of the selected block according to the block selection signal; Applying an erase voltage of a positive potential to the global word line according to an erase command and applying a bulk voltage higher than the erase voltage to a bulk of a memory cell to perform an erase operation; A verification step of determining whether the erase operation is normally performed; And If the erase operation is not performed normally, simultaneously adjusting the levels of the erase voltage and the bulk voltage so that the voltage difference between the local word line and the bulk becomes larger and performing the erase operation again. Method of controlling erase operation. The method of claim 26, The verifying step and the re-implementing of the erase operation may be repeated a predetermined number of times by lowering the level of the erase voltage by a predetermined level and increasing the bulk voltage by a predetermined level. An erase operation control method of a flash memory device which processes the block as an invalid block. The method according to any one of claims 22 to 27, And setting the levels of the erase voltage and the bulk voltage such that the voltage difference between the local word line and the bulk is at least 15V. The method according to any one of claims 22, 23, 26 and 27, And the erase voltage is lowered in units of 0.1V to 0.5V so that the voltage difference increases in a range where a voltage difference between the local word line and the bulk becomes at least 15V. The method according to any one of claims 22, 23, 26 and 27, And the erase voltage is exponentially lowered so that the voltage difference increases in a range where the voltage difference between the local word line and the bulk becomes at least 15V. The method according to any one of claims 24 to 27, And the bulk voltage is increased by 0.5V to 1V so that the voltage difference increases in a range where a voltage difference between the local word line and the bulk becomes at least 15V. The method according to any one of claims 24 to 27, And the bulk voltage is exponentially increased such that the voltage difference increases in a range where a voltage difference between the local word line and the bulk becomes at least 15V.

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